1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33 #include <target/cortex_m.h>
35 /* stm32lx flash register locations */
37 #define FLASH_ACR 0x00
38 #define FLASH_PECR 0x04
39 #define FLASH_PDKEYR 0x08
40 #define FLASH_PEKEYR 0x0C
41 #define FLASH_PRGKEYR 0x10
42 #define FLASH_OPTKEYR 0x14
44 #define FLASH_OBR 0x1C
45 #define FLASH_WRPR 0x20
48 #define FLASH_ACR__LATENCY (1<<0)
49 #define FLASH_ACR__PRFTEN (1<<1)
50 #define FLASH_ACR__ACC64 (1<<2)
51 #define FLASH_ACR__SLEEP_PD (1<<3)
52 #define FLASH_ACR__RUN_PD (1<<4)
55 #define FLASH_PECR__PELOCK (1<<0)
56 #define FLASH_PECR__PRGLOCK (1<<1)
57 #define FLASH_PECR__OPTLOCK (1<<2)
58 #define FLASH_PECR__PROG (1<<3)
59 #define FLASH_PECR__DATA (1<<4)
60 #define FLASH_PECR__FTDW (1<<8)
61 #define FLASH_PECR__ERASE (1<<9)
62 #define FLASH_PECR__FPRG (1<<10)
63 #define FLASH_PECR__EOPIE (1<<16)
64 #define FLASH_PECR__ERRIE (1<<17)
65 #define FLASH_PECR__OBL_LAUNCH (1<<18)
68 #define FLASH_SR__BSY (1<<0)
69 #define FLASH_SR__EOP (1<<1)
70 #define FLASH_SR__ENDHV (1<<2)
71 #define FLASH_SR__READY (1<<3)
72 #define FLASH_SR__WRPERR (1<<8)
73 #define FLASH_SR__PGAERR (1<<9)
74 #define FLASH_SR__SIZERR (1<<10)
75 #define FLASH_SR__OPTVERR (1<<11)
78 #define PEKEY1 0x89ABCDEF
79 #define PEKEY2 0x02030405
80 #define PRGKEY1 0x8C9DAEBF
81 #define PRGKEY2 0x13141516
82 #define OPTKEY1 0xFBEAD9C8
83 #define OPTKEY2 0x24252627
86 #define DBGMCU_IDCODE 0xE0042000
87 #define DBGMCU_IDCODE_L0 0x40015800
90 #define FLASH_SECTOR_SIZE 4096
91 #define FLASH_BANK0_ADDRESS 0x08000000
94 #define OPTION_BYTES_ADDRESS 0x1FF80000
96 #define OPTION_BYTE_0_PR1 0xFFFF0000
97 #define OPTION_BYTE_0_PR0 0xFF5500AA
99 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
100 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
101 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
102 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
103 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
104 static int stm32lx_lock(struct flash_bank
*bank
);
105 static int stm32lx_unlock(struct flash_bank
*bank
);
106 static int stm32lx_mass_erase(struct flash_bank
*bank
);
107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank
*bank
, int timeout
);
108 static int stm32lx_update_part_info(struct flash_bank
*bank
, uint16_t flash_size_in_kb
);
115 struct stm32lx_part_info
{
117 const char *device_str
;
118 const struct stm32lx_rev
*revs
;
120 unsigned int page_size
;
121 unsigned int pages_per_sector
;
122 uint16_t max_flash_size_kb
;
123 uint16_t first_bank_size_kb
; /* used when has_dual_banks is true */
126 uint32_t flash_base
; /* Flash controller registers location */
127 uint32_t fsize_base
; /* Location of FSIZE register */
130 struct stm32lx_flash_bank
{
133 uint32_t user_bank_size
;
136 struct stm32lx_part_info part_info
;
139 static const struct stm32lx_rev stm32_416_revs
[] = {
140 { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
142 static const struct stm32lx_rev stm32_417_revs
[] = {
143 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
145 static const struct stm32lx_rev stm32_425_revs
[] = {
146 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
148 static const struct stm32lx_rev stm32_427_revs
[] = {
149 { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },
151 static const struct stm32lx_rev stm32_429_revs
[] = {
152 { 0x1000, "A" }, { 0x1018, "Z" },
154 static const struct stm32lx_rev stm32_436_revs
[] = {
155 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
157 static const struct stm32lx_rev stm32_437_revs
[] = {
160 static const struct stm32lx_rev stm32_447_revs
[] = {
161 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
163 static const struct stm32lx_rev stm32_457_revs
[] = {
164 { 0x1000, "A" }, { 0x1008, "Z" },
167 static const struct stm32lx_part_info stm32lx_parts
[] = {
170 .revs
= stm32_416_revs
,
171 .num_revs
= ARRAY_SIZE(stm32_416_revs
),
172 .device_str
= "STM32L1xx (Cat.1 - Low/Medium Density)",
174 .pages_per_sector
= 16,
175 .max_flash_size_kb
= 128,
176 .has_dual_banks
= false,
177 .flash_base
= 0x40023C00,
178 .fsize_base
= 0x1FF8004C,
182 .revs
= stm32_417_revs
,
183 .num_revs
= ARRAY_SIZE(stm32_417_revs
),
184 .device_str
= "STM32L0xx (Cat. 3)",
186 .pages_per_sector
= 32,
187 .max_flash_size_kb
= 64,
188 .has_dual_banks
= false,
189 .flash_base
= 0x40022000,
190 .fsize_base
= 0x1FF8007C,
194 .revs
= stm32_425_revs
,
195 .num_revs
= ARRAY_SIZE(stm32_425_revs
),
196 .device_str
= "STM32L0xx (Cat. 2)",
198 .pages_per_sector
= 32,
199 .max_flash_size_kb
= 32,
200 .has_dual_banks
= false,
201 .flash_base
= 0x40022000,
202 .fsize_base
= 0x1FF8007C,
206 .revs
= stm32_427_revs
,
207 .num_revs
= ARRAY_SIZE(stm32_427_revs
),
208 .device_str
= "STM32L1xx (Cat.3 - Medium+ Density)",
210 .pages_per_sector
= 16,
211 .max_flash_size_kb
= 256,
212 .has_dual_banks
= false,
213 .flash_base
= 0x40023C00,
214 .fsize_base
= 0x1FF800CC,
218 .revs
= stm32_429_revs
,
219 .num_revs
= ARRAY_SIZE(stm32_429_revs
),
220 .device_str
= "STM32L1xx (Cat.2)",
222 .pages_per_sector
= 16,
223 .max_flash_size_kb
= 128,
224 .has_dual_banks
= false,
225 .flash_base
= 0x40023C00,
226 .fsize_base
= 0x1FF8004C,
230 .revs
= stm32_436_revs
,
231 .num_revs
= ARRAY_SIZE(stm32_436_revs
),
232 .device_str
= "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
234 .pages_per_sector
= 16,
235 .max_flash_size_kb
= 384,
236 .first_bank_size_kb
= 192,
237 .has_dual_banks
= true,
238 .flash_base
= 0x40023C00,
239 .fsize_base
= 0x1FF800CC,
243 .revs
= stm32_437_revs
,
244 .num_revs
= ARRAY_SIZE(stm32_437_revs
),
245 .device_str
= "STM32L1xx (Cat.5/Cat.6)",
247 .pages_per_sector
= 16,
248 .max_flash_size_kb
= 512,
249 .first_bank_size_kb
= 0, /* determined in runtime */
250 .has_dual_banks
= true,
251 .flash_base
= 0x40023C00,
252 .fsize_base
= 0x1FF800CC,
256 .revs
= stm32_447_revs
,
257 .num_revs
= ARRAY_SIZE(stm32_447_revs
),
258 .device_str
= "STM32L0xx (Cat.5)",
260 .pages_per_sector
= 32,
261 .max_flash_size_kb
= 192,
262 .first_bank_size_kb
= 0, /* determined in runtime */
263 .has_dual_banks
= false, /* determined in runtime */
264 .flash_base
= 0x40022000,
265 .fsize_base
= 0x1FF8007C,
269 .revs
= stm32_457_revs
,
270 .num_revs
= ARRAY_SIZE(stm32_457_revs
),
271 .device_str
= "STM32L0xx (Cat.1)",
273 .pages_per_sector
= 32,
274 .max_flash_size_kb
= 16,
275 .has_dual_banks
= false,
276 .flash_base
= 0x40022000,
277 .fsize_base
= 0x1FF8007C,
281 /* flash bank stm32lx <base> <size> 0 0 <target#>
283 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
285 struct stm32lx_flash_bank
*stm32lx_info
;
287 return ERROR_COMMAND_SYNTAX_ERROR
;
289 /* Create the bank structure */
290 stm32lx_info
= calloc(1, sizeof(*stm32lx_info
));
292 /* Check allocation */
294 LOG_ERROR("failed to allocate bank structure");
298 bank
->driver_priv
= stm32lx_info
;
300 stm32lx_info
->probed
= false;
301 stm32lx_info
->user_bank_size
= bank
->size
;
303 /* the stm32l erased value is 0x00 */
304 bank
->default_padded_value
= bank
->erased_value
= 0x00;
309 COMMAND_HANDLER(stm32lx_handle_mass_erase_command
)
312 return ERROR_COMMAND_SYNTAX_ERROR
;
314 struct flash_bank
*bank
;
315 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
316 if (retval
!= ERROR_OK
)
319 retval
= stm32lx_mass_erase(bank
);
320 if (retval
== ERROR_OK
)
321 command_print(CMD
, "stm32lx mass erase complete");
323 command_print(CMD
, "stm32lx mass erase failed");
328 COMMAND_HANDLER(stm32lx_handle_lock_command
)
331 return ERROR_COMMAND_SYNTAX_ERROR
;
333 struct flash_bank
*bank
;
334 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
335 if (retval
!= ERROR_OK
)
338 retval
= stm32lx_lock(bank
);
340 if (retval
== ERROR_OK
)
341 command_print(CMD
, "STM32Lx locked, takes effect after power cycle.");
343 command_print(CMD
, "STM32Lx lock failed");
348 COMMAND_HANDLER(stm32lx_handle_unlock_command
)
351 return ERROR_COMMAND_SYNTAX_ERROR
;
353 struct flash_bank
*bank
;
354 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
355 if (retval
!= ERROR_OK
)
358 retval
= stm32lx_unlock(bank
);
360 if (retval
== ERROR_OK
)
361 command_print(CMD
, "STM32Lx unlocked, takes effect after power cycle.");
363 command_print(CMD
, "STM32Lx unlock failed");
368 static int stm32lx_protect_check(struct flash_bank
*bank
)
371 struct target
*target
= bank
->target
;
372 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
377 * Read the WRPR word, and check each bit (corresponding to each
380 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_WRPR
,
382 if (retval
!= ERROR_OK
)
385 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
387 bank
->sectors
[i
].is_protected
= 1;
389 bank
->sectors
[i
].is_protected
= 0;
394 static int stm32lx_erase(struct flash_bank
*bank
, unsigned int first
,
400 * It could be possible to do a mass erase if all sectors must be
401 * erased, but it is not implemented yet.
404 if (bank
->target
->state
!= TARGET_HALTED
) {
405 LOG_ERROR("Target not halted");
406 return ERROR_TARGET_NOT_HALTED
;
410 * Loop over the selected sectors and erase them
412 for (unsigned int i
= first
; i
<= last
; i
++) {
413 retval
= stm32lx_erase_sector(bank
, i
);
414 if (retval
!= ERROR_OK
)
416 bank
->sectors
[i
].is_erased
= 1;
421 static int stm32lx_write_half_pages(struct flash_bank
*bank
, const uint8_t *buffer
,
422 uint32_t offset
, uint32_t count
)
424 struct target
*target
= bank
->target
;
425 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
427 uint32_t hp_nb
= stm32lx_info
->part_info
.page_size
/ 2;
428 uint32_t buffer_size
= 16384;
429 struct working_area
*write_algorithm
;
430 struct working_area
*source
;
431 uint32_t address
= bank
->base
+ offset
;
433 struct reg_param reg_params
[3];
434 struct armv7m_algorithm armv7m_info
;
436 int retval
= ERROR_OK
;
438 static const uint8_t stm32lx_flash_write_code
[] = {
439 #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
442 /* Make sure we're performing a half-page aligned write. */
444 LOG_ERROR("The byte count must be %" PRIu32
"B-aligned but count is %" PRIu32
"B)", hp_nb
, count
);
448 /* flash write code */
449 if (target_alloc_working_area(target
, sizeof(stm32lx_flash_write_code
),
450 &write_algorithm
) != ERROR_OK
) {
451 LOG_DEBUG("no working area for block memory writes");
452 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
455 /* Write the flashing code */
456 retval
= target_write_buffer(target
,
457 write_algorithm
->address
,
458 sizeof(stm32lx_flash_write_code
),
459 stm32lx_flash_write_code
);
460 if (retval
!= ERROR_OK
) {
461 target_free_working_area(target
, write_algorithm
);
465 /* Allocate half pages memory */
466 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
467 if (buffer_size
> 1024)
472 if (buffer_size
<= stm32lx_info
->part_info
.page_size
) {
473 /* we already allocated the writing code, but failed to get a
474 * buffer, free the algorithm */
475 target_free_working_area(target
, write_algorithm
);
477 LOG_WARNING("no large enough working area available, can't do block memory writes");
478 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
482 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
483 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
484 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
485 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
486 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
488 /* Enable half-page write */
489 retval
= stm32lx_enable_write_half_page(bank
);
490 if (retval
!= ERROR_OK
) {
491 target_free_working_area(target
, source
);
492 target_free_working_area(target
, write_algorithm
);
494 destroy_reg_param(®_params
[0]);
495 destroy_reg_param(®_params
[1]);
496 destroy_reg_param(®_params
[2]);
500 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
503 /* something is very wrong if armv7m is NULL */
504 LOG_ERROR("unable to get armv7m target");
508 /* save any DEMCR flags and configure target to catch any Hard Faults */
509 uint32_t demcr_save
= armv7m
->demcr
;
510 armv7m
->demcr
= VC_HARDERR
;
512 /* Loop while there are bytes to write */
515 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
517 /* Write the next half pages */
518 retval
= target_write_buffer(target
, source
->address
, this_count
, buffer
);
519 if (retval
!= ERROR_OK
)
522 /* 4: Store useful information in the registers */
523 /* the destination address of the copy (R0) */
524 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
525 /* The source address of the copy (R1) */
526 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
527 /* The length of the copy (R2) */
528 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
530 /* 5: Execute the bunch of code */
531 retval
= target_run_algorithm(target
, 0, NULL
,
532 ARRAY_SIZE(reg_params
), reg_params
,
533 write_algorithm
->address
, 0, 10000, &armv7m_info
);
534 if (retval
!= ERROR_OK
)
537 /* check for Hard Fault */
538 if (armv7m
->exception_number
== 3)
541 /* 6: Wait while busy */
542 retval
= stm32lx_wait_until_bsy_clear(bank
);
543 if (retval
!= ERROR_OK
)
546 buffer
+= this_count
;
547 address
+= this_count
;
551 /* restore previous flags */
552 armv7m
->demcr
= demcr_save
;
554 if (armv7m
->exception_number
== 3) {
556 /* the stm32l15x devices seem to have an issue when blank.
557 * if a ram loader is executed on a blank device it will
558 * Hard Fault, this issue does not happen for a already programmed device.
559 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
560 * The workaround of handling the Hard Fault exception does work, but makes the
561 * loader more complicated, as a compromise we manually write the pages, programming time
562 * is reduced by 50% using this slower method.
565 LOG_WARNING("Couldn't use loader, falling back to page memory writes");
569 this_count
= (count
> hp_nb
) ? hp_nb
: count
;
571 /* Write the next half pages */
572 retval
= target_write_buffer(target
, address
, this_count
, buffer
);
573 if (retval
!= ERROR_OK
)
576 /* Wait while busy */
577 retval
= stm32lx_wait_until_bsy_clear(bank
);
578 if (retval
!= ERROR_OK
)
581 buffer
+= this_count
;
582 address
+= this_count
;
587 if (retval
== ERROR_OK
)
588 retval
= stm32lx_lock_program_memory(bank
);
590 target_free_working_area(target
, source
);
591 target_free_working_area(target
, write_algorithm
);
593 destroy_reg_param(®_params
[0]);
594 destroy_reg_param(®_params
[1]);
595 destroy_reg_param(®_params
[2]);
600 static int stm32lx_write(struct flash_bank
*bank
, const uint8_t *buffer
,
601 uint32_t offset
, uint32_t count
)
603 struct target
*target
= bank
->target
;
604 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
606 uint32_t hp_nb
= stm32lx_info
->part_info
.page_size
/ 2;
607 uint32_t halfpages_number
;
608 uint32_t bytes_remaining
= 0;
609 uint32_t address
= bank
->base
+ offset
;
610 uint32_t bytes_written
= 0;
613 if (bank
->target
->state
!= TARGET_HALTED
) {
614 LOG_ERROR("Target not halted");
615 return ERROR_TARGET_NOT_HALTED
;
619 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte alignment", offset
);
620 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
623 retval
= stm32lx_unlock_program_memory(bank
);
624 if (retval
!= ERROR_OK
)
627 /* first we need to write any unaligned head bytes up to
628 * the next 128 byte page */
631 bytes_remaining
= MIN(count
, hp_nb
- (offset
% hp_nb
));
633 while (bytes_remaining
> 0) {
634 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
636 /* copy remaining bytes into the write buffer */
637 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
638 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
640 retval
= target_write_buffer(target
, address
, 4, value
);
641 if (retval
!= ERROR_OK
)
642 goto reset_pg_and_lock
;
644 bytes_written
+= bytes_to_write
;
645 bytes_remaining
-= bytes_to_write
;
648 retval
= stm32lx_wait_until_bsy_clear(bank
);
649 if (retval
!= ERROR_OK
)
650 goto reset_pg_and_lock
;
653 offset
+= bytes_written
;
654 count
-= bytes_written
;
656 /* this should always pass this check here */
657 assert((offset
% hp_nb
) == 0);
659 /* calculate half pages */
660 halfpages_number
= count
/ hp_nb
;
662 if (halfpages_number
) {
663 retval
= stm32lx_write_half_pages(bank
, buffer
+ bytes_written
, offset
, hp_nb
* halfpages_number
);
664 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
665 /* attempt slow memory writes */
666 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
667 halfpages_number
= 0;
669 if (retval
!= ERROR_OK
)
674 /* write any remaining bytes */
675 uint32_t page_bytes_written
= hp_nb
* halfpages_number
;
676 bytes_written
+= page_bytes_written
;
677 address
+= page_bytes_written
;
678 bytes_remaining
= count
- page_bytes_written
;
680 retval
= stm32lx_unlock_program_memory(bank
);
681 if (retval
!= ERROR_OK
)
684 while (bytes_remaining
> 0) {
685 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
687 /* copy remaining bytes into the write buffer */
688 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
689 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
691 retval
= target_write_buffer(target
, address
, 4, value
);
692 if (retval
!= ERROR_OK
)
693 goto reset_pg_and_lock
;
695 bytes_written
+= bytes_to_write
;
696 bytes_remaining
-= bytes_to_write
;
699 retval
= stm32lx_wait_until_bsy_clear(bank
);
700 if (retval
!= ERROR_OK
)
701 goto reset_pg_and_lock
;
705 retval2
= stm32lx_lock_program_memory(bank
);
706 if (retval
== ERROR_OK
)
712 static int stm32lx_read_id_code(struct target
*target
, uint32_t *id
)
714 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
716 if (armv7m
->arm
.arch
== ARM_ARCH_V6M
)
717 retval
= target_read_u32(target
, DBGMCU_IDCODE_L0
, id
);
719 /* read stm32 device id register */
720 retval
= target_read_u32(target
, DBGMCU_IDCODE
, id
);
724 static int stm32lx_probe(struct flash_bank
*bank
)
726 struct target
*target
= bank
->target
;
727 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
728 uint16_t flash_size_in_kb
;
730 uint32_t base_address
= FLASH_BANK0_ADDRESS
;
731 uint32_t second_bank_base
;
734 stm32lx_info
->probed
= false;
736 int retval
= stm32lx_read_id_code(bank
->target
, &device_id
);
737 if (retval
!= ERROR_OK
)
740 stm32lx_info
->idcode
= device_id
;
742 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
744 for (n
= 0; n
< ARRAY_SIZE(stm32lx_parts
); n
++) {
745 if ((device_id
& 0xfff) == stm32lx_parts
[n
].id
) {
746 stm32lx_info
->part_info
= stm32lx_parts
[n
];
751 if (n
== ARRAY_SIZE(stm32lx_parts
)) {
752 LOG_ERROR("Cannot identify target as an STM32 L0 or L1 family device.");
755 LOG_INFO("Device: %s", stm32lx_info
->part_info
.device_str
);
758 stm32lx_info
->flash_base
= stm32lx_info
->part_info
.flash_base
;
760 /* Get the flash size from target. */
761 retval
= target_read_u16(target
, stm32lx_info
->part_info
.fsize_base
,
764 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
765 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
767 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x436) {
768 if (flash_size_in_kb
== 0)
769 flash_size_in_kb
= 384;
770 else if (flash_size_in_kb
== 1)
771 flash_size_in_kb
= 256;
774 /* 0x429 devices only use the lowest 8 bits of the flash size register */
775 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x429) {
776 flash_size_in_kb
&= 0xff;
779 /* Failed reading flash size or flash size invalid (early silicon),
780 * default to max target family */
781 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
782 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
783 stm32lx_info
->part_info
.max_flash_size_kb
);
784 flash_size_in_kb
= stm32lx_info
->part_info
.max_flash_size_kb
;
785 } else if (flash_size_in_kb
> stm32lx_info
->part_info
.max_flash_size_kb
) {
786 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
787 flash_size_in_kb
, stm32lx_info
->part_info
.max_flash_size_kb
,
788 stm32lx_info
->part_info
.max_flash_size_kb
);
789 flash_size_in_kb
= stm32lx_info
->part_info
.max_flash_size_kb
;
792 /* Overwrite default dual-bank configuration */
793 retval
= stm32lx_update_part_info(bank
, flash_size_in_kb
);
794 if (retval
!= ERROR_OK
)
797 if (stm32lx_info
->part_info
.has_dual_banks
) {
798 /* Use the configured base address to determine if this is the first or second flash bank.
799 * Verify that the base address is reasonably correct and determine the flash bank size
801 second_bank_base
= base_address
+
802 stm32lx_info
->part_info
.first_bank_size_kb
* 1024;
803 if (bank
->base
== second_bank_base
|| !bank
->base
) {
804 /* This is the second bank */
805 base_address
= second_bank_base
;
806 flash_size_in_kb
= flash_size_in_kb
-
807 stm32lx_info
->part_info
.first_bank_size_kb
;
808 } else if (bank
->base
== base_address
) {
809 /* This is the first bank */
810 flash_size_in_kb
= stm32lx_info
->part_info
.first_bank_size_kb
;
812 LOG_WARNING("STM32L flash bank base address config is incorrect. "
813 TARGET_ADDR_FMT
" but should rather be 0x%" PRIx32
815 bank
->base
, base_address
, second_bank_base
);
818 LOG_INFO("STM32L flash has dual banks. Bank (%u) size is %dkb, base address is 0x%" PRIx32
,
819 bank
->bank_number
, flash_size_in_kb
, base_address
);
821 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32
, flash_size_in_kb
, base_address
);
824 /* if the user sets the size manually then ignore the probed value
825 * this allows us to work around devices that have a invalid flash size register value */
826 if (stm32lx_info
->user_bank_size
) {
827 flash_size_in_kb
= stm32lx_info
->user_bank_size
/ 1024;
828 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb
);
831 /* calculate numbers of sectors (4kB per sector) */
832 unsigned int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
836 bank
->size
= flash_size_in_kb
* 1024;
837 bank
->base
= base_address
;
838 bank
->num_sectors
= num_sectors
;
839 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
840 if (!bank
->sectors
) {
841 LOG_ERROR("failed to allocate bank sectors");
845 for (unsigned int i
= 0; i
< num_sectors
; i
++) {
846 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
847 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
848 bank
->sectors
[i
].is_erased
= -1;
849 bank
->sectors
[i
].is_protected
= -1;
852 stm32lx_info
->probed
= true;
857 static int stm32lx_auto_probe(struct flash_bank
*bank
)
859 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
861 if (stm32lx_info
->probed
)
864 return stm32lx_probe(bank
);
867 /* This method must return a string displaying information about the bank */
868 static int stm32lx_get_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
870 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
871 const struct stm32lx_part_info
*info
= &stm32lx_info
->part_info
;
872 uint16_t rev_id
= stm32lx_info
->idcode
>> 16;
873 const char *rev_str
= NULL
;
875 if (!stm32lx_info
->probed
) {
876 int retval
= stm32lx_probe(bank
);
877 if (retval
!= ERROR_OK
) {
878 command_print_sameline(cmd
, "Unable to find bank information.");
883 for (unsigned int i
= 0; i
< info
->num_revs
; i
++)
884 if (rev_id
== info
->revs
[i
].rev
)
885 rev_str
= info
->revs
[i
].str
;
888 command_print_sameline(cmd
, "%s - Rev: %s", info
->device_str
, rev_str
);
890 command_print_sameline(cmd
, "%s - Rev: unknown (0x%04x)", info
->device_str
, rev_id
);
896 static const struct command_registration stm32lx_exec_command_handlers
[] = {
898 .name
= "mass_erase",
899 .handler
= stm32lx_handle_mass_erase_command
,
900 .mode
= COMMAND_EXEC
,
902 .help
= "Erase entire flash device. including available EEPROM",
906 .handler
= stm32lx_handle_lock_command
,
907 .mode
= COMMAND_EXEC
,
909 .help
= "Increase the readout protection to Level 1.",
913 .handler
= stm32lx_handle_unlock_command
,
914 .mode
= COMMAND_EXEC
,
916 .help
= "Lower the readout protection from Level 1 to 0.",
918 COMMAND_REGISTRATION_DONE
921 static const struct command_registration stm32lx_command_handlers
[] = {
925 .help
= "stm32lx flash command group",
927 .chain
= stm32lx_exec_command_handlers
,
929 COMMAND_REGISTRATION_DONE
932 const struct flash_driver stm32lx_flash
= {
934 .commands
= stm32lx_command_handlers
,
935 .flash_bank_command
= stm32lx_flash_bank_command
,
936 .erase
= stm32lx_erase
,
937 .write
= stm32lx_write
,
938 .read
= default_flash_read
,
939 .probe
= stm32lx_probe
,
940 .auto_probe
= stm32lx_auto_probe
,
941 .erase_check
= default_flash_blank_check
,
942 .protect_check
= stm32lx_protect_check
,
943 .info
= stm32lx_get_info
,
944 .free_driver_priv
= default_flash_free_driver_priv
,
947 /* Static methods implementation */
948 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
950 struct target
*target
= bank
->target
;
951 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
956 * Unlocking the program memory is done by unlocking the PECR,
957 * then by writing the 2 PRGKEY to the PRGKEYR register
960 /* check flash is not already unlocked */
961 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
963 if (retval
!= ERROR_OK
)
966 if ((reg32
& FLASH_PECR__PRGLOCK
) == 0)
969 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
970 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
972 if (retval
!= ERROR_OK
)
975 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
977 if (retval
!= ERROR_OK
)
980 /* Make sure it worked */
981 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
983 if (retval
!= ERROR_OK
)
986 if (reg32
& FLASH_PECR__PELOCK
) {
987 LOG_ERROR("PELOCK is not cleared :(");
988 return ERROR_FLASH_OPERATION_FAILED
;
991 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
993 if (retval
!= ERROR_OK
)
995 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
997 if (retval
!= ERROR_OK
)
1000 /* Make sure it worked */
1001 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1003 if (retval
!= ERROR_OK
)
1006 if (reg32
& FLASH_PECR__PRGLOCK
) {
1007 LOG_ERROR("PRGLOCK is not cleared :(");
1008 return ERROR_FLASH_OPERATION_FAILED
;
1014 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
1016 struct target
*target
= bank
->target
;
1017 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1022 * Unlock the program memory, then set the FPRG bit in the PECR register.
1024 retval
= stm32lx_unlock_program_memory(bank
);
1025 if (retval
!= ERROR_OK
)
1028 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1030 if (retval
!= ERROR_OK
)
1033 reg32
|= FLASH_PECR__FPRG
;
1034 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1036 if (retval
!= ERROR_OK
)
1039 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1041 if (retval
!= ERROR_OK
)
1044 reg32
|= FLASH_PECR__PROG
;
1045 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1051 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
1053 struct target
*target
= bank
->target
;
1054 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1058 /* To lock the program memory, simply set the lock bit and lock PECR */
1060 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1062 if (retval
!= ERROR_OK
)
1065 reg32
|= FLASH_PECR__PRGLOCK
;
1066 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1068 if (retval
!= ERROR_OK
)
1071 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1073 if (retval
!= ERROR_OK
)
1076 reg32
|= FLASH_PECR__PELOCK
;
1077 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1079 if (retval
!= ERROR_OK
)
1085 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
1087 struct target
*target
= bank
->target
;
1088 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1093 * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1094 * first unlock the memory, loop over the pages of this sector
1095 * and write 0x0 to its first word.
1098 retval
= stm32lx_unlock_program_memory(bank
);
1099 if (retval
!= ERROR_OK
)
1102 for (int page
= 0; page
< (int)stm32lx_info
->part_info
.pages_per_sector
;
1104 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
1105 retval
= target_write_u32(target
,
1106 stm32lx_info
->flash_base
+ FLASH_PECR
, reg32
);
1107 if (retval
!= ERROR_OK
)
1110 retval
= stm32lx_wait_until_bsy_clear(bank
);
1111 if (retval
!= ERROR_OK
)
1114 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
1115 * stm32lx_info
->part_info
.page_size
);
1116 retval
= target_write_u32(target
, addr
, 0x0);
1117 if (retval
!= ERROR_OK
)
1120 retval
= stm32lx_wait_until_bsy_clear(bank
);
1121 if (retval
!= ERROR_OK
)
1125 retval
= stm32lx_lock_program_memory(bank
);
1126 if (retval
!= ERROR_OK
)
1132 static inline int stm32lx_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
1134 struct target
*target
= bank
->target
;
1135 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1137 return target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_SR
, status
);
1140 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
1142 return stm32lx_wait_until_bsy_clear_timeout(bank
, 100);
1145 static int stm32lx_unlock_options_bytes(struct flash_bank
*bank
)
1147 struct target
*target
= bank
->target
;
1148 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1153 * Unlocking the options bytes is done by unlocking the PECR,
1154 * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1157 /* check flash is not already unlocked */
1158 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, ®32
);
1159 if (retval
!= ERROR_OK
)
1162 if ((reg32
& FLASH_PECR__OPTLOCK
) == 0)
1165 if ((reg32
& FLASH_PECR__PELOCK
) != 0) {
1167 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
, PEKEY1
);
1168 if (retval
!= ERROR_OK
)
1171 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
, PEKEY2
);
1172 if (retval
!= ERROR_OK
)
1176 /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1177 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_OPTKEYR
, OPTKEY1
);
1178 if (retval
!= ERROR_OK
)
1181 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_OPTKEYR
, OPTKEY2
);
1182 if (retval
!= ERROR_OK
)
1188 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank
*bank
, int timeout
)
1190 struct target
*target
= bank
->target
;
1191 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1193 int retval
= ERROR_OK
;
1195 /* wait for busy to clear */
1197 retval
= stm32lx_get_flash_status(bank
, &status
);
1198 if (retval
!= ERROR_OK
)
1201 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
1202 if ((status
& FLASH_SR__BSY
) == 0)
1205 if (timeout
-- <= 0) {
1206 LOG_ERROR("timed out waiting for flash");
1212 if (status
& FLASH_SR__WRPERR
) {
1213 LOG_ERROR("access denied / write protected");
1214 retval
= ERROR_FAIL
;
1217 if (status
& FLASH_SR__PGAERR
) {
1218 LOG_ERROR("invalid program address");
1219 retval
= ERROR_FAIL
;
1222 /* Clear but report errors */
1223 if (status
& FLASH_SR__OPTVERR
) {
1224 /* If this operation fails, we ignore it and report the original retval */
1225 target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_SR
, status
& FLASH_SR__OPTVERR
);
1231 static int stm32lx_obl_launch(struct flash_bank
*bank
)
1233 struct target
*target
= bank
->target
;
1234 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1237 /* This will fail as the target gets immediately rebooted */
1238 target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1239 FLASH_PECR__OBL_LAUNCH
);
1243 target_halt(target
);
1244 retval
= target_poll(target
);
1245 } while (--tries
> 0 &&
1246 (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
));
1248 return tries
? ERROR_OK
: ERROR_FAIL
;
1251 static int stm32lx_lock(struct flash_bank
*bank
)
1254 struct target
*target
= bank
->target
;
1256 if (target
->state
!= TARGET_HALTED
) {
1257 LOG_ERROR("Target not halted");
1258 return ERROR_TARGET_NOT_HALTED
;
1261 retval
= stm32lx_unlock_options_bytes(bank
);
1262 if (retval
!= ERROR_OK
)
1265 /* set the RDP protection level to 1 */
1266 retval
= target_write_u32(target
, OPTION_BYTES_ADDRESS
, OPTION_BYTE_0_PR1
);
1267 if (retval
!= ERROR_OK
)
1273 static int stm32lx_unlock(struct flash_bank
*bank
)
1276 struct target
*target
= bank
->target
;
1278 if (target
->state
!= TARGET_HALTED
) {
1279 LOG_ERROR("Target not halted");
1280 return ERROR_TARGET_NOT_HALTED
;
1283 retval
= stm32lx_unlock_options_bytes(bank
);
1284 if (retval
!= ERROR_OK
)
1287 /* set the RDP protection level to 0 */
1288 retval
= target_write_u32(target
, OPTION_BYTES_ADDRESS
, OPTION_BYTE_0_PR0
);
1289 if (retval
!= ERROR_OK
)
1292 retval
= stm32lx_wait_until_bsy_clear_timeout(bank
, 30000);
1293 if (retval
!= ERROR_OK
)
1299 static int stm32lx_mass_erase(struct flash_bank
*bank
)
1302 struct target
*target
= bank
->target
;
1303 struct stm32lx_flash_bank
*stm32lx_info
= NULL
;
1306 if (target
->state
!= TARGET_HALTED
) {
1307 LOG_ERROR("Target not halted");
1308 return ERROR_TARGET_NOT_HALTED
;
1311 stm32lx_info
= bank
->driver_priv
;
1313 retval
= stm32lx_lock(bank
);
1314 if (retval
!= ERROR_OK
)
1317 retval
= stm32lx_obl_launch(bank
);
1318 if (retval
!= ERROR_OK
)
1321 retval
= stm32lx_unlock(bank
);
1322 if (retval
!= ERROR_OK
)
1325 retval
= stm32lx_obl_launch(bank
);
1326 if (retval
!= ERROR_OK
)
1329 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, ®32
);
1330 if (retval
!= ERROR_OK
)
1333 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, reg32
| FLASH_PECR__OPTLOCK
);
1334 if (retval
!= ERROR_OK
)
1340 static int stm32lx_update_part_info(struct flash_bank
*bank
, uint16_t flash_size_in_kb
)
1342 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1344 switch (stm32lx_info
->part_info
.id
) {
1345 case 0x447: /* STM32L0xx (Cat.5) devices */
1346 if (flash_size_in_kb
== 192 || flash_size_in_kb
== 128) {
1347 stm32lx_info
->part_info
.first_bank_size_kb
= flash_size_in_kb
/ 2;
1348 stm32lx_info
->part_info
.has_dual_banks
= true;
1351 case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
1352 stm32lx_info
->part_info
.first_bank_size_kb
= flash_size_in_kb
/ 2;
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MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)