1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/armv7m.h>
32 /* stm32x register locations */
34 #define STM32_FLASH_ACR 0x40022000
35 #define STM32_FLASH_KEYR 0x40022004
36 #define STM32_FLASH_OPTKEYR 0x40022008
37 #define STM32_FLASH_SR 0x4002200C
38 #define STM32_FLASH_CR 0x40022010
39 #define STM32_FLASH_AR 0x40022014
40 #define STM32_FLASH_OBR 0x4002201C
41 #define STM32_FLASH_WRPR 0x40022020
43 /* option byte location */
45 #define STM32_OB_RDP 0x1FFFF800
46 #define STM32_OB_USER 0x1FFFF802
47 #define STM32_OB_DATA0 0x1FFFF804
48 #define STM32_OB_DATA1 0x1FFFF806
49 #define STM32_OB_WRP0 0x1FFFF808
50 #define STM32_OB_WRP1 0x1FFFF80A
51 #define STM32_OB_WRP2 0x1FFFF80C
52 #define STM32_OB_WRP3 0x1FFFF80E
54 /* FLASH_CR register bits */
56 #define FLASH_PG (1 << 0)
57 #define FLASH_PER (1 << 1)
58 #define FLASH_MER (1 << 2)
59 #define FLASH_OPTPG (1 << 4)
60 #define FLASH_OPTER (1 << 5)
61 #define FLASH_STRT (1 << 6)
62 #define FLASH_LOCK (1 << 7)
63 #define FLASH_OPTWRE (1 << 9)
65 /* FLASH_SR register bits */
67 #define FLASH_BSY (1 << 0)
68 #define FLASH_PGERR (1 << 2)
69 #define FLASH_WRPRTERR (1 << 4)
70 #define FLASH_EOP (1 << 5)
72 /* STM32_FLASH_OBR bit definitions (reading) */
77 #define OPT_RDRSTSTOP 3
78 #define OPT_RDRSTSTDBY 4
79 #define OPT_BFB2 5 /* dual flash bank only */
81 /* register unlock keys */
83 #define KEY1 0x45670123
84 #define KEY2 0xCDEF89AB
86 /* we use an offset to access the second bank on dual flash devices
87 * strangely the protection of the second bank is done on the bank0 reg's */
89 #define FLASH_OFFSET_B0 0x00
90 #define FLASH_OFFSET_B1 0x40
95 uint16_t user_options
;
96 uint16_t protection
[4];
99 struct stm32x_flash_bank
101 struct stm32x_options option_bytes
;
102 struct working_area
*write_algorithm
;
107 /* used to access dual flash bank stm32xl
108 * 0x00 will address bank 0 flash
109 * 0x40 will address bank 1 flash */
113 static int stm32x_mass_erase(struct flash_bank
*bank
);
115 /* flash bank stm32x <base> <size> 0 0 <target#>
117 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
119 struct stm32x_flash_bank
*stm32x_info
;
123 LOG_WARNING("incomplete flash_bank stm32x configuration");
124 return ERROR_FLASH_BANK_INVALID
;
127 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
128 bank
->driver_priv
= stm32x_info
;
130 stm32x_info
->write_algorithm
= NULL
;
131 stm32x_info
->probed
= 0;
132 stm32x_info
->has_dual_banks
= false;
133 stm32x_info
->register_offset
= FLASH_OFFSET_B0
;
138 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
140 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
141 return reg
+ stm32x_info
->register_offset
;
144 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
146 struct target
*target
= bank
->target
;
147 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
150 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
152 struct target
*target
= bank
->target
;
154 int retval
= ERROR_OK
;
156 /* wait for busy to clear */
159 retval
= stm32x_get_flash_status(bank
, &status
);
160 if (retval
!= ERROR_OK
)
162 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
163 if ((status
& FLASH_BSY
) == 0)
167 LOG_ERROR("timed out waiting for flash");
173 if (status
& FLASH_WRPRTERR
)
175 LOG_ERROR("stm32x device protected");
179 if (status
& FLASH_PGERR
)
181 LOG_ERROR("stm32x device programming failed");
185 /* Clear but report errors */
186 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
))
188 /* If this operation fails, we ignore it and report the original
191 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
192 FLASH_WRPRTERR
| FLASH_PGERR
);
197 int stm32x_check_operation_supported(struct flash_bank
*bank
)
199 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
201 /* if we have a dual flash bank device then
202 * we need to perform option byte stuff on bank0 only */
203 if (stm32x_info
->register_offset
!= FLASH_OFFSET_B0
)
205 LOG_ERROR("Option Byte Operation's must use bank0");
206 return ERROR_FLASH_OPERATION_FAILED
;
212 static int stm32x_read_options(struct flash_bank
*bank
)
215 struct stm32x_flash_bank
*stm32x_info
= NULL
;
216 struct target
*target
= bank
->target
;
218 stm32x_info
= bank
->driver_priv
;
220 /* read current option bytes */
221 int retval
= target_read_u32(target
, STM32_FLASH_OBR
, &optiondata
);
222 if (retval
!= ERROR_OK
)
225 stm32x_info
->option_bytes
.user_options
= (uint16_t)0xFFF8 | ((optiondata
>> 2) & 0x07);
226 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
228 if (optiondata
& (1 << OPT_READOUT
))
229 LOG_INFO("Device Security Bit Set");
231 /* each bit refers to a 4bank protection */
232 retval
= target_read_u32(target
, STM32_FLASH_WRPR
, &optiondata
);
233 if (retval
!= ERROR_OK
)
236 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
237 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
238 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
239 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
244 static int stm32x_erase_options(struct flash_bank
*bank
)
246 struct stm32x_flash_bank
*stm32x_info
= NULL
;
247 struct target
*target
= bank
->target
;
249 stm32x_info
= bank
->driver_priv
;
251 /* read current options */
252 stm32x_read_options(bank
);
254 /* unlock flash registers */
255 int retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
256 if (retval
!= ERROR_OK
)
259 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
260 if (retval
!= ERROR_OK
)
263 /* unlock option flash registers */
264 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
265 if (retval
!= ERROR_OK
)
267 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
268 if (retval
!= ERROR_OK
)
271 /* erase option bytes */
272 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
| FLASH_OPTWRE
);
273 if (retval
!= ERROR_OK
)
275 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
276 if (retval
!= ERROR_OK
)
279 retval
= stm32x_wait_status_busy(bank
, 10);
280 if (retval
!= ERROR_OK
)
283 /* clear readout protection and complementary option bytes
284 * this will also force a device unlock if set */
285 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
290 static int stm32x_write_options(struct flash_bank
*bank
)
292 struct stm32x_flash_bank
*stm32x_info
= NULL
;
293 struct target
*target
= bank
->target
;
295 stm32x_info
= bank
->driver_priv
;
297 /* unlock flash registers */
298 int retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
299 if (retval
!= ERROR_OK
)
301 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
302 if (retval
!= ERROR_OK
)
305 /* unlock option flash registers */
306 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
307 if (retval
!= ERROR_OK
)
309 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
310 if (retval
!= ERROR_OK
)
313 /* program option bytes */
314 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
| FLASH_OPTWRE
);
315 if (retval
!= ERROR_OK
)
318 /* write user option byte */
319 retval
= target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
320 if (retval
!= ERROR_OK
)
323 retval
= stm32x_wait_status_busy(bank
, 10);
324 if (retval
!= ERROR_OK
)
327 /* write protection byte 1 */
328 retval
= target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
329 if (retval
!= ERROR_OK
)
332 retval
= stm32x_wait_status_busy(bank
, 10);
333 if (retval
!= ERROR_OK
)
336 /* write protection byte 2 */
337 retval
= target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
338 if (retval
!= ERROR_OK
)
341 retval
= stm32x_wait_status_busy(bank
, 10);
342 if (retval
!= ERROR_OK
)
345 /* write protection byte 3 */
346 retval
= target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
347 if (retval
!= ERROR_OK
)
350 retval
= stm32x_wait_status_busy(bank
, 10);
351 if (retval
!= ERROR_OK
)
354 /* write protection byte 4 */
355 retval
= target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
356 if (retval
!= ERROR_OK
)
359 retval
= stm32x_wait_status_busy(bank
, 10);
360 if (retval
!= ERROR_OK
)
363 /* write readout protection bit */
364 retval
= target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
365 if (retval
!= ERROR_OK
)
368 retval
= stm32x_wait_status_busy(bank
, 10);
369 if (retval
!= ERROR_OK
)
372 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
373 if (retval
!= ERROR_OK
)
379 static int stm32x_protect_check(struct flash_bank
*bank
)
381 struct target
*target
= bank
->target
;
382 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
389 if (target
->state
!= TARGET_HALTED
)
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED
;
395 int retval
= stm32x_check_operation_supported(bank
);
396 if (ERROR_OK
!= retval
)
399 /* medium density - each bit refers to a 4bank protection
400 * high density - each bit refers to a 2bank protection */
401 retval
= target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
402 if (retval
!= ERROR_OK
)
405 /* medium density - each protection bit is for 4 * 1K pages
406 * high density - each protection bit is for 2 * 2K pages */
407 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
409 if (stm32x_info
->ppage_size
== 2)
411 /* high density flash/connectivity line protection */
415 if (protection
& (1 << 31))
418 /* bit 31 controls sector 62 - 255 protection for high density
419 * bit 31 controls sector 62 - 127 protection for connectivity line */
420 for (s
= 62; s
< bank
->num_sectors
; s
++)
422 bank
->sectors
[s
].is_protected
= set
;
425 if (bank
->num_sectors
> 61)
428 for (i
= 0; i
< num_bits
; i
++)
432 if (protection
& (1 << i
))
435 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
436 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
441 /* low/medium density flash protection */
442 for (i
= 0; i
< num_bits
; i
++)
446 if (protection
& (1 << i
))
449 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
450 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
457 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
459 struct target
*target
= bank
->target
;
462 if (bank
->target
->state
!= TARGET_HALTED
)
464 LOG_ERROR("Target not halted");
465 return ERROR_TARGET_NOT_HALTED
;
468 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
470 return stm32x_mass_erase(bank
);
473 /* unlock flash registers */
474 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
475 if (retval
!= ERROR_OK
)
477 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
478 if (retval
!= ERROR_OK
)
481 for (i
= first
; i
<= last
; i
++)
483 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
484 if (retval
!= ERROR_OK
)
486 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
487 bank
->base
+ bank
->sectors
[i
].offset
);
488 if (retval
!= ERROR_OK
)
490 retval
= target_write_u32(target
,
491 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
492 if (retval
!= ERROR_OK
)
495 retval
= stm32x_wait_status_busy(bank
, 100);
496 if (retval
!= ERROR_OK
)
499 bank
->sectors
[i
].is_erased
= 1;
502 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
503 if (retval
!= ERROR_OK
)
509 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
511 struct stm32x_flash_bank
*stm32x_info
= NULL
;
512 struct target
*target
= bank
->target
;
513 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
518 stm32x_info
= bank
->driver_priv
;
520 if (target
->state
!= TARGET_HALTED
)
522 LOG_ERROR("Target not halted");
523 return ERROR_TARGET_NOT_HALTED
;
526 int retval
= stm32x_check_operation_supported(bank
);
527 if (ERROR_OK
!= retval
)
530 if ((first
% stm32x_info
->ppage_size
) != 0)
532 LOG_WARNING("aligned start protect sector to a %d sector boundary",
533 stm32x_info
->ppage_size
);
534 first
= first
- (first
% stm32x_info
->ppage_size
);
536 if (((last
+ 1) % stm32x_info
->ppage_size
) != 0)
538 LOG_WARNING("aligned end protect sector to a %d sector boundary",
539 stm32x_info
->ppage_size
);
541 last
= last
- (last
% stm32x_info
->ppage_size
);
545 /* medium density - each bit refers to a 4bank protection
546 * high density - each bit refers to a 2bank protection */
547 retval
= target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
548 if (retval
!= ERROR_OK
)
551 prot_reg
[0] = (uint16_t)protection
;
552 prot_reg
[1] = (uint16_t)(protection
>> 8);
553 prot_reg
[2] = (uint16_t)(protection
>> 16);
554 prot_reg
[3] = (uint16_t)(protection
>> 24);
556 if (stm32x_info
->ppage_size
== 2)
558 /* high density flash */
560 /* bit 7 controls sector 62 - 255 protection */
564 prot_reg
[3] &= ~(1 << 7);
566 prot_reg
[3] |= (1 << 7);
574 for (i
= first
; i
<= last
; i
++)
576 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
577 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
580 prot_reg
[reg
] &= ~(1 << bit
);
582 prot_reg
[reg
] |= (1 << bit
);
587 /* medium density flash */
588 for (i
= first
; i
<= last
; i
++)
590 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
591 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
594 prot_reg
[reg
] &= ~(1 << bit
);
596 prot_reg
[reg
] |= (1 << bit
);
600 if ((status
= stm32x_erase_options(bank
)) != ERROR_OK
)
603 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
604 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
605 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
606 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
608 return stm32x_write_options(bank
);
611 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
612 uint32_t offset
, uint32_t count
)
614 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
615 struct target
*target
= bank
->target
;
616 uint32_t buffer_size
= 16384;
617 struct working_area
*source
;
618 uint32_t address
= bank
->base
+ offset
;
619 struct reg_param reg_params
[4];
620 struct armv7m_algorithm armv7m_info
;
621 int retval
= ERROR_OK
;
623 /* see contib/loaders/flash/stm32x.s for src */
625 static const uint8_t stm32x_flash_write_code
[] = {
626 /* #define STM32_FLASH_CR_OFFSET 0x10 */
627 /* #define STM32_FLASH_SR_OFFSET 0x0C */
629 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
630 0x1c, 0x44, /* add r4, r3 */
631 /* write_half_word: */
632 0x01, 0x23, /* movs r3, #0x01 */
633 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
634 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
635 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
637 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
638 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
639 0xfb, 0xd0, /* beq busy */
640 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
641 0x01, 0xd1, /* bne exit */
642 0x01, 0x3a, /* subs r2, r2, #0x01 */
643 0xf0, 0xd1, /* bne write_half_word */
645 0x00, 0xbe, /* bkpt #0x00 */
646 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
649 /* flash write code */
650 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
651 &stm32x_info
->write_algorithm
) != ERROR_OK
)
653 LOG_WARNING("no working area available, can't do block memory writes");
654 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
657 if ((retval
= target_write_buffer(target
, stm32x_info
->write_algorithm
->address
,
658 sizeof(stm32x_flash_write_code
),
659 (uint8_t*)stm32x_flash_write_code
)) != ERROR_OK
)
663 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
666 if (buffer_size
<= 256)
668 /* if we already allocated the writing code, but failed to get a
669 * buffer, free the algorithm */
670 if (stm32x_info
->write_algorithm
)
671 target_free_working_area(target
, stm32x_info
->write_algorithm
);
673 LOG_WARNING("no large enough working area available, can't do block memory writes");
674 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
678 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
679 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
681 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
682 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
683 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
684 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
);
688 uint32_t thisrun_count
= (count
> (buffer_size
/ 2)) ?
689 (buffer_size
/ 2) : count
;
691 if ((retval
= target_write_buffer(target
, source
->address
,
692 thisrun_count
* 2, buffer
)) != ERROR_OK
)
695 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
696 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
697 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
698 buf_set_u32(reg_params
[3].value
, 0, 32, stm32x_info
->register_offset
);
700 if ((retval
= target_run_algorithm(target
, 0, NULL
, 4, reg_params
,
701 stm32x_info
->write_algorithm
->address
,
703 10000, &armv7m_info
)) != ERROR_OK
)
705 LOG_ERROR("error executing stm32x flash write algorithm");
709 if (buf_get_u32(reg_params
[3].value
, 0, 32) & FLASH_PGERR
)
711 LOG_ERROR("flash memory not erased before writing");
712 /* Clear but report errors */
713 target_write_u32(target
, STM32_FLASH_SR
, FLASH_PGERR
);
718 if (buf_get_u32(reg_params
[3].value
, 0, 32) & FLASH_WRPRTERR
)
720 LOG_ERROR("flash memory write protected");
721 /* Clear but report errors */
722 target_write_u32(target
, STM32_FLASH_SR
, FLASH_WRPRTERR
);
727 buffer
+= thisrun_count
* 2;
728 address
+= thisrun_count
* 2;
729 count
-= thisrun_count
;
732 target_free_working_area(target
, source
);
733 target_free_working_area(target
, stm32x_info
->write_algorithm
);
735 destroy_reg_param(®_params
[0]);
736 destroy_reg_param(®_params
[1]);
737 destroy_reg_param(®_params
[2]);
738 destroy_reg_param(®_params
[3]);
743 static int stm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
744 uint32_t offset
, uint32_t count
)
746 struct target
*target
= bank
->target
;
747 uint32_t words_remaining
= (count
/ 2);
748 uint32_t bytes_remaining
= (count
& 0x00000001);
749 uint32_t address
= bank
->base
+ offset
;
750 uint32_t bytes_written
= 0;
753 if (bank
->target
->state
!= TARGET_HALTED
)
755 LOG_ERROR("Target not halted");
756 return ERROR_TARGET_NOT_HALTED
;
761 LOG_WARNING("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
762 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
765 /* unlock flash registers */
766 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
767 if (retval
!= ERROR_OK
)
769 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
770 if (retval
!= ERROR_OK
)
773 /* multiple half words (2-byte) to be programmed? */
774 if (words_remaining
> 0)
776 /* try using a block write */
777 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
779 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
781 /* if block write failed (no sufficient working area),
782 * we use normal (slow) single dword accesses */
783 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
788 buffer
+= words_remaining
* 2;
789 address
+= words_remaining
* 2;
794 if ((retval
!= ERROR_OK
) && (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
))
797 while (words_remaining
> 0)
800 memcpy(&value
, buffer
+ bytes_written
, sizeof(uint16_t));
802 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
803 if (retval
!= ERROR_OK
)
805 retval
= target_write_u16(target
, address
, value
);
806 if (retval
!= ERROR_OK
)
809 retval
= stm32x_wait_status_busy(bank
, 5);
810 if (retval
!= ERROR_OK
)
820 uint16_t value
= 0xffff;
821 memcpy(&value
, buffer
+ bytes_written
, bytes_remaining
);
823 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
824 if (retval
!= ERROR_OK
)
826 retval
= target_write_u16(target
, address
, value
);
827 if (retval
!= ERROR_OK
)
830 retval
= stm32x_wait_status_busy(bank
, 5);
831 if (retval
!= ERROR_OK
)
835 return target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
838 static int stm32x_probe(struct flash_bank
*bank
)
840 struct target
*target
= bank
->target
;
841 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
846 uint32_t base_address
= 0x08000000;
848 stm32x_info
->probed
= 0;
849 stm32x_info
->register_offset
= FLASH_OFFSET_B0
;
851 /* read stm32 device id register */
852 int retval
= target_read_u32(target
, 0xE0042000, &device_id
);
853 if (retval
!= ERROR_OK
)
855 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
857 /* get flash size from target. */
858 retval
= target_read_u16(target
, 0x1FFFF7E0, &num_pages
);
859 if (retval
!= ERROR_OK
)
861 LOG_WARNING("failed reading flash size, default to max target family");
862 /* failed reading flash size, default to max target family */
866 if ((device_id
& 0x7ff) == 0x410)
868 /* medium density - we have 1k pages
869 * 4 pages for a protection area */
871 stm32x_info
->ppage_size
= 4;
873 /* check for early silicon */
874 if (num_pages
== 0xffff)
876 /* number of sectors incorrect on revA */
877 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
881 else if ((device_id
& 0x7ff) == 0x412)
883 /* low density - we have 1k pages
884 * 4 pages for a protection area */
886 stm32x_info
->ppage_size
= 4;
888 /* check for early silicon */
889 if (num_pages
== 0xffff)
891 /* number of sectors incorrect on revA */
892 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
896 else if ((device_id
& 0x7ff) == 0x414)
898 /* high density - we have 2k pages
899 * 2 pages for a protection area */
901 stm32x_info
->ppage_size
= 2;
903 /* check for early silicon */
904 if (num_pages
== 0xffff)
906 /* number of sectors incorrect on revZ */
907 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
911 else if ((device_id
& 0x7ff) == 0x418)
913 /* connectivity line density - we have 2k pages
914 * 2 pages for a protection area */
916 stm32x_info
->ppage_size
= 2;
918 /* check for early silicon */
919 if (num_pages
== 0xffff)
921 /* number of sectors incorrect on revZ */
922 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
926 else if ((device_id
& 0x7ff) == 0x420)
928 /* value line density - we have 1k pages
929 * 4 pages for a protection area */
931 stm32x_info
->ppage_size
= 4;
933 /* check for early silicon */
934 if (num_pages
== 0xffff)
936 /* number of sectors may be incorrrect on early silicon */
937 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
941 else if ((device_id
& 0x7ff) == 0x430)
943 /* xl line density - we have 2k pages
944 * 2 pages for a protection area */
946 stm32x_info
->ppage_size
= 2;
947 stm32x_info
->has_dual_banks
= true;
949 /* check for early silicon */
950 if (num_pages
== 0xffff)
952 /* number of sectors may be incorrrect on early silicon */
953 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
957 /* split reported size into matching bank */
958 if (bank
->base
!= 0x08080000)
960 /* bank 0 will be fixed 512k */
966 /* bank1 also uses a register offset */
967 stm32x_info
->register_offset
= FLASH_OFFSET_B1
;
968 base_address
= 0x08080000;
973 LOG_WARNING("Cannot identify target as a STM32 family.");
977 LOG_INFO("flash size = %dkbytes", num_pages
);
979 /* calculate numbers of pages */
980 num_pages
/= (page_size
/ 1024);
985 bank
->sectors
= NULL
;
988 bank
->base
= base_address
;
989 bank
->size
= (num_pages
* page_size
);
990 bank
->num_sectors
= num_pages
;
991 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
993 for (i
= 0; i
< num_pages
; i
++)
995 bank
->sectors
[i
].offset
= i
* page_size
;
996 bank
->sectors
[i
].size
= page_size
;
997 bank
->sectors
[i
].is_erased
= -1;
998 bank
->sectors
[i
].is_protected
= 1;
1001 stm32x_info
->probed
= 1;
1006 static int stm32x_auto_probe(struct flash_bank
*bank
)
1008 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1009 if (stm32x_info
->probed
)
1011 return stm32x_probe(bank
);
1015 COMMAND_HANDLER(stm32x_handle_part_id_command
)
1021 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1023 struct target
*target
= bank
->target
;
1027 /* read stm32 device id register */
1028 int retval
= target_read_u32(target
, 0xE0042000, &device_id
);
1029 if (retval
!= ERROR_OK
)
1032 if ((device_id
& 0x7ff) == 0x410)
1034 printed
= snprintf(buf
, buf_size
, "stm32x (Medium Density) - Rev: ");
1036 buf_size
-= printed
;
1038 switch (device_id
>> 16)
1041 snprintf(buf
, buf_size
, "A");
1045 snprintf(buf
, buf_size
, "B");
1049 snprintf(buf
, buf_size
, "Z");
1053 snprintf(buf
, buf_size
, "Y");
1057 snprintf(buf
, buf_size
, "unknown");
1061 else if ((device_id
& 0x7ff) == 0x412)
1063 printed
= snprintf(buf
, buf_size
, "stm32x (Low Density) - Rev: ");
1065 buf_size
-= printed
;
1067 switch (device_id
>> 16)
1070 snprintf(buf
, buf_size
, "A");
1074 snprintf(buf
, buf_size
, "unknown");
1078 else if ((device_id
& 0x7ff) == 0x414)
1080 printed
= snprintf(buf
, buf_size
, "stm32x (High Density) - Rev: ");
1082 buf_size
-= printed
;
1084 switch (device_id
>> 16)
1087 snprintf(buf
, buf_size
, "A");
1091 snprintf(buf
, buf_size
, "Z");
1095 snprintf(buf
, buf_size
, "unknown");
1099 else if ((device_id
& 0x7ff) == 0x418)
1101 printed
= snprintf(buf
, buf_size
, "stm32x (Connectivity) - Rev: ");
1103 buf_size
-= printed
;
1105 switch (device_id
>> 16)
1108 snprintf(buf
, buf_size
, "A");
1112 snprintf(buf
, buf_size
, "Z");
1116 snprintf(buf
, buf_size
, "unknown");
1120 else if ((device_id
& 0x7ff) == 0x420)
1122 printed
= snprintf(buf
, buf_size
, "stm32x (Value) - Rev: ");
1124 buf_size
-= printed
;
1126 switch (device_id
>> 16)
1129 snprintf(buf
, buf_size
, "A");
1133 snprintf(buf
, buf_size
, "Z");
1137 snprintf(buf
, buf_size
, "unknown");
1141 else if ((device_id
& 0x7ff) == 0x430)
1143 printed
= snprintf(buf
, buf_size
, "stm32x (XL) - Rev: ");
1145 buf_size
-= printed
;
1147 switch (device_id
>> 16)
1150 snprintf(buf
, buf_size
, "A");
1154 snprintf(buf
, buf_size
, "unknown");
1160 snprintf(buf
, buf_size
, "Cannot identify target as a stm32x\n");
1167 COMMAND_HANDLER(stm32x_handle_lock_command
)
1169 struct target
*target
= NULL
;
1170 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1174 command_print(CMD_CTX
, "stm32x lock <bank>");
1178 struct flash_bank
*bank
;
1179 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1180 if (ERROR_OK
!= retval
)
1183 stm32x_info
= bank
->driver_priv
;
1185 target
= bank
->target
;
1187 if (target
->state
!= TARGET_HALTED
)
1189 LOG_ERROR("Target not halted");
1190 return ERROR_TARGET_NOT_HALTED
;
1193 retval
= stm32x_check_operation_supported(bank
);
1194 if (ERROR_OK
!= retval
)
1197 if (stm32x_erase_options(bank
) != ERROR_OK
)
1199 command_print(CMD_CTX
, "stm32x failed to erase options");
1203 /* set readout protection */
1204 stm32x_info
->option_bytes
.RDP
= 0;
1206 if (stm32x_write_options(bank
) != ERROR_OK
)
1208 command_print(CMD_CTX
, "stm32x failed to lock device");
1212 command_print(CMD_CTX
, "stm32x locked");
1217 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1219 struct target
*target
= NULL
;
1223 command_print(CMD_CTX
, "stm32x unlock <bank>");
1227 struct flash_bank
*bank
;
1228 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1229 if (ERROR_OK
!= retval
)
1232 target
= bank
->target
;
1234 if (target
->state
!= TARGET_HALTED
)
1236 LOG_ERROR("Target not halted");
1237 return ERROR_TARGET_NOT_HALTED
;
1240 retval
= stm32x_check_operation_supported(bank
);
1241 if (ERROR_OK
!= retval
)
1244 if (stm32x_erase_options(bank
) != ERROR_OK
)
1246 command_print(CMD_CTX
, "stm32x failed to unlock device");
1250 if (stm32x_write_options(bank
) != ERROR_OK
)
1252 command_print(CMD_CTX
, "stm32x failed to lock device");
1256 command_print(CMD_CTX
, "stm32x unlocked.\n"
1257 "INFO: a reset or power cycle is required "
1258 "for the new settings to take effect.");
1263 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1265 uint32_t optionbyte
;
1266 struct target
*target
= NULL
;
1267 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1271 command_print(CMD_CTX
, "stm32x options_read <bank>");
1275 struct flash_bank
*bank
;
1276 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1277 if (ERROR_OK
!= retval
)
1280 stm32x_info
= bank
->driver_priv
;
1282 target
= bank
->target
;
1284 if (target
->state
!= TARGET_HALTED
)
1286 LOG_ERROR("Target not halted");
1287 return ERROR_TARGET_NOT_HALTED
;
1290 retval
= stm32x_check_operation_supported(bank
);
1291 if (ERROR_OK
!= retval
)
1294 retval
= target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
1295 if (retval
!= ERROR_OK
)
1297 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1299 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_ERROR
, 1))
1300 command_print(CMD_CTX
, "Option Byte Complement Error");
1302 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_READOUT
, 1))
1303 command_print(CMD_CTX
, "Readout Protection On");
1305 command_print(CMD_CTX
, "Readout Protection Off");
1307 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDWDGSW
, 1))
1308 command_print(CMD_CTX
, "Software Watchdog");
1310 command_print(CMD_CTX
, "Hardware Watchdog");
1312 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDRSTSTOP
, 1))
1313 command_print(CMD_CTX
, "Stop: No reset generated");
1315 command_print(CMD_CTX
, "Stop: Reset generated");
1317 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
1318 command_print(CMD_CTX
, "Standby: No reset generated");
1320 command_print(CMD_CTX
, "Standby: Reset generated");
1322 if (stm32x_info
->has_dual_banks
)
1324 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_BFB2
, 1))
1325 command_print(CMD_CTX
, "Boot: Bank 0");
1327 command_print(CMD_CTX
, "Boot: Bank 1");
1333 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1335 struct target
*target
= NULL
;
1336 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1337 uint16_t optionbyte
= 0xF8;
1341 command_print(CMD_CTX
, "stm32x options_write <bank> <SWWDG | HWWDG> "
1342 "<RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP> <BOOT0 | BOOT1>");
1346 struct flash_bank
*bank
;
1347 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1348 if (ERROR_OK
!= retval
)
1351 stm32x_info
= bank
->driver_priv
;
1353 target
= bank
->target
;
1355 if (target
->state
!= TARGET_HALTED
)
1357 LOG_ERROR("Target not halted");
1358 return ERROR_TARGET_NOT_HALTED
;
1361 retval
= stm32x_check_operation_supported(bank
);
1362 if (ERROR_OK
!= retval
)
1365 /* REVISIT: ignores some options which we will display...
1366 * and doesn't insist on the specified syntax.
1370 if (strcmp(CMD_ARGV
[1], "SWWDG") == 0)
1372 optionbyte
|= (1 << 0);
1374 else /* REVISIT must be "HWWDG" then ... */
1376 optionbyte
&= ~(1 << 0);
1380 if (strcmp(CMD_ARGV
[2], "NORSTSTOP") == 0)
1382 optionbyte
|= (1 << 1);
1384 else /* REVISIT must be "RSTSTNDBY" then ... */
1386 optionbyte
&= ~(1 << 1);
1389 /* OPT_RDRSTSTDBY */
1390 if (strcmp(CMD_ARGV
[3], "NORSTSTNDBY") == 0)
1392 optionbyte
|= (1 << 2);
1394 else /* REVISIT must be "RSTSTOP" then ... */
1396 optionbyte
&= ~(1 << 2);
1399 if (CMD_ARGC
> 4 && stm32x_info
->has_dual_banks
)
1402 if (strcmp(CMD_ARGV
[4], "BOOT0") == 0)
1404 optionbyte
|= (1 << 3);
1408 optionbyte
&= ~(1 << 3);
1412 if (stm32x_erase_options(bank
) != ERROR_OK
)
1414 command_print(CMD_CTX
, "stm32x failed to erase options");
1418 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1420 if (stm32x_write_options(bank
) != ERROR_OK
)
1422 command_print(CMD_CTX
, "stm32x failed to write options");
1426 command_print(CMD_CTX
, "stm32x write options complete.\n"
1427 "INFO: a reset or power cycle is required "
1428 "for the new settings to take effect.");
1433 static int stm32x_mass_erase(struct flash_bank
*bank
)
1435 struct target
*target
= bank
->target
;
1437 if (target
->state
!= TARGET_HALTED
)
1439 LOG_ERROR("Target not halted");
1440 return ERROR_TARGET_NOT_HALTED
;
1443 /* unlock option flash registers */
1444 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1445 if (retval
!= ERROR_OK
)
1447 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1448 if (retval
!= ERROR_OK
)
1451 /* mass erase flash memory */
1452 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1453 if (retval
!= ERROR_OK
)
1455 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
| FLASH_STRT
);
1456 if (retval
!= ERROR_OK
)
1459 retval
= stm32x_wait_status_busy(bank
, 100);
1460 if (retval
!= ERROR_OK
)
1463 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1464 if (retval
!= ERROR_OK
)
1470 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1476 command_print(CMD_CTX
, "stm32x mass_erase <bank>");
1480 struct flash_bank
*bank
;
1481 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1482 if (ERROR_OK
!= retval
)
1485 retval
= stm32x_mass_erase(bank
);
1486 if (retval
== ERROR_OK
)
1488 /* set all sectors as erased */
1489 for (i
= 0; i
< bank
->num_sectors
; i
++)
1491 bank
->sectors
[i
].is_erased
= 1;
1494 command_print(CMD_CTX
, "stm32x mass erase complete");
1498 command_print(CMD_CTX
, "stm32x mass erase failed");
1504 static const struct command_registration stm32x_exec_command_handlers
[] = {
1507 .handler
= stm32x_handle_lock_command
,
1508 .mode
= COMMAND_EXEC
,
1510 .help
= "Lock entire flash device.",
1514 .handler
= stm32x_handle_unlock_command
,
1515 .mode
= COMMAND_EXEC
,
1517 .help
= "Unlock entire protected flash device.",
1520 .name
= "mass_erase",
1521 .handler
= stm32x_handle_mass_erase_command
,
1522 .mode
= COMMAND_EXEC
,
1524 .help
= "Erase entire flash device.",
1527 .name
= "options_read",
1528 .handler
= stm32x_handle_options_read_command
,
1529 .mode
= COMMAND_EXEC
,
1531 .help
= "Read and display device option byte.",
1534 .name
= "options_write",
1535 .handler
= stm32x_handle_options_write_command
,
1536 .mode
= COMMAND_EXEC
,
1537 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1538 "('RSTSTNDBY'|'NORSTSTNDBY') "
1539 "('RSTSTOP'|'NORSTSTOP')",
1540 .help
= "Replace bits in device option byte.",
1542 COMMAND_REGISTRATION_DONE
1545 static const struct command_registration stm32x_command_handlers
[] = {
1548 .mode
= COMMAND_ANY
,
1549 .help
= "stm32x flash command group",
1550 .chain
= stm32x_exec_command_handlers
,
1552 COMMAND_REGISTRATION_DONE
1555 struct flash_driver stm32x_flash
= {
1557 .commands
= stm32x_command_handlers
,
1558 .flash_bank_command
= stm32x_flash_bank_command
,
1559 .erase
= stm32x_erase
,
1560 .protect
= stm32x_protect
,
1561 .write
= stm32x_write
,
1562 .read
= default_flash_read
,
1563 .probe
= stm32x_probe
,
1564 .auto_probe
= stm32x_auto_probe
,
1565 .erase_check
= default_flash_mem_blank_check
,
1566 .protect_check
= stm32x_protect_check
,
1567 .info
= get_stm32x_info
,
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