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stm32: add error propagation on writes
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
58 {
59 struct target *target = bank->target;
60 return target_read_u32(target, STM32_FLASH_SR, status);
61 }
62
63 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
64 {
65 struct target *target = bank->target;
66 uint32_t status;
67 int retval = ERROR_OK;
68
69 /* wait for busy to clear */
70 for (;;)
71 {
72 retval = stm32x_get_flash_status(bank, &status);
73 if (retval != ERROR_OK)
74 return retval;
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 if ((status & FLASH_BSY) == 0)
77 break;
78 if (timeout-- <= 0)
79 {
80 LOG_ERROR("timed out waiting for flash");
81 return ERROR_FAIL;
82 }
83 alive_sleep(1);
84 }
85
86 if (status & FLASH_WRPRTERR)
87 {
88 LOG_ERROR("stm32x device protected");
89 retval = ERROR_FAIL;
90 }
91
92 if (status & FLASH_PGERR)
93 {
94 LOG_ERROR("stm32x device programming failed");
95 retval = ERROR_FAIL;
96 }
97
98 /* Clear but report errors */
99 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
100 {
101 /* If this operation fails, we ignore it and report the original
102 * retval
103 */
104 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
105 }
106 return retval;
107 }
108
109 static int stm32x_read_options(struct flash_bank *bank)
110 {
111 uint32_t optiondata;
112 struct stm32x_flash_bank *stm32x_info = NULL;
113 struct target *target = bank->target;
114
115 stm32x_info = bank->driver_priv;
116
117 /* read current option bytes */
118 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
119
120 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
121 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
122
123 if (optiondata & (1 << OPT_READOUT))
124 LOG_INFO("Device Security Bit Set");
125
126 /* each bit refers to a 4bank protection */
127 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
128
129 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
130 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
131 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
132 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
133
134 return ERROR_OK;
135 }
136
137 static int stm32x_erase_options(struct flash_bank *bank)
138 {
139 struct stm32x_flash_bank *stm32x_info = NULL;
140 struct target *target = bank->target;
141
142 stm32x_info = bank->driver_priv;
143
144 /* read current options */
145 stm32x_read_options(bank);
146
147 /* unlock flash registers */
148 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
149 if (retval != ERROR_OK)
150 return retval;
151
152 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
153 if (retval != ERROR_OK)
154 return retval;
155
156 /* unlock option flash registers */
157 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
158 if (retval != ERROR_OK)
159 return retval;
160 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
161 if (retval != ERROR_OK)
162 return retval;
163
164 /* erase option bytes */
165 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
166 if (retval != ERROR_OK)
167 return retval;
168 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
169 if (retval != ERROR_OK)
170 return retval;
171
172 retval = stm32x_wait_status_busy(bank, 10);
173 if (retval != ERROR_OK)
174 return retval;
175
176 /* clear readout protection and complementary option bytes
177 * this will also force a device unlock if set */
178 stm32x_info->option_bytes.RDP = 0x5AA5;
179
180 return ERROR_OK;
181 }
182
183 static int stm32x_write_options(struct flash_bank *bank)
184 {
185 struct stm32x_flash_bank *stm32x_info = NULL;
186 struct target *target = bank->target;
187
188 stm32x_info = bank->driver_priv;
189
190 /* unlock flash registers */
191 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
192 if (retval != ERROR_OK)
193 return retval;
194 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
195 if (retval != ERROR_OK)
196 return retval;
197
198 /* unlock option flash registers */
199 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
200 if (retval != ERROR_OK)
201 return retval;
202 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
203 if (retval != ERROR_OK)
204 return retval;
205
206 /* program option bytes */
207 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
208 if (retval != ERROR_OK)
209 return retval;
210
211 /* write user option byte */
212 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
213 if (retval != ERROR_OK)
214 return retval;
215
216 retval = stm32x_wait_status_busy(bank, 10);
217 if (retval != ERROR_OK)
218 return retval;
219
220 /* write protection byte 1 */
221 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
222 if (retval != ERROR_OK)
223 return retval;
224
225 retval = stm32x_wait_status_busy(bank, 10);
226 if (retval != ERROR_OK)
227 return retval;
228
229 /* write protection byte 2 */
230 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
231 if (retval != ERROR_OK)
232 return retval;
233
234 retval = stm32x_wait_status_busy(bank, 10);
235 if (retval != ERROR_OK)
236 return retval;
237
238 /* write protection byte 3 */
239 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
240 if (retval != ERROR_OK)
241 return retval;
242
243 retval = stm32x_wait_status_busy(bank, 10);
244 if (retval != ERROR_OK)
245 return retval;
246
247 /* write protection byte 4 */
248 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
249 if (retval != ERROR_OK)
250 return retval;
251
252 retval = stm32x_wait_status_busy(bank, 10);
253 if (retval != ERROR_OK)
254 return retval;
255
256 /* write readout protection bit */
257 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
258 if (retval != ERROR_OK)
259 return retval;
260
261 retval = stm32x_wait_status_busy(bank, 10);
262 if (retval != ERROR_OK)
263 return retval;
264
265 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
266 if (retval != ERROR_OK)
267 return retval;
268
269 return ERROR_OK;
270 }
271
272 static int stm32x_protect_check(struct flash_bank *bank)
273 {
274 struct target *target = bank->target;
275 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
276
277 uint32_t protection;
278 int i, s;
279 int num_bits;
280 int set;
281
282 if (target->state != TARGET_HALTED)
283 {
284 LOG_ERROR("Target not halted");
285 return ERROR_TARGET_NOT_HALTED;
286 }
287
288 /* medium density - each bit refers to a 4bank protection
289 * high density - each bit refers to a 2bank protection */
290 target_read_u32(target, STM32_FLASH_WRPR, &protection);
291
292 /* medium density - each protection bit is for 4 * 1K pages
293 * high density - each protection bit is for 2 * 2K pages */
294 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
295
296 if (stm32x_info->ppage_size == 2)
297 {
298 /* high density flash/connectivity line protection */
299
300 set = 1;
301
302 if (protection & (1 << 31))
303 set = 0;
304
305 /* bit 31 controls sector 62 - 255 protection for high density
306 * bit 31 controls sector 62 - 127 protection for connectivity line */
307 for (s = 62; s < bank->num_sectors; s++)
308 {
309 bank->sectors[s].is_protected = set;
310 }
311
312 if (bank->num_sectors > 61)
313 num_bits = 31;
314
315 for (i = 0; i < num_bits; i++)
316 {
317 set = 1;
318
319 if (protection & (1 << i))
320 set = 0;
321
322 for (s = 0; s < stm32x_info->ppage_size; s++)
323 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
324 }
325 }
326 else
327 {
328 /* low/medium density flash protection */
329 for (i = 0; i < num_bits; i++)
330 {
331 set = 1;
332
333 if (protection & (1 << i))
334 set = 0;
335
336 for (s = 0; s < stm32x_info->ppage_size; s++)
337 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
338 }
339 }
340
341 return ERROR_OK;
342 }
343
344 static int stm32x_erase(struct flash_bank *bank, int first, int last)
345 {
346 struct target *target = bank->target;
347 int i;
348
349 if (bank->target->state != TARGET_HALTED)
350 {
351 LOG_ERROR("Target not halted");
352 return ERROR_TARGET_NOT_HALTED;
353 }
354
355 if ((first == 0) && (last == (bank->num_sectors - 1)))
356 {
357 return stm32x_mass_erase(bank);
358 }
359
360 /* unlock flash registers */
361 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
362 if (retval != ERROR_OK)
363 return retval;
364 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
365 if (retval != ERROR_OK)
366 return retval;
367
368 for (i = first; i <= last; i++)
369 {
370 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
371 if (retval != ERROR_OK)
372 return retval;
373 retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
374 if (retval != ERROR_OK)
375 return retval;
376 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
377 if (retval != ERROR_OK)
378 return retval;
379
380 retval = stm32x_wait_status_busy(bank, 100);
381 if (retval != ERROR_OK)
382 return retval;
383
384 bank->sectors[i].is_erased = 1;
385 }
386
387 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
388 if (retval != ERROR_OK)
389 return retval;
390
391 return ERROR_OK;
392 }
393
394 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
395 {
396 struct stm32x_flash_bank *stm32x_info = NULL;
397 struct target *target = bank->target;
398 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
399 int i, reg, bit;
400 int status;
401 uint32_t protection;
402
403 stm32x_info = bank->driver_priv;
404
405 if (target->state != TARGET_HALTED)
406 {
407 LOG_ERROR("Target not halted");
408 return ERROR_TARGET_NOT_HALTED;
409 }
410
411 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
412 (last + 1) % stm32x_info->ppage_size))
413 {
414 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
415 stm32x_info->ppage_size);
416 return ERROR_FLASH_SECTOR_INVALID;
417 }
418
419 /* medium density - each bit refers to a 4bank protection
420 * high density - each bit refers to a 2bank protection */
421 target_read_u32(target, STM32_FLASH_WRPR, &protection);
422
423 prot_reg[0] = (uint16_t)protection;
424 prot_reg[1] = (uint16_t)(protection >> 8);
425 prot_reg[2] = (uint16_t)(protection >> 16);
426 prot_reg[3] = (uint16_t)(protection >> 24);
427
428 if (stm32x_info->ppage_size == 2)
429 {
430 /* high density flash */
431
432 /* bit 7 controls sector 62 - 255 protection */
433 if (last > 61)
434 {
435 if (set)
436 prot_reg[3] &= ~(1 << 7);
437 else
438 prot_reg[3] |= (1 << 7);
439 }
440
441 if (first > 61)
442 first = 62;
443 if (last > 61)
444 last = 61;
445
446 for (i = first; i <= last; i++)
447 {
448 reg = (i / stm32x_info->ppage_size) / 8;
449 bit = (i / stm32x_info->ppage_size) - (reg * 8);
450
451 if (set)
452 prot_reg[reg] &= ~(1 << bit);
453 else
454 prot_reg[reg] |= (1 << bit);
455 }
456 }
457 else
458 {
459 /* medium density flash */
460 for (i = first; i <= last; i++)
461 {
462 reg = (i / stm32x_info->ppage_size) / 8;
463 bit = (i / stm32x_info->ppage_size) - (reg * 8);
464
465 if (set)
466 prot_reg[reg] &= ~(1 << bit);
467 else
468 prot_reg[reg] |= (1 << bit);
469 }
470 }
471
472 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
473 return status;
474
475 stm32x_info->option_bytes.protection[0] = prot_reg[0];
476 stm32x_info->option_bytes.protection[1] = prot_reg[1];
477 stm32x_info->option_bytes.protection[2] = prot_reg[2];
478 stm32x_info->option_bytes.protection[3] = prot_reg[3];
479
480 return stm32x_write_options(bank);
481 }
482
483 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
484 uint32_t offset, uint32_t count)
485 {
486 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
487 struct target *target = bank->target;
488 uint32_t buffer_size = 16384;
489 struct working_area *source;
490 uint32_t address = bank->base + offset;
491 struct reg_param reg_params[4];
492 struct armv7m_algorithm armv7m_info;
493 int retval = ERROR_OK;
494
495 /* see contib/loaders/flash/stm32x.s for src */
496
497 static const uint8_t stm32x_flash_write_code[] = {
498 /* write: */
499 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
500 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
501 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
502 0x23, 0x60, /* str r3, [r4, #0] */
503 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
504 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
505 /* busy: */
506 0x2B, 0x68, /* ldr r3, [r5, #0] */
507 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
508 0xFB, 0xD0, /* beq busy */
509 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
510 0x01, 0xD1, /* bne exit */
511 0x01, 0x3A, /* subs r2, r2, #1 */
512 0xED, 0xD1, /* bne write */
513 /* exit: */
514 0x00, 0xBE, /* bkpt #0 */
515 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
516 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
517 };
518
519 /* flash write code */
520 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
521 &stm32x_info->write_algorithm) != ERROR_OK)
522 {
523 LOG_WARNING("no working area available, can't do block memory writes");
524 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
525 };
526
527 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
528 sizeof(stm32x_flash_write_code),
529 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
530 return retval;
531
532 /* memory buffer */
533 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
534 {
535 buffer_size /= 2;
536 if (buffer_size <= 256)
537 {
538 /* if we already allocated the writing code, but failed to get a
539 * buffer, free the algorithm */
540 if (stm32x_info->write_algorithm)
541 target_free_working_area(target, stm32x_info->write_algorithm);
542
543 LOG_WARNING("no large enough working area available, can't do block memory writes");
544 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
545 }
546 };
547
548 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
549 armv7m_info.core_mode = ARMV7M_MODE_ANY;
550
551 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
552 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
553 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
554 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
555
556 while (count > 0)
557 {
558 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
559 (buffer_size / 2) : count;
560
561 if ((retval = target_write_buffer(target, source->address,
562 thisrun_count * 2, buffer)) != ERROR_OK)
563 break;
564
565 buf_set_u32(reg_params[0].value, 0, 32, source->address);
566 buf_set_u32(reg_params[1].value, 0, 32, address);
567 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
568
569 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
570 stm32x_info->write_algorithm->address,
571 0,
572 10000, &armv7m_info)) != ERROR_OK)
573 {
574 LOG_ERROR("error executing stm32x flash write algorithm");
575 break;
576 }
577
578 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
579 {
580 LOG_ERROR("flash memory not erased before writing");
581 /* Clear but report errors */
582 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
583 retval = ERROR_FAIL;
584 break;
585 }
586
587 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
588 {
589 LOG_ERROR("flash memory write protected");
590 /* Clear but report errors */
591 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
592 retval = ERROR_FAIL;
593 break;
594 }
595
596 buffer += thisrun_count * 2;
597 address += thisrun_count * 2;
598 count -= thisrun_count;
599 }
600
601 target_free_working_area(target, source);
602 target_free_working_area(target, stm32x_info->write_algorithm);
603
604 destroy_reg_param(&reg_params[0]);
605 destroy_reg_param(&reg_params[1]);
606 destroy_reg_param(&reg_params[2]);
607 destroy_reg_param(&reg_params[3]);
608
609 return retval;
610 }
611
612 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
613 uint32_t offset, uint32_t count)
614 {
615 struct target *target = bank->target;
616 uint32_t words_remaining = (count / 2);
617 uint32_t bytes_remaining = (count & 0x00000001);
618 uint32_t address = bank->base + offset;
619 uint32_t bytes_written = 0;
620 int retval;
621
622 if (bank->target->state != TARGET_HALTED)
623 {
624 LOG_ERROR("Target not halted");
625 return ERROR_TARGET_NOT_HALTED;
626 }
627
628 if (offset & 0x1)
629 {
630 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
631 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
632 }
633
634 /* unlock flash registers */
635 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
636 if (retval != ERROR_OK)
637 return retval;
638 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
639 if (retval != ERROR_OK)
640 return retval;
641
642 /* multiple half words (2-byte) to be programmed? */
643 if (words_remaining > 0)
644 {
645 /* try using a block write */
646 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
647 {
648 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
649 {
650 /* if block write failed (no sufficient working area),
651 * we use normal (slow) single dword accesses */
652 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
653 }
654 }
655 else
656 {
657 buffer += words_remaining * 2;
658 address += words_remaining * 2;
659 words_remaining = 0;
660 }
661 }
662
663 while (words_remaining > 0)
664 {
665 uint16_t value;
666 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
667
668 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
669 if (retval != ERROR_OK)
670 return retval;
671 retval = target_write_u16(target, address, value);
672 if (retval != ERROR_OK)
673 return retval;
674
675 retval = stm32x_wait_status_busy(bank, 5);
676 if (retval != ERROR_OK)
677 return retval;
678
679 bytes_written += 2;
680 words_remaining--;
681 address += 2;
682 }
683
684 if (bytes_remaining)
685 {
686 uint16_t value = 0xffff;
687 memcpy(&value, buffer + bytes_written, bytes_remaining);
688
689 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
690 if (retval != ERROR_OK)
691 return retval;
692 retval = target_write_u16(target, address, value);
693 if (retval != ERROR_OK)
694 return retval;
695
696 retval = stm32x_wait_status_busy(bank, 5);
697 if (retval != ERROR_OK)
698 return retval;
699 }
700
701 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
702 }
703
704 static int stm32x_probe(struct flash_bank *bank)
705 {
706 struct target *target = bank->target;
707 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
708 int i;
709 uint16_t num_pages;
710 uint32_t device_id;
711 int page_size;
712
713 stm32x_info->probed = 0;
714
715 /* read stm32 device id register */
716 target_read_u32(target, 0xE0042000, &device_id);
717 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
718
719 /* get flash size from target */
720 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
721 {
722 /* failed reading flash size, default to max target family */
723 num_pages = 0xffff;
724 }
725
726 if ((device_id & 0x7ff) == 0x410)
727 {
728 /* medium density - we have 1k pages
729 * 4 pages for a protection area */
730 page_size = 1024;
731 stm32x_info->ppage_size = 4;
732
733 /* check for early silicon */
734 if (num_pages == 0xffff)
735 {
736 /* number of sectors incorrect on revA */
737 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
738 num_pages = 128;
739 }
740 }
741 else if ((device_id & 0x7ff) == 0x412)
742 {
743 /* low density - we have 1k pages
744 * 4 pages for a protection area */
745 page_size = 1024;
746 stm32x_info->ppage_size = 4;
747
748 /* check for early silicon */
749 if (num_pages == 0xffff)
750 {
751 /* number of sectors incorrect on revA */
752 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
753 num_pages = 32;
754 }
755 }
756 else if ((device_id & 0x7ff) == 0x414)
757 {
758 /* high density - we have 2k pages
759 * 2 pages for a protection area */
760 page_size = 2048;
761 stm32x_info->ppage_size = 2;
762
763 /* check for early silicon */
764 if (num_pages == 0xffff)
765 {
766 /* number of sectors incorrect on revZ */
767 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
768 num_pages = 512;
769 }
770 }
771 else if ((device_id & 0x7ff) == 0x418)
772 {
773 /* connectivity line density - we have 2k pages
774 * 2 pages for a protection area */
775 page_size = 2048;
776 stm32x_info->ppage_size = 2;
777
778 /* check for early silicon */
779 if (num_pages == 0xffff)
780 {
781 /* number of sectors incorrect on revZ */
782 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
783 num_pages = 256;
784 }
785 }
786 else if ((device_id & 0x7ff) == 0x420)
787 {
788 /* value line density - we have 1k pages
789 * 4 pages for a protection area */
790 page_size = 1024;
791 stm32x_info->ppage_size = 4;
792
793 /* check for early silicon */
794 if (num_pages == 0xffff)
795 {
796 /* number of sectors may be incorrrect on early silicon */
797 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
798 num_pages = 128;
799 }
800 }
801 else
802 {
803 LOG_WARNING("Cannot identify target as a STM32 family.");
804 return ERROR_FAIL;
805 }
806
807 LOG_INFO("flash size = %dkbytes", num_pages);
808
809 /* calculate numbers of pages */
810 num_pages /= (page_size / 1024);
811
812 if (bank->sectors)
813 {
814 free(bank->sectors);
815 bank->sectors = NULL;
816 }
817
818 bank->base = 0x08000000;
819 bank->size = (num_pages * page_size);
820 bank->num_sectors = num_pages;
821 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
822
823 for (i = 0; i < num_pages; i++)
824 {
825 bank->sectors[i].offset = i * page_size;
826 bank->sectors[i].size = page_size;
827 bank->sectors[i].is_erased = -1;
828 bank->sectors[i].is_protected = 1;
829 }
830
831 stm32x_info->probed = 1;
832
833 return ERROR_OK;
834 }
835
836 static int stm32x_auto_probe(struct flash_bank *bank)
837 {
838 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
839 if (stm32x_info->probed)
840 return ERROR_OK;
841 return stm32x_probe(bank);
842 }
843
844 #if 0
845 COMMAND_HANDLER(stm32x_handle_part_id_command)
846 {
847 return ERROR_OK;
848 }
849 #endif
850
851 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
852 {
853 struct target *target = bank->target;
854 uint32_t device_id;
855 int printed;
856
857 /* read stm32 device id register */
858 target_read_u32(target, 0xE0042000, &device_id);
859
860 if ((device_id & 0x7ff) == 0x410)
861 {
862 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
863 buf += printed;
864 buf_size -= printed;
865
866 switch (device_id >> 16)
867 {
868 case 0x0000:
869 snprintf(buf, buf_size, "A");
870 break;
871
872 case 0x2000:
873 snprintf(buf, buf_size, "B");
874 break;
875
876 case 0x2001:
877 snprintf(buf, buf_size, "Z");
878 break;
879
880 case 0x2003:
881 snprintf(buf, buf_size, "Y");
882 break;
883
884 default:
885 snprintf(buf, buf_size, "unknown");
886 break;
887 }
888 }
889 else if ((device_id & 0x7ff) == 0x412)
890 {
891 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
892 buf += printed;
893 buf_size -= printed;
894
895 switch (device_id >> 16)
896 {
897 case 0x1000:
898 snprintf(buf, buf_size, "A");
899 break;
900
901 default:
902 snprintf(buf, buf_size, "unknown");
903 break;
904 }
905 }
906 else if ((device_id & 0x7ff) == 0x414)
907 {
908 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
909 buf += printed;
910 buf_size -= printed;
911
912 switch (device_id >> 16)
913 {
914 case 0x1000:
915 snprintf(buf, buf_size, "A");
916 break;
917
918 case 0x1001:
919 snprintf(buf, buf_size, "Z");
920 break;
921
922 default:
923 snprintf(buf, buf_size, "unknown");
924 break;
925 }
926 }
927 else if ((device_id & 0x7ff) == 0x418)
928 {
929 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
930 buf += printed;
931 buf_size -= printed;
932
933 switch (device_id >> 16)
934 {
935 case 0x1000:
936 snprintf(buf, buf_size, "A");
937 break;
938
939 case 0x1001:
940 snprintf(buf, buf_size, "Z");
941 break;
942
943 default:
944 snprintf(buf, buf_size, "unknown");
945 break;
946 }
947 }
948 else if ((device_id & 0x7ff) == 0x420)
949 {
950 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
951 buf += printed;
952 buf_size -= printed;
953
954 switch (device_id >> 16)
955 {
956 case 0x1000:
957 snprintf(buf, buf_size, "A");
958 break;
959
960 case 0x1001:
961 snprintf(buf, buf_size, "Z");
962 break;
963
964 default:
965 snprintf(buf, buf_size, "unknown");
966 break;
967 }
968 }
969 else
970 {
971 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
972 return ERROR_FAIL;
973 }
974
975 return ERROR_OK;
976 }
977
978 COMMAND_HANDLER(stm32x_handle_lock_command)
979 {
980 struct target *target = NULL;
981 struct stm32x_flash_bank *stm32x_info = NULL;
982
983 if (CMD_ARGC < 1)
984 {
985 command_print(CMD_CTX, "stm32x lock <bank>");
986 return ERROR_OK;
987 }
988
989 struct flash_bank *bank;
990 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
991 if (ERROR_OK != retval)
992 return retval;
993
994 stm32x_info = bank->driver_priv;
995
996 target = bank->target;
997
998 if (target->state != TARGET_HALTED)
999 {
1000 LOG_ERROR("Target not halted");
1001 return ERROR_TARGET_NOT_HALTED;
1002 }
1003
1004 if (stm32x_erase_options(bank) != ERROR_OK)
1005 {
1006 command_print(CMD_CTX, "stm32x failed to erase options");
1007 return ERROR_OK;
1008 }
1009
1010 /* set readout protection */
1011 stm32x_info->option_bytes.RDP = 0;
1012
1013 if (stm32x_write_options(bank) != ERROR_OK)
1014 {
1015 command_print(CMD_CTX, "stm32x failed to lock device");
1016 return ERROR_OK;
1017 }
1018
1019 command_print(CMD_CTX, "stm32x locked");
1020
1021 return ERROR_OK;
1022 }
1023
1024 COMMAND_HANDLER(stm32x_handle_unlock_command)
1025 {
1026 struct target *target = NULL;
1027 struct stm32x_flash_bank *stm32x_info = NULL;
1028
1029 if (CMD_ARGC < 1)
1030 {
1031 command_print(CMD_CTX, "stm32x unlock <bank>");
1032 return ERROR_OK;
1033 }
1034
1035 struct flash_bank *bank;
1036 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1037 if (ERROR_OK != retval)
1038 return retval;
1039
1040 stm32x_info = bank->driver_priv;
1041
1042 target = bank->target;
1043
1044 if (target->state != TARGET_HALTED)
1045 {
1046 LOG_ERROR("Target not halted");
1047 return ERROR_TARGET_NOT_HALTED;
1048 }
1049
1050 if (stm32x_erase_options(bank) != ERROR_OK)
1051 {
1052 command_print(CMD_CTX, "stm32x failed to unlock device");
1053 return ERROR_OK;
1054 }
1055
1056 if (stm32x_write_options(bank) != ERROR_OK)
1057 {
1058 command_print(CMD_CTX, "stm32x failed to lock device");
1059 return ERROR_OK;
1060 }
1061
1062 command_print(CMD_CTX, "stm32x unlocked.\n"
1063 "INFO: a reset or power cycle is required "
1064 "for the new settings to take effect.");
1065
1066 return ERROR_OK;
1067 }
1068
1069 COMMAND_HANDLER(stm32x_handle_options_read_command)
1070 {
1071 uint32_t optionbyte;
1072 struct target *target = NULL;
1073 struct stm32x_flash_bank *stm32x_info = NULL;
1074
1075 if (CMD_ARGC < 1)
1076 {
1077 command_print(CMD_CTX, "stm32x options_read <bank>");
1078 return ERROR_OK;
1079 }
1080
1081 struct flash_bank *bank;
1082 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1083 if (ERROR_OK != retval)
1084 return retval;
1085
1086 stm32x_info = bank->driver_priv;
1087
1088 target = bank->target;
1089
1090 if (target->state != TARGET_HALTED)
1091 {
1092 LOG_ERROR("Target not halted");
1093 return ERROR_TARGET_NOT_HALTED;
1094 }
1095
1096 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1097 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1098
1099 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1100 command_print(CMD_CTX, "Option Byte Complement Error");
1101
1102 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1103 command_print(CMD_CTX, "Readout Protection On");
1104 else
1105 command_print(CMD_CTX, "Readout Protection Off");
1106
1107 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1108 command_print(CMD_CTX, "Software Watchdog");
1109 else
1110 command_print(CMD_CTX, "Hardware Watchdog");
1111
1112 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1113 command_print(CMD_CTX, "Stop: No reset generated");
1114 else
1115 command_print(CMD_CTX, "Stop: Reset generated");
1116
1117 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1118 command_print(CMD_CTX, "Standby: No reset generated");
1119 else
1120 command_print(CMD_CTX, "Standby: Reset generated");
1121
1122 return ERROR_OK;
1123 }
1124
1125 COMMAND_HANDLER(stm32x_handle_options_write_command)
1126 {
1127 struct target *target = NULL;
1128 struct stm32x_flash_bank *stm32x_info = NULL;
1129 uint16_t optionbyte = 0xF8;
1130
1131 if (CMD_ARGC < 4)
1132 {
1133 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1134 return ERROR_OK;
1135 }
1136
1137 struct flash_bank *bank;
1138 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1139 if (ERROR_OK != retval)
1140 return retval;
1141
1142 stm32x_info = bank->driver_priv;
1143
1144 target = bank->target;
1145
1146 if (target->state != TARGET_HALTED)
1147 {
1148 LOG_ERROR("Target not halted");
1149 return ERROR_TARGET_NOT_HALTED;
1150 }
1151
1152 /* REVISIT: ignores some options which we will display...
1153 * and doesn't insist on the specified syntax.
1154 */
1155
1156 /* OPT_RDWDGSW */
1157 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1158 {
1159 optionbyte |= (1 << 0);
1160 }
1161 else /* REVISIT must be "HWWDG" then ... */
1162 {
1163 optionbyte &= ~(1 << 0);
1164 }
1165
1166 /* OPT_RDRSTSTDBY */
1167 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1168 {
1169 optionbyte |= (1 << 1);
1170 }
1171 else /* REVISIT must be "RSTSTNDBY" then ... */
1172 {
1173 optionbyte &= ~(1 << 1);
1174 }
1175
1176 /* OPT_RDRSTSTOP */
1177 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1178 {
1179 optionbyte |= (1 << 2);
1180 }
1181 else /* REVISIT must be "RSTSTOP" then ... */
1182 {
1183 optionbyte &= ~(1 << 2);
1184 }
1185
1186 if (stm32x_erase_options(bank) != ERROR_OK)
1187 {
1188 command_print(CMD_CTX, "stm32x failed to erase options");
1189 return ERROR_OK;
1190 }
1191
1192 stm32x_info->option_bytes.user_options = optionbyte;
1193
1194 if (stm32x_write_options(bank) != ERROR_OK)
1195 {
1196 command_print(CMD_CTX, "stm32x failed to write options");
1197 return ERROR_OK;
1198 }
1199
1200 command_print(CMD_CTX, "stm32x write options complete.\n"
1201 "INFO: a reset or power cycle is required "
1202 "for the new settings to take effect.");
1203
1204 return ERROR_OK;
1205 }
1206
1207 static int stm32x_mass_erase(struct flash_bank *bank)
1208 {
1209 struct target *target = bank->target;
1210
1211 if (target->state != TARGET_HALTED)
1212 {
1213 LOG_ERROR("Target not halted");
1214 return ERROR_TARGET_NOT_HALTED;
1215 }
1216
1217 /* unlock option flash registers */
1218 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1219 if (retval != ERROR_OK)
1220 return retval;
1221 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1222 if (retval != ERROR_OK)
1223 return retval;
1224
1225 /* mass erase flash memory */
1226 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1227 if (retval != ERROR_OK)
1228 return retval;
1229 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1230 if (retval != ERROR_OK)
1231 return retval;
1232
1233 retval = stm32x_wait_status_busy(bank, 100);
1234 if (retval != ERROR_OK)
1235 return retval;
1236
1237 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1238 if (retval != ERROR_OK)
1239 return retval;
1240
1241 return ERROR_OK;
1242 }
1243
1244 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1245 {
1246 int i;
1247
1248 if (CMD_ARGC < 1)
1249 {
1250 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1251 return ERROR_OK;
1252 }
1253
1254 struct flash_bank *bank;
1255 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1256 if (ERROR_OK != retval)
1257 return retval;
1258
1259 retval = stm32x_mass_erase(bank);
1260 if (retval == ERROR_OK)
1261 {
1262 /* set all sectors as erased */
1263 for (i = 0; i < bank->num_sectors; i++)
1264 {
1265 bank->sectors[i].is_erased = 1;
1266 }
1267
1268 command_print(CMD_CTX, "stm32x mass erase complete");
1269 }
1270 else
1271 {
1272 command_print(CMD_CTX, "stm32x mass erase failed");
1273 }
1274
1275 return retval;
1276 }
1277
1278 static const struct command_registration stm32x_exec_command_handlers[] = {
1279 {
1280 .name = "lock",
1281 .handler = stm32x_handle_lock_command,
1282 .mode = COMMAND_EXEC,
1283 .usage = "bank_id",
1284 .help = "Lock entire flash device.",
1285 },
1286 {
1287 .name = "unlock",
1288 .handler = stm32x_handle_unlock_command,
1289 .mode = COMMAND_EXEC,
1290 .usage = "bank_id",
1291 .help = "Unlock entire protected flash device.",
1292 },
1293 {
1294 .name = "mass_erase",
1295 .handler = stm32x_handle_mass_erase_command,
1296 .mode = COMMAND_EXEC,
1297 .usage = "bank_id",
1298 .help = "Erase entire flash device.",
1299 },
1300 {
1301 .name = "options_read",
1302 .handler = stm32x_handle_options_read_command,
1303 .mode = COMMAND_EXEC,
1304 .usage = "bank_id",
1305 .help = "Read and display device option byte.",
1306 },
1307 {
1308 .name = "options_write",
1309 .handler = stm32x_handle_options_write_command,
1310 .mode = COMMAND_EXEC,
1311 .usage = "bank_id ('SWWDG'|'HWWDG') "
1312 "('RSTSTNDBY'|'NORSTSTNDBY') "
1313 "('RSTSTOP'|'NORSTSTOP')",
1314 .help = "Replace bits in device option byte.",
1315 },
1316 COMMAND_REGISTRATION_DONE
1317 };
1318
1319 static const struct command_registration stm32x_command_handlers[] = {
1320 {
1321 .name = "stm32x",
1322 .mode = COMMAND_ANY,
1323 .help = "stm32x flash command group",
1324 .chain = stm32x_exec_command_handlers,
1325 },
1326 COMMAND_REGISTRATION_DONE
1327 };
1328
1329 struct flash_driver stm32x_flash = {
1330 .name = "stm32x",
1331 .commands = stm32x_command_handlers,
1332 .flash_bank_command = stm32x_flash_bank_command,
1333 .erase = stm32x_erase,
1334 .protect = stm32x_protect,
1335 .write = stm32x_write,
1336 .read = default_flash_read,
1337 .probe = stm32x_probe,
1338 .auto_probe = stm32x_auto_probe,
1339 .erase_check = default_flash_mem_blank_check,
1340 .protect_check = stm32x_protect_check,
1341 .info = get_stm32x_info,
1342 };
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