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jtagspi: fix build on MacOS
[openocd.git] / src / flash / nor / str7x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <target/arm.h>
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
33
34 /* Flash registers */
35
36 #define FLASH_CR0 0x00000000
37 #define FLASH_CR1 0x00000004
38 #define FLASH_DR0 0x00000008
39 #define FLASH_DR1 0x0000000C
40 #define FLASH_AR 0x00000010
41 #define FLASH_ER 0x00000014
42 #define FLASH_NVWPAR 0x0000DFB0
43 #define FLASH_NVAPR0 0x0000DFB8
44 #define FLASH_NVAPR1 0x0000DFBC
45
46 /* FLASH_CR0 register bits */
47
48 #define FLASH_WMS 0x80000000
49 #define FLASH_SUSP 0x40000000
50 #define FLASH_WPG 0x20000000
51 #define FLASH_DWPG 0x10000000
52 #define FLASH_SER 0x08000000
53 #define FLASH_SPR 0x01000000
54 #define FLASH_BER 0x04000000
55 #define FLASH_MER 0x02000000
56 #define FLASH_LOCK 0x00000010
57 #define FLASH_BSYA1 0x00000004
58 #define FLASH_BSYA0 0x00000002
59
60 /* FLASH_CR1 register bits */
61
62 #define FLASH_B1S 0x02000000
63 #define FLASH_B0S 0x01000000
64 #define FLASH_B1F1 0x00020000
65 #define FLASH_B1F0 0x00010000
66 #define FLASH_B0F7 0x00000080
67 #define FLASH_B0F6 0x00000040
68 #define FLASH_B0F5 0x00000020
69 #define FLASH_B0F4 0x00000010
70 #define FLASH_B0F3 0x00000008
71 #define FLASH_B0F2 0x00000004
72 #define FLASH_B0F1 0x00000002
73 #define FLASH_B0F0 0x00000001
74
75 /* FLASH_ER register bits */
76
77 #define FLASH_WPF 0x00000100
78 #define FLASH_RESER 0x00000080
79 #define FLASH_SEQER 0x00000040
80 #define FLASH_10ER 0x00000008
81 #define FLASH_PGER 0x00000004
82 #define FLASH_ERER 0x00000002
83 #define FLASH_ERR 0x00000001
84
85
86 struct str7x_flash_bank {
87 uint32_t *sector_bits;
88 uint32_t disable_bit;
89 uint32_t busy_bits;
90 uint32_t register_base;
91 };
92
93 struct str7x_mem_layout {
94 uint32_t sector_start;
95 uint32_t sector_size;
96 uint32_t sector_bit;
97 };
98
99 enum str7x_status_codes {
100 STR7X_CMD_SUCCESS = 0,
101 STR7X_INVALID_COMMAND = 1,
102 STR7X_SRC_ADDR_ERROR = 2,
103 STR7X_DST_ADDR_ERROR = 3,
104 STR7X_SRC_ADDR_NOT_MAPPED = 4,
105 STR7X_DST_ADDR_NOT_MAPPED = 5,
106 STR7X_COUNT_ERROR = 6,
107 STR7X_INVALID_SECTOR = 7,
108 STR7X_SECTOR_NOT_BLANK = 8,
109 STR7X_SECTOR_NOT_PREPARED = 9,
110 STR7X_COMPARE_ERROR = 10,
111 STR7X_BUSY = 11
112 };
113
114 static const struct str7x_mem_layout mem_layout_str7bank0[] = {
115 {0x00000000, 0x02000, 0x01},
116 {0x00002000, 0x02000, 0x02},
117 {0x00004000, 0x02000, 0x04},
118 {0x00006000, 0x02000, 0x08},
119 {0x00008000, 0x08000, 0x10},
120 {0x00010000, 0x10000, 0x20},
121 {0x00020000, 0x10000, 0x40},
122 {0x00030000, 0x10000, 0x80}
123 };
124
125 static const struct str7x_mem_layout mem_layout_str7bank1[] = {
126 {0x00000000, 0x02000, 0x10000},
127 {0x00002000, 0x02000, 0x20000}
128 };
129
130 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
131 {
132 struct str7x_flash_bank *str7x_info = bank->driver_priv;
133 return str7x_info->register_base | reg;
134 }
135
136 static int str7x_build_block_list(struct flash_bank *bank)
137 {
138 struct str7x_flash_bank *str7x_info = bank->driver_priv;
139
140 int i;
141 unsigned int num_sectors;
142 int b0_sectors = 0, b1_sectors = 0;
143
144 switch (bank->size) {
145 case 16 * 1024:
146 b1_sectors = 2;
147 break;
148 case 64 * 1024:
149 b0_sectors = 5;
150 break;
151 case 128 * 1024:
152 b0_sectors = 6;
153 break;
154 case 256 * 1024:
155 b0_sectors = 8;
156 break;
157 default:
158 LOG_ERROR("BUG: unknown bank->size encountered");
159 exit(-1);
160 }
161
162 num_sectors = b0_sectors + b1_sectors;
163
164 bank->num_sectors = num_sectors;
165 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
166 str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
167
168 num_sectors = 0;
169
170 for (i = 0; i < b0_sectors; i++) {
171 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
172 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
173 bank->sectors[num_sectors].is_erased = -1;
174 /* the reset_init handler marks all the sectors unprotected,
175 * matching hardware after reset; keep the driver in sync
176 */
177 bank->sectors[num_sectors].is_protected = 0;
178 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
179 }
180
181 for (i = 0; i < b1_sectors; i++) {
182 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
183 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
184 bank->sectors[num_sectors].is_erased = -1;
185 /* the reset_init handler marks all the sectors unprotected,
186 * matching hardware after reset; keep the driver in sync
187 */
188 bank->sectors[num_sectors].is_protected = 0;
189 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
190 }
191
192 return ERROR_OK;
193 }
194
195 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
196 */
197 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
198 {
199 struct str7x_flash_bank *str7x_info;
200
201 if (CMD_ARGC < 7)
202 return ERROR_COMMAND_SYNTAX_ERROR;
203
204 str7x_info = malloc(sizeof(struct str7x_flash_bank));
205 bank->driver_priv = str7x_info;
206
207 /* set default bits for str71x flash */
208 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
209 str7x_info->disable_bit = (1 << 1);
210
211 if (strcmp(CMD_ARGV[6], "STR71x") == 0)
212 str7x_info->register_base = 0x40100000;
213 else if (strcmp(CMD_ARGV[6], "STR73x") == 0) {
214 str7x_info->register_base = 0x80100000;
215 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
216 } else if (strcmp(CMD_ARGV[6], "STR75x") == 0) {
217 str7x_info->register_base = 0x20100000;
218 str7x_info->disable_bit = (1 << 0);
219 } else {
220 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
221 free(str7x_info);
222 return ERROR_FLASH_BANK_INVALID;
223 }
224
225 str7x_build_block_list(bank);
226
227 return ERROR_OK;
228 }
229
230 /* wait for flash to become idle or report errors.
231
232 FIX!!! what's the maximum timeout??? The documentation doesn't
233 state any maximum time.... by inspection it seems > 1000ms is to be
234 expected.
235
236 10000ms is long enough that it should cover anything, yet not
237 quite be equivalent to an infinite loop.
238
239 */
240 static int str7x_waitbusy(struct flash_bank *bank)
241 {
242 int err;
243 int i;
244 struct target *target = bank->target;
245 struct str7x_flash_bank *str7x_info = bank->driver_priv;
246
247 for (i = 0 ; i < 10000; i++) {
248 uint32_t retval;
249 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
250 if (err != ERROR_OK)
251 return err;
252
253 if ((retval & str7x_info->busy_bits) == 0)
254 return ERROR_OK;
255
256 alive_sleep(1);
257 }
258 LOG_ERROR("Timed out waiting for str7x flash");
259 return ERROR_FAIL;
260 }
261
262
263 static int str7x_result(struct flash_bank *bank)
264 {
265 struct target *target = bank->target;
266 uint32_t flash_flags;
267
268 int retval;
269 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
270 if (retval != ERROR_OK)
271 return retval;
272
273 if (flash_flags & FLASH_WPF) {
274 LOG_ERROR("str7x hw write protection set");
275 retval = ERROR_FAIL;
276 }
277 if (flash_flags & FLASH_RESER) {
278 LOG_ERROR("str7x suspended program erase not resumed");
279 retval = ERROR_FAIL;
280 }
281 if (flash_flags & FLASH_10ER) {
282 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
283 retval = ERROR_FAIL;
284 }
285 if (flash_flags & FLASH_PGER) {
286 LOG_ERROR("str7x program error");
287 retval = ERROR_FAIL;
288 }
289 if (flash_flags & FLASH_ERER) {
290 LOG_ERROR("str7x erase error");
291 retval = ERROR_FAIL;
292 }
293 if (retval == ERROR_OK) {
294 if (flash_flags & FLASH_ERR) {
295 /* this should always be set if one of the others are set... */
296 LOG_ERROR("str7x write operation failed / bad setup");
297 retval = ERROR_FAIL;
298 }
299 }
300
301 return retval;
302 }
303
304 static int str7x_protect_check(struct flash_bank *bank)
305 {
306 struct str7x_flash_bank *str7x_info = bank->driver_priv;
307 struct target *target = bank->target;
308
309 uint32_t flash_flags;
310
311 if (bank->target->state != TARGET_HALTED) {
312 LOG_ERROR("Target not halted");
313 return ERROR_TARGET_NOT_HALTED;
314 }
315
316 int retval;
317 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
318 if (retval != ERROR_OK)
319 return retval;
320
321 for (unsigned int i = 0; i < bank->num_sectors; i++) {
322 if (flash_flags & str7x_info->sector_bits[i])
323 bank->sectors[i].is_protected = 0;
324 else
325 bank->sectors[i].is_protected = 1;
326 }
327
328 return ERROR_OK;
329 }
330
331 static int str7x_erase(struct flash_bank *bank, unsigned int first,
332 unsigned int last)
333 {
334 struct str7x_flash_bank *str7x_info = bank->driver_priv;
335 struct target *target = bank->target;
336
337 uint32_t cmd;
338 uint32_t sectors = 0;
339 int err;
340
341 if (bank->target->state != TARGET_HALTED) {
342 LOG_ERROR("Target not halted");
343 return ERROR_TARGET_NOT_HALTED;
344 }
345
346 for (unsigned int i = first; i <= last; i++)
347 sectors |= str7x_info->sector_bits[i];
348
349 LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
350
351 /* clear FLASH_ER register */
352 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
353 if (err != ERROR_OK)
354 return err;
355
356 cmd = FLASH_SER;
357 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
358 if (err != ERROR_OK)
359 return err;
360
361 cmd = sectors;
362 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
363 if (err != ERROR_OK)
364 return err;
365
366 cmd = FLASH_SER | FLASH_WMS;
367 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
368 if (err != ERROR_OK)
369 return err;
370
371 err = str7x_waitbusy(bank);
372 if (err != ERROR_OK)
373 return err;
374
375 err = str7x_result(bank);
376 if (err != ERROR_OK)
377 return err;
378
379 return ERROR_OK;
380 }
381
382 static int str7x_protect(struct flash_bank *bank, int set, unsigned int first,
383 unsigned int last)
384 {
385 struct str7x_flash_bank *str7x_info = bank->driver_priv;
386 struct target *target = bank->target;
387 uint32_t cmd;
388 uint32_t protect_blocks;
389
390 if (bank->target->state != TARGET_HALTED) {
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED;
393 }
394
395 protect_blocks = 0xFFFFFFFF;
396
397 if (set) {
398 for (unsigned int i = first; i <= last; i++)
399 protect_blocks &= ~(str7x_info->sector_bits[i]);
400 }
401
402 /* clear FLASH_ER register */
403 int err;
404 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
405 if (err != ERROR_OK)
406 return err;
407
408 cmd = FLASH_SPR;
409 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
410 if (err != ERROR_OK)
411 return err;
412
413 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
414 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
415 if (err != ERROR_OK)
416 return err;
417
418 cmd = protect_blocks;
419 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
420 if (err != ERROR_OK)
421 return err;
422
423 cmd = FLASH_SPR | FLASH_WMS;
424 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
425 if (err != ERROR_OK)
426 return err;
427
428 err = str7x_waitbusy(bank);
429 if (err != ERROR_OK)
430 return err;
431
432 err = str7x_result(bank);
433 if (err != ERROR_OK)
434 return err;
435
436 return ERROR_OK;
437 }
438
439 static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
440 uint32_t offset, uint32_t count)
441 {
442 struct str7x_flash_bank *str7x_info = bank->driver_priv;
443 struct target *target = bank->target;
444 uint32_t buffer_size = 32768;
445 struct working_area *write_algorithm;
446 struct working_area *source;
447 uint32_t address = bank->base + offset;
448 struct reg_param reg_params[6];
449 struct arm_algorithm arm_algo;
450 int retval = ERROR_OK;
451
452 /* see contrib/loaders/flash/str7x.s for src */
453
454 static const uint32_t str7x_flash_write_code[] = {
455 /* write: */
456 0xe3a04201, /* mov r4, #0x10000000 */
457 0xe5824000, /* str r4, [r2, #0x0] */
458 0xe5821010, /* str r1, [r2, #0x10] */
459 0xe4904004, /* ldr r4, [r0], #4 */
460 0xe5824008, /* str r4, [r2, #0x8] */
461 0xe4904004, /* ldr r4, [r0], #4 */
462 0xe582400c, /* str r4, [r2, #0xc] */
463 0xe3a04209, /* mov r4, #0x90000000 */
464 0xe5824000, /* str r4, [r2, #0x0] */
465 /* busy: */
466 0xe5924000, /* ldr r4, [r2, #0x0] */
467 0xe1140005, /* tst r4, r5 */
468 0x1afffffc, /* bne busy */
469 0xe5924014, /* ldr r4, [r2, #0x14] */
470 0xe31400ff, /* tst r4, #0xff */
471 0x03140c01, /* tsteq r4, #0x100 */
472 0x1a000002, /* bne exit */
473 0xe2811008, /* add r1, r1, #0x8 */
474 0xe2533001, /* subs r3, r3, #1 */
475 0x1affffec, /* bne write */
476 /* exit: */
477 0xeafffffe, /* b exit */
478 };
479
480 /* flash write code */
481 if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
482 &write_algorithm) != ERROR_OK) {
483 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
484 }
485
486 uint8_t code[sizeof(str7x_flash_write_code)];
487 target_buffer_set_u32_array(target, code, ARRAY_SIZE(str7x_flash_write_code),
488 str7x_flash_write_code);
489 target_write_buffer(target, write_algorithm->address, sizeof(code), code);
490
491 /* memory buffer */
492 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
493 buffer_size /= 2;
494 if (buffer_size <= 256) {
495 /* we already allocated the writing code, but failed to get a
496 * buffer, free the algorithm */
497 target_free_working_area(target, write_algorithm);
498
499 LOG_WARNING("no large enough working area available, can't do block memory writes");
500 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
501 }
502 }
503
504 arm_algo.common_magic = ARM_COMMON_MAGIC;
505 arm_algo.core_mode = ARM_MODE_SVC;
506 arm_algo.core_state = ARM_STATE_ARM;
507
508 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
509 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
510 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
511 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
512 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
513 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
514
515 while (count > 0) {
516 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
517
518 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
519
520 buf_set_u32(reg_params[0].value, 0, 32, source->address);
521 buf_set_u32(reg_params[1].value, 0, 32, address);
522 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
523 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
524 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
525
526 retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
527 write_algorithm->address,
528 write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
529 10000, &arm_algo);
530 if (retval != ERROR_OK)
531 break;
532
533 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00) {
534 retval = str7x_result(bank);
535 break;
536 }
537
538 buffer += thisrun_count * 8;
539 address += thisrun_count * 8;
540 count -= thisrun_count;
541 }
542
543 target_free_working_area(target, source);
544 target_free_working_area(target, write_algorithm);
545
546 destroy_reg_param(&reg_params[0]);
547 destroy_reg_param(&reg_params[1]);
548 destroy_reg_param(&reg_params[2]);
549 destroy_reg_param(&reg_params[3]);
550 destroy_reg_param(&reg_params[4]);
551 destroy_reg_param(&reg_params[5]);
552
553 return retval;
554 }
555
556 static int str7x_write(struct flash_bank *bank, const uint8_t *buffer,
557 uint32_t offset, uint32_t count)
558 {
559 struct target *target = bank->target;
560 uint32_t dwords_remaining = (count / 8);
561 uint32_t bytes_remaining = (count & 0x00000007);
562 uint32_t address = bank->base + offset;
563 uint32_t bytes_written = 0;
564 uint32_t cmd;
565 int retval;
566 uint32_t check_address = offset;
567
568 if (bank->target->state != TARGET_HALTED) {
569 LOG_ERROR("Target not halted");
570 return ERROR_TARGET_NOT_HALTED;
571 }
572
573 if (offset & 0x7) {
574 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
575 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
576 }
577
578 for (unsigned int i = 0; i < bank->num_sectors; i++) {
579 uint32_t sec_start = bank->sectors[i].offset;
580 uint32_t sec_end = sec_start + bank->sectors[i].size;
581
582 /* check if destination falls within the current sector */
583 if ((check_address >= sec_start) && (check_address < sec_end)) {
584 /* check if destination ends in the current sector */
585 if (offset + count < sec_end)
586 check_address = offset + count;
587 else
588 check_address = sec_end;
589 }
590 }
591
592 if (check_address != offset + count)
593 return ERROR_FLASH_DST_OUT_OF_BANK;
594
595 /* clear FLASH_ER register */
596 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
597
598 /* multiple dwords (8-byte) to be programmed? */
599 if (dwords_remaining > 0) {
600 /* try using a block write */
601 retval = str7x_write_block(bank, buffer, offset, dwords_remaining);
602 if (retval != ERROR_OK) {
603 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
604 /* if block write failed (no sufficient working area),
605 * we use normal (slow) single dword accesses */
606 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
607 } else {
608 return retval;
609 }
610 } else {
611 buffer += dwords_remaining * 8;
612 address += dwords_remaining * 8;
613 dwords_remaining = 0;
614 }
615 }
616
617 while (dwords_remaining > 0) {
618 /* command */
619 cmd = FLASH_DWPG;
620 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
621
622 /* address */
623 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
624
625 /* data word 1 */
626 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
627 4, 1, buffer + bytes_written);
628 bytes_written += 4;
629
630 /* data word 2 */
631 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
632 4, 1, buffer + bytes_written);
633 bytes_written += 4;
634
635 /* start programming cycle */
636 cmd = FLASH_DWPG | FLASH_WMS;
637 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
638
639 int err;
640 err = str7x_waitbusy(bank);
641 if (err != ERROR_OK)
642 return err;
643
644 err = str7x_result(bank);
645 if (err != ERROR_OK)
646 return err;
647
648 dwords_remaining--;
649 address += 8;
650 }
651
652 if (bytes_remaining) {
653 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
654
655 /* copy the last remaining bytes into the write buffer */
656 memcpy(last_dword, buffer+bytes_written, bytes_remaining);
657
658 /* command */
659 cmd = FLASH_DWPG;
660 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
661
662 /* address */
663 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
664
665 /* data word 1 */
666 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
667 4, 1, last_dword);
668
669 /* data word 2 */
670 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
671 4, 1, last_dword + 4);
672
673 /* start programming cycle */
674 cmd = FLASH_DWPG | FLASH_WMS;
675 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
676
677 int err;
678 err = str7x_waitbusy(bank);
679 if (err != ERROR_OK)
680 return err;
681
682 err = str7x_result(bank);
683 if (err != ERROR_OK)
684 return err;
685 }
686
687 return ERROR_OK;
688 }
689
690 static int str7x_probe(struct flash_bank *bank)
691 {
692 return ERROR_OK;
693 }
694
695 #if 0
696 COMMAND_HANDLER(str7x_handle_part_id_command)
697 {
698 return ERROR_OK;
699 }
700 #endif
701
702 static int get_str7x_info(struct flash_bank *bank, struct command_invocation *cmd)
703 {
704 /* Setting the write protection on a sector is a permanent change but it
705 * can be disabled temporarily. FLASH_NVWPAR reflects the permanent
706 * protection state of the sectors, not the temporary.
707 */
708 command_print_sameline(cmd, "STR7x flash protection info is only valid after a power cycle, "
709 "clearing the protection is only temporary and may not be reflected in the current "
710 "info returned.");
711 return ERROR_OK;
712 }
713
714 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
715 {
716 struct target *target = NULL;
717 struct str7x_flash_bank *str7x_info = NULL;
718
719 uint32_t flash_cmd;
720 uint16_t protection_level = 0;
721 uint16_t protection_regs;
722
723 if (CMD_ARGC < 1)
724 return ERROR_COMMAND_SYNTAX_ERROR;
725
726 struct flash_bank *bank;
727 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
728 if (retval != ERROR_OK)
729 return retval;
730
731 str7x_info = bank->driver_priv;
732
733 target = bank->target;
734
735 if (target->state != TARGET_HALTED) {
736 LOG_ERROR("Target not halted");
737 return ERROR_TARGET_NOT_HALTED;
738 }
739
740 /* first we get protection status */
741 uint32_t reg;
742 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
743
744 if (!(reg & str7x_info->disable_bit))
745 protection_level = 1;
746
747 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
748 protection_regs = ~(reg >> 16);
749
750 while (((protection_regs) != 0) && (protection_level < 16)) {
751 protection_regs >>= 1;
752 protection_level++;
753 }
754
755 if (protection_level == 0) {
756 flash_cmd = FLASH_SPR;
757 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
758 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
759 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
760 flash_cmd = FLASH_SPR | FLASH_WMS;
761 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
762 } else {
763 flash_cmd = FLASH_SPR;
764 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
765 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
766 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
767 ~(1 << (15 + protection_level)));
768 flash_cmd = FLASH_SPR | FLASH_WMS;
769 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
770 }
771
772 return ERROR_OK;
773 }
774
775 static const struct command_registration str7x_exec_command_handlers[] = {
776 {
777 .name = "disable_jtag",
778 .usage = "<bank>",
779 .handler = str7x_handle_disable_jtag_command,
780 .mode = COMMAND_EXEC,
781 .help = "disable jtag access",
782 },
783 COMMAND_REGISTRATION_DONE
784 };
785
786 static const struct command_registration str7x_command_handlers[] = {
787 {
788 .name = "str7x",
789 .mode = COMMAND_ANY,
790 .help = "str7x flash command group",
791 .usage = "",
792 .chain = str7x_exec_command_handlers,
793 },
794 COMMAND_REGISTRATION_DONE
795 };
796
797 const struct flash_driver str7x_flash = {
798 .name = "str7x",
799 .commands = str7x_command_handlers,
800 .flash_bank_command = str7x_flash_bank_command,
801 .erase = str7x_erase,
802 .protect = str7x_protect,
803 .write = str7x_write,
804 .read = default_flash_read,
805 .probe = str7x_probe,
806 .auto_probe = str7x_probe,
807 .erase_check = default_flash_blank_check,
808 .protect_check = str7x_protect_check,
809 .info = get_str7x_info,
810 .free_driver_priv = default_flash_free_driver_priv,
811 };
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