1 /***************************************************************************
2 * Copyright (C) 2007,2008 by Christopher Kilgour *
3 * techie |_at_| whiterocker |_dot_| com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
25 /* ----------------------------------------------------------------------
26 * Internal Support, Helpers
27 * ---------------------------------------------------------------------- */
29 struct tms470_flash_bank
{
32 /* device identification register */
33 uint32_t device_ident_reg
;
34 uint32_t silicon_version
;
35 uint32_t technology_family
;
38 const char *part_name
;
42 static const struct flash_sector TMS470R1A256_SECTORS
[] = {
43 {0x00000000, 0x00002000, -1, -1},
44 {0x00002000, 0x00002000, -1, -1},
45 {0x00004000, 0x00002000, -1, -1},
46 {0x00006000, 0x00002000, -1, -1},
47 {0x00008000, 0x00008000, -1, -1},
48 {0x00010000, 0x00008000, -1, -1},
49 {0x00018000, 0x00008000, -1, -1},
50 {0x00020000, 0x00008000, -1, -1},
51 {0x00028000, 0x00008000, -1, -1},
52 {0x00030000, 0x00008000, -1, -1},
53 {0x00038000, 0x00002000, -1, -1},
54 {0x0003A000, 0x00002000, -1, -1},
55 {0x0003C000, 0x00002000, -1, -1},
56 {0x0003E000, 0x00002000, -1, -1},
59 #define TMS470R1A256_NUM_SECTORS \
60 ARRAY_SIZE(TMS470R1A256_SECTORS)
62 static const struct flash_sector TMS470R1A288_BANK0_SECTORS
[] = {
63 {0x00000000, 0x00002000, -1, -1},
64 {0x00002000, 0x00002000, -1, -1},
65 {0x00004000, 0x00002000, -1, -1},
66 {0x00006000, 0x00002000, -1, -1},
69 #define TMS470R1A288_BANK0_NUM_SECTORS \
70 ARRAY_SIZE(TMS470R1A288_BANK0_SECTORS)
72 static const struct flash_sector TMS470R1A288_BANK1_SECTORS
[] = {
73 {0x00040000, 0x00010000, -1, -1},
74 {0x00050000, 0x00010000, -1, -1},
75 {0x00060000, 0x00010000, -1, -1},
76 {0x00070000, 0x00010000, -1, -1},
79 #define TMS470R1A288_BANK1_NUM_SECTORS \
80 ARRAY_SIZE(TMS470R1A288_BANK1_SECTORS)
82 static const struct flash_sector TMS470R1A384_BANK0_SECTORS
[] = {
83 {0x00000000, 0x00002000, -1, -1},
84 {0x00002000, 0x00002000, -1, -1},
85 {0x00004000, 0x00004000, -1, -1},
86 {0x00008000, 0x00004000, -1, -1},
87 {0x0000C000, 0x00004000, -1, -1},
88 {0x00010000, 0x00004000, -1, -1},
89 {0x00014000, 0x00004000, -1, -1},
90 {0x00018000, 0x00002000, -1, -1},
91 {0x0001C000, 0x00002000, -1, -1},
92 {0x0001E000, 0x00002000, -1, -1},
95 #define TMS470R1A384_BANK0_NUM_SECTORS \
96 ARRAY_SIZE(TMS470R1A384_BANK0_SECTORS)
98 static const struct flash_sector TMS470R1A384_BANK1_SECTORS
[] = {
99 {0x00020000, 0x00008000, -1, -1},
100 {0x00028000, 0x00008000, -1, -1},
101 {0x00030000, 0x00008000, -1, -1},
102 {0x00038000, 0x00008000, -1, -1},
105 #define TMS470R1A384_BANK1_NUM_SECTORS \
106 ARRAY_SIZE(TMS470R1A384_BANK1_SECTORS)
108 static const struct flash_sector TMS470R1A384_BANK2_SECTORS
[] = {
109 {0x00040000, 0x00008000, -1, -1},
110 {0x00048000, 0x00008000, -1, -1},
111 {0x00050000, 0x00008000, -1, -1},
112 {0x00058000, 0x00008000, -1, -1},
115 #define TMS470R1A384_BANK2_NUM_SECTORS \
116 ARRAY_SIZE(TMS470R1A384_BANK2_SECTORS)
118 /* ---------------------------------------------------------------------- */
120 static int tms470_read_part_info(struct flash_bank
*bank
)
122 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
123 struct target
*target
= bank
->target
;
124 uint32_t device_ident_reg
;
125 uint32_t silicon_version
;
126 uint32_t technology_family
;
128 uint32_t part_number
;
129 const char *part_name
;
131 /* we shall not rely on the caller in this test, this function allocates memory,
132 thus and executing the code more than once may cause memory leak */
133 if (tms470_info
->device_ident_reg
)
136 /* read and parse the device identification register */
137 target_read_u32(target
, 0xFFFFFFF0, &device_ident_reg
);
139 LOG_INFO("device_ident_reg = 0x%08" PRIx32
"", device_ident_reg
);
141 if ((device_ident_reg
& 7) == 0) {
142 LOG_WARNING("Cannot identify target as a TMS470 family.");
143 return ERROR_FLASH_OPERATION_FAILED
;
146 silicon_version
= (device_ident_reg
>> 12) & 0xF;
147 technology_family
= (device_ident_reg
>> 11) & 1;
148 rom_flash
= (device_ident_reg
>> 10) & 1;
149 part_number
= (device_ident_reg
>> 3) & 0x7f;
153 bank
->sectors
= NULL
;
154 bank
->num_sectors
= 0;
158 * If the part number is known, determine if the flash bank is valid
159 * based on the base address being within the known flash bank
160 * ranges. Then fixup/complete the remaining fields of the flash
163 switch (part_number
) {
165 part_name
= "TMS470R1A256";
167 if (bank
->base
>= 0x00040000) {
168 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32
".",
171 return ERROR_FLASH_OPERATION_FAILED
;
173 tms470_info
->ordinal
= 0;
174 bank
->base
= 0x00000000;
175 bank
->size
= 256 * 1024;
176 bank
->num_sectors
= TMS470R1A256_NUM_SECTORS
;
177 bank
->sectors
= malloc(sizeof(TMS470R1A256_SECTORS
));
179 return ERROR_FLASH_OPERATION_FAILED
;
180 (void)memcpy(bank
->sectors
, TMS470R1A256_SECTORS
, sizeof(TMS470R1A256_SECTORS
));
184 part_name
= "TMS470R1A288";
186 if (bank
->base
< 0x00008000) {
187 tms470_info
->ordinal
= 0;
188 bank
->base
= 0x00000000;
189 bank
->size
= 32 * 1024;
190 bank
->num_sectors
= TMS470R1A288_BANK0_NUM_SECTORS
;
191 bank
->sectors
= malloc(sizeof(TMS470R1A288_BANK0_SECTORS
));
193 return ERROR_FLASH_OPERATION_FAILED
;
194 (void)memcpy(bank
->sectors
, TMS470R1A288_BANK0_SECTORS
,
195 sizeof(TMS470R1A288_BANK0_SECTORS
));
196 } else if ((bank
->base
>= 0x00040000) && (bank
->base
< 0x00080000)) {
197 tms470_info
->ordinal
= 1;
198 bank
->base
= 0x00040000;
199 bank
->size
= 256 * 1024;
200 bank
->num_sectors
= TMS470R1A288_BANK1_NUM_SECTORS
;
201 bank
->sectors
= malloc(sizeof(TMS470R1A288_BANK1_SECTORS
));
203 return ERROR_FLASH_OPERATION_FAILED
;
204 (void)memcpy(bank
->sectors
, TMS470R1A288_BANK1_SECTORS
,
205 sizeof(TMS470R1A288_BANK1_SECTORS
));
207 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32
".",
208 part_name
, bank
->base
);
209 return ERROR_FLASH_OPERATION_FAILED
;
214 part_name
= "TMS470R1A384";
216 if (bank
->base
< 0x00020000) {
217 tms470_info
->ordinal
= 0;
218 bank
->base
= 0x00000000;
219 bank
->size
= 128 * 1024;
220 bank
->num_sectors
= TMS470R1A384_BANK0_NUM_SECTORS
;
221 bank
->sectors
= malloc(sizeof(TMS470R1A384_BANK0_SECTORS
));
223 return ERROR_FLASH_OPERATION_FAILED
;
224 (void)memcpy(bank
->sectors
, TMS470R1A384_BANK0_SECTORS
,
225 sizeof(TMS470R1A384_BANK0_SECTORS
));
226 } else if ((bank
->base
>= 0x00020000) && (bank
->base
< 0x00040000)) {
227 tms470_info
->ordinal
= 1;
228 bank
->base
= 0x00020000;
229 bank
->size
= 128 * 1024;
230 bank
->num_sectors
= TMS470R1A384_BANK1_NUM_SECTORS
;
231 bank
->sectors
= malloc(sizeof(TMS470R1A384_BANK1_SECTORS
));
233 return ERROR_FLASH_OPERATION_FAILED
;
234 (void)memcpy(bank
->sectors
, TMS470R1A384_BANK1_SECTORS
,
235 sizeof(TMS470R1A384_BANK1_SECTORS
));
236 } else if ((bank
->base
>= 0x00040000) && (bank
->base
< 0x00060000)) {
237 tms470_info
->ordinal
= 2;
238 bank
->base
= 0x00040000;
239 bank
->size
= 128 * 1024;
240 bank
->num_sectors
= TMS470R1A384_BANK2_NUM_SECTORS
;
241 bank
->sectors
= malloc(sizeof(TMS470R1A384_BANK2_SECTORS
));
243 return ERROR_FLASH_OPERATION_FAILED
;
244 (void)memcpy(bank
->sectors
, TMS470R1A384_BANK2_SECTORS
,
245 sizeof(TMS470R1A384_BANK2_SECTORS
));
247 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32
".",
248 part_name
, bank
->base
);
249 return ERROR_FLASH_OPERATION_FAILED
;
254 LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.",
255 (unsigned)part_number
);
256 return ERROR_FLASH_OPERATION_FAILED
;
259 /* turn off memory selects */
260 target_write_u32(target
, 0xFFFFFFE4, 0x00000000);
261 target_write_u32(target
, 0xFFFFFFE0, 0x00000000);
263 bank
->chip_width
= 32;
264 bank
->bus_width
= 32;
266 LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
268 (int)(silicon_version
),
269 (technology_family
? "1.8v" : "3.3v"),
270 (rom_flash
? "rom" : "flash"));
272 tms470_info
->device_ident_reg
= device_ident_reg
;
273 tms470_info
->silicon_version
= silicon_version
;
274 tms470_info
->technology_family
= technology_family
;
275 tms470_info
->rom_flash
= rom_flash
;
276 tms470_info
->part_number
= part_number
;
277 tms470_info
->part_name
= part_name
;
280 * Disable reset on address access violation.
282 target_write_u32(target
, 0xFFFFFFE0, 0x00004007);
287 /* ---------------------------------------------------------------------- */
289 static uint32_t keysSet
;
290 static uint32_t flashKeys
[4];
292 COMMAND_HANDLER(tms470_handle_flash_keyset_command
)
295 return ERROR_COMMAND_SYNTAX_ERROR
;
296 else if (CMD_ARGC
== 4) {
299 for (i
= 0; i
< 4; i
++) {
300 int start
= (0 == strncmp(CMD_ARGV
[i
], "0x", 2)) ? 2 : 0;
302 if (1 != sscanf(&CMD_ARGV
[i
][start
], "%" SCNx32
"", &flashKeys
[i
])) {
303 command_print(CMD_CTX
, "could not process flash key %s",
305 LOG_ERROR("could not process flash key %s", CMD_ARGV
[i
]);
306 return ERROR_COMMAND_SYNTAX_ERROR
;
311 } else if (CMD_ARGC
!= 0) {
312 command_print(CMD_CTX
, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
313 return ERROR_COMMAND_SYNTAX_ERROR
;
317 command_print(CMD_CTX
,
318 "using flash keys 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
"",
324 command_print(CMD_CTX
, "flash keys not set");
329 static const uint32_t FLASH_KEYS_ALL_ONES
[] = { 0xFFFFFFFF, 0xFFFFFFFF,
330 0xFFFFFFFF, 0xFFFFFFFF,};
332 static const uint32_t FLASH_KEYS_ALL_ZEROS
[] = { 0x00000000, 0x00000000,
333 0x00000000, 0x00000000,};
335 static const uint32_t FLASH_KEYS_MIX1
[] = { 0xf0fff0ff, 0xf0fff0ff,
336 0xf0fff0ff, 0xf0fff0ff};
338 static const uint32_t FLASH_KEYS_MIX2
[] = { 0x0000ffff, 0x0000ffff,
339 0x0000ffff, 0x0000ffff};
341 /* ---------------------------------------------------------------------- */
343 static int oscMHz
= 12;
345 COMMAND_HANDLER(tms470_handle_osc_megahertz_command
)
348 return ERROR_COMMAND_SYNTAX_ERROR
;
349 else if (CMD_ARGC
== 1)
350 sscanf(CMD_ARGV
[0], "%d", &oscMHz
);
353 LOG_ERROR("osc_megahertz must be positive and non-zero!");
354 command_print(CMD_CTX
, "osc_megahertz must be positive and non-zero!");
356 return ERROR_COMMAND_SYNTAX_ERROR
;
359 command_print(CMD_CTX
, "osc_megahertz=%d", oscMHz
);
364 /* ---------------------------------------------------------------------- */
368 COMMAND_HANDLER(tms470_handle_plldis_command
)
371 return ERROR_COMMAND_SYNTAX_ERROR
;
372 else if (CMD_ARGC
== 1) {
373 sscanf(CMD_ARGV
[0], "%d", &plldis
);
374 plldis
= plldis
? 1 : 0;
377 command_print(CMD_CTX
, "plldis=%d", plldis
);
382 /* ---------------------------------------------------------------------- */
384 static int tms470_check_flash_unlocked(struct target
*target
)
388 target_read_u32(target
, 0xFFE89C08, &fmbbusy
);
389 LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32
" -> %s",
391 fmbbusy
& 0x8000 ? "unlocked" : "LOCKED");
392 return fmbbusy
& 0x8000 ? ERROR_OK
: ERROR_FLASH_OPERATION_FAILED
;
395 /* ---------------------------------------------------------------------- */
397 static int tms470_try_flash_keys(struct target
*target
, const uint32_t *key_set
)
399 uint32_t glbctrl
, fmmstat
;
400 int retval
= ERROR_FLASH_OPERATION_FAILED
;
403 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
404 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
406 /* only perform the key match when 3VSTAT is clear */
407 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
408 if (!(fmmstat
& 0x08)) {
410 uint32_t fmbptr
, fmbac2
, orig_fmregopt
;
412 target_write_u32(target
, 0xFFE8BC04, fmmstat
& ~0x07);
414 /* wait for pump ready */
416 target_read_u32(target
, 0xFFE8A814, &fmbptr
);
418 } while (!(fmbptr
& 0x0200));
420 /* force max wait states */
421 target_read_u32(target
, 0xFFE88004, &fmbac2
);
422 target_write_u32(target
, 0xFFE88004, fmbac2
| 0xff);
424 /* save current access mode, force normal read mode */
425 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
426 target_write_u32(target
, 0xFFE89C00, 0x00);
428 for (i
= 0; i
< 4; i
++) {
431 /* There is no point displaying the value of tmp, it is
432 * filtered by the chip. The purpose of this read is to
433 * prime the unlocking logic rather than read out the value.
435 target_read_u32(target
, 0x00001FF0 + 4 * i
, &tmp
);
437 LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32
"", key_set
[i
]);
438 target_write_u32(target
, 0xFFE89C0C, key_set
[i
]);
441 if (ERROR_OK
== tms470_check_flash_unlocked(target
)) {
443 * There seems to be a side-effect of reading the FMPKEY
444 * register in that it re-enables the protection. So we
447 for (i
= 0; i
< 4; i
++) {
450 target_read_u32(target
, 0x00001FF0 + 4 * i
, &tmp
);
451 target_write_u32(target
, 0xFFE89C0C, key_set
[i
]);
456 /* restore settings */
457 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
458 target_write_u32(target
, 0xFFE88004, fmbac2
);
461 /* clear config bit */
462 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
467 /* ---------------------------------------------------------------------- */
469 static int tms470_unlock_flash(struct flash_bank
*bank
)
471 struct target
*target
= bank
->target
;
472 const uint32_t *p_key_sets
[5];
473 unsigned i
, key_set_count
;
477 p_key_sets
[0] = flashKeys
;
478 p_key_sets
[1] = FLASH_KEYS_ALL_ONES
;
479 p_key_sets
[2] = FLASH_KEYS_ALL_ZEROS
;
480 p_key_sets
[3] = FLASH_KEYS_MIX1
;
481 p_key_sets
[4] = FLASH_KEYS_MIX2
;
484 p_key_sets
[0] = FLASH_KEYS_ALL_ONES
;
485 p_key_sets
[1] = FLASH_KEYS_ALL_ZEROS
;
486 p_key_sets
[2] = FLASH_KEYS_MIX1
;
487 p_key_sets
[3] = FLASH_KEYS_MIX2
;
490 for (i
= 0; i
< key_set_count
; i
++) {
491 if (tms470_try_flash_keys(target
, p_key_sets
[i
]) == ERROR_OK
) {
492 LOG_INFO("tms470 flash is unlocked");
497 LOG_WARNING("tms470 could not unlock flash memory protection level 2");
498 return ERROR_FLASH_OPERATION_FAILED
;
501 /* ---------------------------------------------------------------------- */
503 static int tms470_flash_initialize_internal_state_machine(struct flash_bank
*bank
)
505 uint32_t fmmac2
, fmmac1
, fmmaxep
, k
, delay
, glbctrl
, sysclk
;
506 struct target
*target
= bank
->target
;
507 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
508 int result
= ERROR_OK
;
511 * Select the desired bank to be programmed by writing BANK[2:0] of
514 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
516 fmmac2
|= (tms470_info
->ordinal
& 7);
517 target_write_u32(target
, 0xFFE8BC04, fmmac2
);
518 LOG_DEBUG("set fmmac2 = 0x%04" PRIx32
"", fmmac2
);
521 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
523 target_read_u32(target
, 0xFFE8BC00, &fmmac1
);
525 target_write_u32(target
, 0xFFE8BC00, fmmac1
);
526 LOG_DEBUG("set fmmac1 = 0x%04" PRIx32
"", fmmac1
);
531 target_write_u32(target
, 0xFFE8BC10, 0x2fc0);
532 LOG_DEBUG("set fmtcreg = 0x2fc0");
537 target_write_u32(target
, 0xFFE8A07C, 50);
538 LOG_DEBUG("set fmmaxpp = 50");
541 * MAXCP = 0xf000 + 2000
543 target_write_u32(target
, 0xFFE8A084, 0xf000 + 2000);
544 LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
549 target_read_u32(target
, 0xFFE8A080, &fmmaxep
);
550 if (fmmaxep
== 0xf000) {
551 fmmaxep
= 0xf000 + 4095;
552 target_write_u32(target
, 0xFFE8A80C, 0x9964);
553 LOG_DEBUG("set fmptr3 = 0x9964");
555 fmmaxep
= 0xa000 + 4095;
556 target_write_u32(target
, 0xFFE8A80C, 0x9b64);
557 LOG_DEBUG("set fmptr3 = 0x9b64");
559 target_write_u32(target
, 0xFFE8A080, fmmaxep
);
560 LOG_DEBUG("set fmmaxep = 0x%04" PRIx32
"", fmmaxep
);
565 target_write_u32(target
, 0xFFE8A810, 0xa000);
566 LOG_DEBUG("set fmptr4 = 0xa000");
569 * FMPESETUP, delay parameter selected based on clock frequency.
571 * According to the TI App Note SPNU257 and flashing code, delay is
572 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
573 * clock is usually derived from the ZPLL module, and selected by
576 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
577 sysclk
= (plldis
? 1 : (glbctrl
& 0x08) ? 4 : 8) * oscMHz
/ (1 + (glbctrl
& 7));
578 delay
= (sysclk
> 10) ? (sysclk
+ 1) / 2 : 5;
579 target_write_u32(target
, 0xFFE8A018, (delay
<< 4) | (delay
<< 8));
580 LOG_DEBUG("set fmpsetup = 0x%04" PRIx32
"", (delay
<< 4) | (delay
<< 8));
583 * FMPVEVACCESS, based on delay.
585 k
= delay
| (delay
<< 8);
586 target_write_u32(target
, 0xFFE8A05C, k
);
587 LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32
"", k
);
590 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
593 target_write_u32(target
, 0xFFE8A034, k
);
594 LOG_DEBUG("set fmpchold = 0x%04" PRIx32
"", k
);
595 target_write_u32(target
, 0xFFE8A040, k
);
596 LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32
"", k
);
597 target_write_u32(target
, 0xFFE8A024, k
);
598 LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32
"", k
);
601 * FMCVACCESS, based on delay.
604 target_write_u32(target
, 0xFFE8A060, k
);
605 LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32
"", k
);
608 * FMCSETUP, based on delay.
610 k
= 0x3000 | delay
* 20;
611 target_write_u32(target
, 0xFFE8A020, k
);
612 LOG_DEBUG("set fmcsetup = 0x%04" PRIx32
"", k
);
615 * FMEHOLD, based on delay.
617 k
= (delay
* 20) << 2;
618 target_write_u32(target
, 0xFFE8A038, k
);
619 LOG_DEBUG("set fmehold = 0x%04" PRIx32
"", k
);
622 * PWIDTH, CWIDTH, EWIDTH, based on delay.
624 target_write_u32(target
, 0xFFE8A050, delay
* 8);
625 LOG_DEBUG("set fmpwidth = 0x%04" PRIx32
"", delay
* 8);
626 target_write_u32(target
, 0xFFE8A058, delay
* 1000);
627 LOG_DEBUG("set fmcwidth = 0x%04" PRIx32
"", delay
* 1000);
628 target_write_u32(target
, 0xFFE8A054, delay
* 5400);
629 LOG_DEBUG("set fmewidth = 0x%04" PRIx32
"", delay
* 5400);
634 /* ---------------------------------------------------------------------- */
636 static int tms470_flash_status(struct flash_bank
*bank
)
638 struct target
*target
= bank
->target
;
639 int result
= ERROR_OK
;
642 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
643 LOG_DEBUG("set fmmstat = 0x%04" PRIx32
"", fmmstat
);
645 if (fmmstat
& 0x0080) {
646 LOG_WARNING("tms470 flash command: erase still active after busy clear.");
647 result
= ERROR_FLASH_OPERATION_FAILED
;
650 if (fmmstat
& 0x0040) {
651 LOG_WARNING("tms470 flash command: program still active after busy clear.");
652 result
= ERROR_FLASH_OPERATION_FAILED
;
655 if (fmmstat
& 0x0020) {
656 LOG_WARNING("tms470 flash command: invalid data command.");
657 result
= ERROR_FLASH_OPERATION_FAILED
;
660 if (fmmstat
& 0x0010) {
661 LOG_WARNING("tms470 flash command: program, erase or validate sector failed.");
662 result
= ERROR_FLASH_OPERATION_FAILED
;
665 if (fmmstat
& 0x0008) {
666 LOG_WARNING("tms470 flash command: voltage instability detected.");
667 result
= ERROR_FLASH_OPERATION_FAILED
;
670 if (fmmstat
& 0x0006) {
671 LOG_WARNING("tms470 flash command: command suspend detected.");
672 result
= ERROR_FLASH_OPERATION_FAILED
;
675 if (fmmstat
& 0x0001) {
676 LOG_WARNING("tms470 flash command: sector was locked.");
677 result
= ERROR_FLASH_OPERATION_FAILED
;
683 /* ---------------------------------------------------------------------- */
685 static int tms470_erase_sector(struct flash_bank
*bank
, int sector
)
687 uint32_t glbctrl
, orig_fmregopt
, fmbsea
, fmbseb
, fmmstat
;
688 struct target
*target
= bank
->target
;
689 uint32_t flashAddr
= bank
->base
+ bank
->sectors
[sector
].offset
;
690 int result
= ERROR_OK
;
693 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
694 * module) to enable writing to the flash registers }.
696 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
697 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
698 LOG_DEBUG("set glbctrl = 0x%08" PRIx32
"", glbctrl
| 0x10);
700 /* Force normal read mode. */
701 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
702 target_write_u32(target
, 0xFFE89C00, 0);
703 LOG_DEBUG("set fmregopt = 0x%08x", 0);
705 (void)tms470_flash_initialize_internal_state_machine(bank
);
708 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
709 * protection for the particular sector to be erased/written.
712 target_read_u32(target
, 0xFFE88008, &fmbsea
);
713 target_write_u32(target
, 0xFFE88008, fmbsea
| (1 << sector
));
714 LOG_DEBUG("set fmbsea = 0x%04" PRIx32
"", fmbsea
| (1 << sector
));
716 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
717 target_write_u32(target
, 0xFFE8800C, fmbseb
| (1 << (sector
- 16)));
718 LOG_DEBUG("set fmbseb = 0x%04" PRIx32
"", fmbseb
| (1 << (sector
- 16)));
720 bank
->sectors
[sector
].is_protected
= 0;
723 * clear status regiser, sent erase command, kickoff erase
725 target_write_u16(target
, flashAddr
, 0x0040);
726 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32
"=0x0040", flashAddr
);
727 target_write_u16(target
, flashAddr
, 0x0020);
728 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32
"=0x0020", flashAddr
);
729 target_write_u16(target
, flashAddr
, 0xffff);
730 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32
"=0xffff", flashAddr
);
733 * Monitor FMMSTAT, busy until clear, then check and other flags for
734 * ultimate result of the operation.
737 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
738 if (fmmstat
& 0x0100)
740 } while (fmmstat
& 0x0100);
742 result
= tms470_flash_status(bank
);
745 target_write_u32(target
, 0xFFE88008, fmbsea
);
746 LOG_DEBUG("set fmbsea = 0x%04" PRIx32
"", fmbsea
);
747 bank
->sectors
[sector
].is_protected
= fmbsea
& (1 << sector
) ? 0 : 1;
749 target_write_u32(target
, 0xFFE8800C, fmbseb
);
750 LOG_DEBUG("set fmbseb = 0x%04" PRIx32
"", fmbseb
);
751 bank
->sectors
[sector
].is_protected
= fmbseb
& (1 << (sector
- 16)) ? 0 : 1;
753 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
754 LOG_DEBUG("set fmregopt = 0x%08" PRIx32
"", orig_fmregopt
);
755 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
756 LOG_DEBUG("set glbctrl = 0x%08" PRIx32
"", glbctrl
);
761 /*----------------------------------------------------------------------
762 * Implementation of Flash Driver Interfaces
763 *---------------------------------------------------------------------- */
765 static const struct command_registration tms470_any_command_handlers
[] = {
767 .name
= "flash_keyset",
768 .usage
= "<key0> <key1> <key2> <key3>",
769 .handler
= tms470_handle_flash_keyset_command
,
771 .help
= "tms470 flash_keyset <key0> <key1> <key2> <key3>",
774 .name
= "osc_megahertz",
776 .handler
= tms470_handle_osc_megahertz_command
,
778 .help
= "tms470 osc_megahertz <MHz>",
783 .handler
= tms470_handle_plldis_command
,
785 .help
= "tms470 plldis <0/1>",
787 COMMAND_REGISTRATION_DONE
789 static const struct command_registration tms470_command_handlers
[] = {
793 .help
= "TI tms470 flash command group",
795 .chain
= tms470_any_command_handlers
,
797 COMMAND_REGISTRATION_DONE
800 /* ---------------------------------------------------------------------- */
802 static int tms470_erase(struct flash_bank
*bank
, int first
, int last
)
804 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
805 int sector
, result
= ERROR_OK
;
807 if (bank
->target
->state
!= TARGET_HALTED
) {
808 LOG_ERROR("Target not halted");
809 return ERROR_TARGET_NOT_HALTED
;
812 tms470_read_part_info(bank
);
814 if ((first
< 0) || (first
>= bank
->num_sectors
) || (last
< 0) ||
815 (last
>= bank
->num_sectors
) || (first
> last
)) {
816 LOG_ERROR("Sector range %d to %d invalid.", first
, last
);
817 return ERROR_FLASH_SECTOR_INVALID
;
820 result
= tms470_unlock_flash(bank
);
821 if (result
!= ERROR_OK
)
824 for (sector
= first
; sector
<= last
; sector
++) {
825 LOG_INFO("Erasing tms470 bank %d sector %d...", tms470_info
->ordinal
, sector
);
827 result
= tms470_erase_sector(bank
, sector
);
829 if (result
!= ERROR_OK
) {
830 LOG_ERROR("tms470 could not erase flash sector.");
833 LOG_INFO("sector erased successfully.");
839 /* ---------------------------------------------------------------------- */
841 static int tms470_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
843 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
844 struct target
*target
= bank
->target
;
845 uint32_t fmmac2
, fmbsea
, fmbseb
;
848 if (target
->state
!= TARGET_HALTED
) {
849 LOG_ERROR("Target not halted");
850 return ERROR_TARGET_NOT_HALTED
;
853 tms470_read_part_info(bank
);
855 if ((first
< 0) || (first
>= bank
->num_sectors
) || (last
< 0) ||
856 (last
>= bank
->num_sectors
) || (first
> last
)) {
857 LOG_ERROR("Sector range %d to %d invalid.", first
, last
);
858 return ERROR_FLASH_SECTOR_INVALID
;
861 /* enable the appropriate bank */
862 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
863 target_write_u32(target
, 0xFFE8BC04, (fmmac2
& ~7) | tms470_info
->ordinal
);
865 /* get the original sector proection flags for this bank */
866 target_read_u32(target
, 0xFFE88008, &fmbsea
);
867 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
869 for (sector
= 0; sector
< bank
->num_sectors
; sector
++) {
871 fmbsea
= set
? fmbsea
& ~(1 << sector
) : fmbsea
| (1 << sector
);
872 bank
->sectors
[sector
].is_protected
= set
? 1 : 0;
874 fmbseb
= set
? fmbseb
&
875 ~(1 << (sector
- 16)) : fmbseb
| (1 << (sector
- 16));
876 bank
->sectors
[sector
].is_protected
= set
? 1 : 0;
880 /* update the protection bits */
881 target_write_u32(target
, 0xFFE88008, fmbsea
);
882 target_write_u32(target
, 0xFFE8800C, fmbseb
);
887 /* ---------------------------------------------------------------------- */
889 static int tms470_write(struct flash_bank
*bank
, const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
891 struct target
*target
= bank
->target
;
892 uint32_t glbctrl
, fmbac2
, orig_fmregopt
, fmbsea
, fmbseb
, fmmaxpp
, fmmstat
;
893 int result
= ERROR_OK
;
896 if (target
->state
!= TARGET_HALTED
) {
897 LOG_ERROR("Target not halted");
898 return ERROR_TARGET_NOT_HALTED
;
901 tms470_read_part_info(bank
);
903 LOG_INFO("Writing %" PRId32
" bytes starting at 0x%08" PRIx32
"", count
, bank
->base
+
907 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
908 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
910 (void)tms470_flash_initialize_internal_state_machine(bank
);
912 /* force max wait states */
913 target_read_u32(target
, 0xFFE88004, &fmbac2
);
914 target_write_u32(target
, 0xFFE88004, fmbac2
| 0xff);
916 /* save current access mode, force normal read mode */
917 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
918 target_write_u32(target
, 0xFFE89C00, 0x00);
921 * Disable Level 1 protection for all sectors to be erased/written.
923 target_read_u32(target
, 0xFFE88008, &fmbsea
);
924 target_write_u32(target
, 0xFFE88008, 0xffff);
925 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
926 target_write_u32(target
, 0xFFE8800C, 0xffff);
929 target_read_u32(target
, 0xFFE8A07C, &fmmaxpp
);
931 for (i
= 0; i
< count
; i
+= 2) {
932 uint32_t addr
= bank
->base
+ offset
+ i
;
933 uint16_t word
= (((uint16_t) buffer
[i
]) << 8) | (uint16_t) buffer
[i
+ 1];
935 if (word
!= 0xffff) {
936 LOG_INFO("writing 0x%04x at 0x%08" PRIx32
"", word
, addr
);
938 /* clear status register */
939 target_write_u16(target
, addr
, 0x0040);
940 /* program flash command */
941 target_write_u16(target
, addr
, 0x0010);
942 /* burn the 16-bit word (big-endian) */
943 target_write_u16(target
, addr
, word
);
946 * Monitor FMMSTAT, busy until clear, then check and other flags
947 * for ultimate result of the operation.
950 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
951 if (fmmstat
& 0x0100)
953 } while (fmmstat
& 0x0100);
955 if (fmmstat
& 0x3ff) {
956 LOG_ERROR("fmstat = 0x%04" PRIx32
"", fmmstat
);
958 "Could not program word 0x%04x at address 0x%08" PRIx32
".",
961 result
= ERROR_FLASH_OPERATION_FAILED
;
965 LOG_INFO("skipping 0xffff at 0x%08" PRIx32
"", addr
);
969 target_write_u32(target
, 0xFFE88008, fmbsea
);
970 target_write_u32(target
, 0xFFE8800C, fmbseb
);
971 target_write_u32(target
, 0xFFE88004, fmbac2
);
972 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
973 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
978 /* ---------------------------------------------------------------------- */
980 static int tms470_probe(struct flash_bank
*bank
)
982 if (bank
->target
->state
!= TARGET_HALTED
) {
983 LOG_WARNING("Cannot communicate... target not halted.");
984 return ERROR_TARGET_NOT_HALTED
;
987 return tms470_read_part_info(bank
);
990 static int tms470_auto_probe(struct flash_bank
*bank
)
992 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
994 if (tms470_info
->device_ident_reg
)
996 return tms470_probe(bank
);
999 /* ---------------------------------------------------------------------- */
1001 static int tms470_erase_check(struct flash_bank
*bank
)
1003 struct target
*target
= bank
->target
;
1004 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
1005 int sector
, result
= ERROR_OK
;
1006 uint32_t fmmac2
, fmbac2
, glbctrl
, orig_fmregopt
;
1007 static uint8_t buffer
[64 * 1024];
1009 if (target
->state
!= TARGET_HALTED
) {
1010 LOG_ERROR("Target not halted");
1011 return ERROR_TARGET_NOT_HALTED
;
1014 if (!tms470_info
->device_ident_reg
)
1015 tms470_read_part_info(bank
);
1018 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
1019 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
1021 /* save current access mode, force normal read mode */
1022 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
1023 target_write_u32(target
, 0xFFE89C00, 0x00);
1025 /* enable the appropriate bank */
1026 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
1027 target_write_u32(target
, 0xFFE8BC04, (fmmac2
& ~7) | tms470_info
->ordinal
);
1030 target_write_u32(target
, 0xFFE8BC10, 0x2fc0);
1032 /* clear TEZ in fmbrdy */
1033 target_write_u32(target
, 0xFFE88010, 0x0b);
1035 /* save current wait states, force max */
1036 target_read_u32(target
, 0xFFE88004, &fmbac2
);
1037 target_write_u32(target
, 0xFFE88004, fmbac2
| 0xff);
1040 * The TI primitives inspect the flash memory by reading one 32-bit
1041 * word at a time. Here we read an entire sector and inspect it in
1042 * an attempt to reduce the JTAG overhead.
1044 for (sector
= 0; sector
< bank
->num_sectors
; sector
++) {
1045 uint32_t i
, addr
= bank
->base
+ bank
->sectors
[sector
].offset
;
1047 LOG_INFO("checking flash bank %d sector %d", tms470_info
->ordinal
, sector
);
1049 target_read_buffer(target
, addr
, bank
->sectors
[sector
].size
, buffer
);
1051 bank
->sectors
[sector
].is_erased
= 1;
1052 for (i
= 0; i
< bank
->sectors
[sector
].size
; i
++) {
1053 if (buffer
[i
] != 0xff) {
1054 bank
->sectors
[sector
].is_erased
= 0;
1058 if (bank
->sectors
[sector
].is_erased
!= 1) {
1059 result
= ERROR_FLASH_SECTOR_NOT_ERASED
;
1062 LOG_INFO("sector erased");
1065 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1066 target_write_u32(target
, 0xFFE88010, 0x0f);
1067 target_write_u32(target
, 0xFFE88004, fmbac2
);
1068 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
1069 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
1074 /* ---------------------------------------------------------------------- */
1076 static int tms470_protect_check(struct flash_bank
*bank
)
1078 struct target
*target
= bank
->target
;
1079 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
1080 int sector
, result
= ERROR_OK
;
1081 uint32_t fmmac2
, fmbsea
, fmbseb
;
1083 if (target
->state
!= TARGET_HALTED
) {
1084 LOG_ERROR("Target not halted");
1085 return ERROR_TARGET_NOT_HALTED
;
1088 if (!tms470_info
->device_ident_reg
)
1089 tms470_read_part_info(bank
);
1091 /* enable the appropriate bank */
1092 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
1093 target_write_u32(target
, 0xFFE8BC04, (fmmac2
& ~7) | tms470_info
->ordinal
);
1095 target_read_u32(target
, 0xFFE88008, &fmbsea
);
1096 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
1098 for (sector
= 0; sector
< bank
->num_sectors
; sector
++) {
1102 protected = fmbsea
& (1 << sector
) ? 0 : 1;
1103 bank
->sectors
[sector
].is_protected
= protected;
1105 protected = fmbseb
& (1 << (sector
- 16)) ? 0 : 1;
1106 bank
->sectors
[sector
].is_protected
= protected;
1109 LOG_DEBUG("bank %d sector %d is %s",
1110 tms470_info
->ordinal
,
1112 protected ? "protected" : "not protected");
1118 /* ---------------------------------------------------------------------- */
1120 static int get_tms470_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1123 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
1125 if (!tms470_info
->device_ident_reg
)
1126 tms470_read_part_info(bank
);
1128 if (!tms470_info
->device_ident_reg
) {
1129 (void)snprintf(buf
, buf_size
, "Cannot identify target as a TMS470\n");
1130 return ERROR_FLASH_OPERATION_FAILED
;
1134 snprintf(buf
, buf_size
, "\ntms470 information: Chip is %s\n",
1135 tms470_info
->part_name
);
1139 snprintf(buf
, buf_size
, "Flash protection level 2 is %s\n",
1140 tms470_check_flash_unlocked(bank
->target
) == ERROR_OK
? "disabled" : "enabled");
1145 /* ---------------------------------------------------------------------- */
1148 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1152 FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command
)
1154 bank
->driver_priv
= malloc(sizeof(struct tms470_flash_bank
));
1156 if (!bank
->driver_priv
)
1157 return ERROR_FLASH_OPERATION_FAILED
;
1159 (void)memset(bank
->driver_priv
, 0, sizeof(struct tms470_flash_bank
));
1164 struct flash_driver tms470_flash
= {
1166 .commands
= tms470_command_handlers
,
1167 .flash_bank_command
= tms470_flash_bank_command
,
1168 .erase
= tms470_erase
,
1169 .protect
= tms470_protect
,
1170 .write
= tms470_write
,
1171 .read
= default_flash_read
,
1172 .probe
= tms470_probe
,
1173 .auto_probe
= tms470_auto_probe
,
1174 .erase_check
= tms470_erase_check
,
1175 .protect_check
= tms470_protect_check
,
1176 .info
= get_tms470_info
,
1177 .free_driver_priv
= default_flash_free_driver_priv
,