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openocd: src/flash: replace the GPL-2.0-or-later license tag
[openocd.git] / src / flash / nor / tms470.c
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /***************************************************************************
4 * Copyright (C) 2007,2008 by Christopher Kilgour *
5 * techie |_at_| whiterocker |_dot_| com *
6 ***************************************************************************/
7
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11
12 #include "imp.h"
13
14 /* ----------------------------------------------------------------------
15 * Internal Support, Helpers
16 * ---------------------------------------------------------------------- */
17
18 struct tms470_flash_bank {
19 unsigned ordinal;
20
21 /* device identification register */
22 uint32_t device_ident_reg;
23 uint32_t silicon_version;
24 uint32_t technology_family;
25 uint32_t rom_flash;
26 uint32_t part_number;
27 const char *part_name;
28
29 };
30
31 static const struct flash_sector tms470r1a256_sectors[] = {
32 {0x00000000, 0x00002000, -1, -1},
33 {0x00002000, 0x00002000, -1, -1},
34 {0x00004000, 0x00002000, -1, -1},
35 {0x00006000, 0x00002000, -1, -1},
36 {0x00008000, 0x00008000, -1, -1},
37 {0x00010000, 0x00008000, -1, -1},
38 {0x00018000, 0x00008000, -1, -1},
39 {0x00020000, 0x00008000, -1, -1},
40 {0x00028000, 0x00008000, -1, -1},
41 {0x00030000, 0x00008000, -1, -1},
42 {0x00038000, 0x00002000, -1, -1},
43 {0x0003A000, 0x00002000, -1, -1},
44 {0x0003C000, 0x00002000, -1, -1},
45 {0x0003E000, 0x00002000, -1, -1},
46 };
47
48 #define TMS470R1A256_NUM_SECTORS \
49 ARRAY_SIZE(tms470r1a256_sectors)
50
51 static const struct flash_sector tms470r1a288_bank0_sectors[] = {
52 {0x00000000, 0x00002000, -1, -1},
53 {0x00002000, 0x00002000, -1, -1},
54 {0x00004000, 0x00002000, -1, -1},
55 {0x00006000, 0x00002000, -1, -1},
56 };
57
58 #define TMS470R1A288_BANK0_NUM_SECTORS \
59 ARRAY_SIZE(tms470r1a288_bank0_sectors)
60
61 static const struct flash_sector tms470r1a288_bank1_sectors[] = {
62 {0x00040000, 0x00010000, -1, -1},
63 {0x00050000, 0x00010000, -1, -1},
64 {0x00060000, 0x00010000, -1, -1},
65 {0x00070000, 0x00010000, -1, -1},
66 };
67
68 #define TMS470R1A288_BANK1_NUM_SECTORS \
69 ARRAY_SIZE(tms470r1a288_bank1_sectors)
70
71 static const struct flash_sector tms470r1a384_bank0_sectors[] = {
72 {0x00000000, 0x00002000, -1, -1},
73 {0x00002000, 0x00002000, -1, -1},
74 {0x00004000, 0x00004000, -1, -1},
75 {0x00008000, 0x00004000, -1, -1},
76 {0x0000C000, 0x00004000, -1, -1},
77 {0x00010000, 0x00004000, -1, -1},
78 {0x00014000, 0x00004000, -1, -1},
79 {0x00018000, 0x00002000, -1, -1},
80 {0x0001C000, 0x00002000, -1, -1},
81 {0x0001E000, 0x00002000, -1, -1},
82 };
83
84 #define TMS470R1A384_BANK0_NUM_SECTORS \
85 ARRAY_SIZE(tms470r1a384_bank0_sectors)
86
87 static const struct flash_sector tms470r1a384_bank1_sectors[] = {
88 {0x00020000, 0x00008000, -1, -1},
89 {0x00028000, 0x00008000, -1, -1},
90 {0x00030000, 0x00008000, -1, -1},
91 {0x00038000, 0x00008000, -1, -1},
92 };
93
94 #define TMS470R1A384_BANK1_NUM_SECTORS \
95 ARRAY_SIZE(tms470r1a384_bank1_sectors)
96
97 static const struct flash_sector tms470r1a384_bank2_sectors[] = {
98 {0x00040000, 0x00008000, -1, -1},
99 {0x00048000, 0x00008000, -1, -1},
100 {0x00050000, 0x00008000, -1, -1},
101 {0x00058000, 0x00008000, -1, -1},
102 };
103
104 #define TMS470R1A384_BANK2_NUM_SECTORS \
105 ARRAY_SIZE(tms470r1a384_bank2_sectors)
106
107 /* ---------------------------------------------------------------------- */
108
109 static int tms470_read_part_info(struct flash_bank *bank)
110 {
111 struct tms470_flash_bank *tms470_info = bank->driver_priv;
112 struct target *target = bank->target;
113 uint32_t device_ident_reg;
114 uint32_t silicon_version;
115 uint32_t technology_family;
116 uint32_t rom_flash;
117 uint32_t part_number;
118 const char *part_name;
119
120 /* we shall not rely on the caller in this test, this function allocates memory,
121 thus and executing the code more than once may cause memory leak */
122 if (tms470_info->device_ident_reg)
123 return ERROR_OK;
124
125 /* read and parse the device identification register */
126 target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
127
128 LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
129
130 if ((device_ident_reg & 7) == 0) {
131 LOG_WARNING("Cannot identify target as a TMS470 family.");
132 return ERROR_FLASH_OPERATION_FAILED;
133 }
134
135 silicon_version = (device_ident_reg >> 12) & 0xF;
136 technology_family = (device_ident_reg >> 11) & 1;
137 rom_flash = (device_ident_reg >> 10) & 1;
138 part_number = (device_ident_reg >> 3) & 0x7f;
139
140 free(bank->sectors);
141 bank->sectors = NULL;
142 bank->num_sectors = 0;
143
144 /*
145 * If the part number is known, determine if the flash bank is valid
146 * based on the base address being within the known flash bank
147 * ranges. Then fixup/complete the remaining fields of the flash
148 * bank structure.
149 */
150 switch (part_number) {
151 case 0x0a:
152 part_name = "TMS470R1A256";
153
154 if (bank->base >= 0x00040000) {
155 LOG_ERROR("No %s flash bank contains base address "
156 TARGET_ADDR_FMT ".",
157 part_name,
158 bank->base);
159 return ERROR_FLASH_OPERATION_FAILED;
160 }
161 tms470_info->ordinal = 0;
162 bank->base = 0x00000000;
163 bank->size = 256 * 1024;
164 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
165 bank->sectors = malloc(sizeof(tms470r1a256_sectors));
166 if (!bank->sectors)
167 return ERROR_FLASH_OPERATION_FAILED;
168 (void)memcpy(bank->sectors, tms470r1a256_sectors, sizeof(tms470r1a256_sectors));
169 break;
170
171 case 0x2b:
172 part_name = "TMS470R1A288";
173
174 if (bank->base < 0x00008000) {
175 tms470_info->ordinal = 0;
176 bank->base = 0x00000000;
177 bank->size = 32 * 1024;
178 bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
179 bank->sectors = malloc(sizeof(tms470r1a288_bank0_sectors));
180 if (!bank->sectors)
181 return ERROR_FLASH_OPERATION_FAILED;
182 (void)memcpy(bank->sectors, tms470r1a288_bank0_sectors,
183 sizeof(tms470r1a288_bank0_sectors));
184 } else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) {
185 tms470_info->ordinal = 1;
186 bank->base = 0x00040000;
187 bank->size = 256 * 1024;
188 bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
189 bank->sectors = malloc(sizeof(tms470r1a288_bank1_sectors));
190 if (!bank->sectors)
191 return ERROR_FLASH_OPERATION_FAILED;
192 (void)memcpy(bank->sectors, tms470r1a288_bank1_sectors,
193 sizeof(tms470r1a288_bank1_sectors));
194 } else {
195 LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
196 part_name, bank->base);
197 return ERROR_FLASH_OPERATION_FAILED;
198 }
199 break;
200
201 case 0x2d:
202 part_name = "TMS470R1A384";
203
204 if (bank->base < 0x00020000) {
205 tms470_info->ordinal = 0;
206 bank->base = 0x00000000;
207 bank->size = 128 * 1024;
208 bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS;
209 bank->sectors = malloc(sizeof(tms470r1a384_bank0_sectors));
210 if (!bank->sectors)
211 return ERROR_FLASH_OPERATION_FAILED;
212 (void)memcpy(bank->sectors, tms470r1a384_bank0_sectors,
213 sizeof(tms470r1a384_bank0_sectors));
214 } else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) {
215 tms470_info->ordinal = 1;
216 bank->base = 0x00020000;
217 bank->size = 128 * 1024;
218 bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS;
219 bank->sectors = malloc(sizeof(tms470r1a384_bank1_sectors));
220 if (!bank->sectors)
221 return ERROR_FLASH_OPERATION_FAILED;
222 (void)memcpy(bank->sectors, tms470r1a384_bank1_sectors,
223 sizeof(tms470r1a384_bank1_sectors));
224 } else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) {
225 tms470_info->ordinal = 2;
226 bank->base = 0x00040000;
227 bank->size = 128 * 1024;
228 bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS;
229 bank->sectors = malloc(sizeof(tms470r1a384_bank2_sectors));
230 if (!bank->sectors)
231 return ERROR_FLASH_OPERATION_FAILED;
232 (void)memcpy(bank->sectors, tms470r1a384_bank2_sectors,
233 sizeof(tms470r1a384_bank2_sectors));
234 } else {
235 LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
236 part_name, bank->base);
237 return ERROR_FLASH_OPERATION_FAILED;
238 }
239 break;
240
241 default:
242 LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.",
243 (unsigned)part_number);
244 return ERROR_FLASH_OPERATION_FAILED;
245 }
246
247 /* turn off memory selects */
248 target_write_u32(target, 0xFFFFFFE4, 0x00000000);
249 target_write_u32(target, 0xFFFFFFE0, 0x00000000);
250
251 bank->chip_width = 32;
252 bank->bus_width = 32;
253
254 LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
255 part_name,
256 (int)(silicon_version),
257 (technology_family ? "1.8v" : "3.3v"),
258 (rom_flash ? "rom" : "flash"));
259
260 tms470_info->device_ident_reg = device_ident_reg;
261 tms470_info->silicon_version = silicon_version;
262 tms470_info->technology_family = technology_family;
263 tms470_info->rom_flash = rom_flash;
264 tms470_info->part_number = part_number;
265 tms470_info->part_name = part_name;
266
267 /*
268 * Disable reset on address access violation.
269 */
270 target_write_u32(target, 0xFFFFFFE0, 0x00004007);
271
272 return ERROR_OK;
273 }
274
275 /* ---------------------------------------------------------------------- */
276
277 static uint32_t keys_set;
278 static uint32_t flash_keys[4];
279
280 COMMAND_HANDLER(tms470_handle_flash_keyset_command)
281 {
282 if (CMD_ARGC > 4)
283 return ERROR_COMMAND_SYNTAX_ERROR;
284 else if (CMD_ARGC == 4) {
285 int i;
286
287 for (i = 0; i < 4; i++) {
288 int start = (strncmp(CMD_ARGV[i], "0x", 2) == 0) ? 2 : 0;
289
290 if (sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i]) != 1) {
291 command_print(CMD, "could not process flash key %s",
292 CMD_ARGV[i]);
293 LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
294 return ERROR_COMMAND_SYNTAX_ERROR;
295 }
296 }
297
298 keys_set = 1;
299 } else if (CMD_ARGC != 0) {
300 command_print(CMD, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
301 return ERROR_COMMAND_SYNTAX_ERROR;
302 }
303
304 if (keys_set) {
305 command_print(CMD,
306 "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
307 flash_keys[0],
308 flash_keys[1],
309 flash_keys[2],
310 flash_keys[3]);
311 } else
312 command_print(CMD, "flash keys not set");
313
314 return ERROR_OK;
315 }
316
317 static const uint32_t flash_keys_all_ones[] = { 0xFFFFFFFF, 0xFFFFFFFF,
318 0xFFFFFFFF, 0xFFFFFFFF,};
319
320 static const uint32_t flash_keys_all_zeros[] = { 0x00000000, 0x00000000,
321 0x00000000, 0x00000000,};
322
323 static const uint32_t flash_keys_mix1[] = { 0xf0fff0ff, 0xf0fff0ff,
324 0xf0fff0ff, 0xf0fff0ff};
325
326 static const uint32_t flash_keys_mix2[] = { 0x0000ffff, 0x0000ffff,
327 0x0000ffff, 0x0000ffff};
328
329 /* ---------------------------------------------------------------------- */
330
331 static int osc_mhz = 12;
332
333 COMMAND_HANDLER(tms470_handle_osc_megahertz_command)
334 {
335 if (CMD_ARGC > 1)
336 return ERROR_COMMAND_SYNTAX_ERROR;
337 else if (CMD_ARGC == 1)
338 sscanf(CMD_ARGV[0], "%d", &osc_mhz);
339
340 if (osc_mhz <= 0) {
341 LOG_ERROR("osc_megahertz must be positive and non-zero!");
342 command_print(CMD, "osc_megahertz must be positive and non-zero!");
343 osc_mhz = 12;
344 return ERROR_COMMAND_SYNTAX_ERROR;
345 }
346
347 command_print(CMD, "osc_megahertz=%d", osc_mhz);
348
349 return ERROR_OK;
350 }
351
352 /* ---------------------------------------------------------------------- */
353
354 static int plldis;
355
356 COMMAND_HANDLER(tms470_handle_plldis_command)
357 {
358 if (CMD_ARGC > 1)
359 return ERROR_COMMAND_SYNTAX_ERROR;
360 else if (CMD_ARGC == 1) {
361 sscanf(CMD_ARGV[0], "%d", &plldis);
362 plldis = plldis ? 1 : 0;
363 }
364
365 command_print(CMD, "plldis=%d", plldis);
366
367 return ERROR_OK;
368 }
369
370 /* ---------------------------------------------------------------------- */
371
372 static int tms470_check_flash_unlocked(struct target *target)
373 {
374 uint32_t fmbbusy;
375
376 target_read_u32(target, 0xFFE89C08, &fmbbusy);
377 LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32 " -> %s",
378 fmbbusy,
379 fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
380 return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
381 }
382
383 /* ---------------------------------------------------------------------- */
384
385 static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set)
386 {
387 uint32_t glbctrl, fmmstat;
388 int retval = ERROR_FLASH_OPERATION_FAILED;
389
390 /* set GLBCTRL.4 */
391 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
392 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
393
394 /* only perform the key match when 3VSTAT is clear */
395 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
396 if (!(fmmstat & 0x08)) {
397 unsigned i;
398 uint32_t fmbptr, fmbac2, orig_fmregopt;
399
400 target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
401
402 /* wait for pump ready */
403 do {
404 target_read_u32(target, 0xFFE8A814, &fmbptr);
405 alive_sleep(1);
406 } while (!(fmbptr & 0x0200));
407
408 /* force max wait states */
409 target_read_u32(target, 0xFFE88004, &fmbac2);
410 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
411
412 /* save current access mode, force normal read mode */
413 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
414 target_write_u32(target, 0xFFE89C00, 0x00);
415
416 for (i = 0; i < 4; i++) {
417 uint32_t tmp;
418
419 /* There is no point displaying the value of tmp, it is
420 * filtered by the chip. The purpose of this read is to
421 * prime the unlocking logic rather than read out the value.
422 */
423 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
424
425 LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
426 target_write_u32(target, 0xFFE89C0C, key_set[i]);
427 }
428
429 if (tms470_check_flash_unlocked(target) == ERROR_OK) {
430 /*
431 * There seems to be a side-effect of reading the FMPKEY
432 * register in that it re-enables the protection. So we
433 * re-enable it.
434 */
435 for (i = 0; i < 4; i++) {
436 uint32_t tmp;
437
438 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
439 target_write_u32(target, 0xFFE89C0C, key_set[i]);
440 }
441 retval = ERROR_OK;
442 }
443
444 /* restore settings */
445 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
446 target_write_u32(target, 0xFFE88004, fmbac2);
447 }
448
449 /* clear config bit */
450 target_write_u32(target, 0xFFFFFFDC, glbctrl);
451
452 return retval;
453 }
454
455 /* ---------------------------------------------------------------------- */
456
457 static int tms470_unlock_flash(struct flash_bank *bank)
458 {
459 struct target *target = bank->target;
460 const uint32_t *p_key_sets[5];
461 unsigned i, key_set_count;
462
463 if (keys_set) {
464 key_set_count = 5;
465 p_key_sets[0] = flash_keys;
466 p_key_sets[1] = flash_keys_all_ones;
467 p_key_sets[2] = flash_keys_all_zeros;
468 p_key_sets[3] = flash_keys_mix1;
469 p_key_sets[4] = flash_keys_mix2;
470 } else {
471 key_set_count = 4;
472 p_key_sets[0] = flash_keys_all_ones;
473 p_key_sets[1] = flash_keys_all_zeros;
474 p_key_sets[2] = flash_keys_mix1;
475 p_key_sets[3] = flash_keys_mix2;
476 }
477
478 for (i = 0; i < key_set_count; i++) {
479 if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK) {
480 LOG_INFO("tms470 flash is unlocked");
481 return ERROR_OK;
482 }
483 }
484
485 LOG_WARNING("tms470 could not unlock flash memory protection level 2");
486 return ERROR_FLASH_OPERATION_FAILED;
487 }
488
489 /* ---------------------------------------------------------------------- */
490
491 static int tms470_flash_initialize_internal_state_machine(struct flash_bank *bank)
492 {
493 uint32_t fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
494 struct target *target = bank->target;
495 struct tms470_flash_bank *tms470_info = bank->driver_priv;
496 int result = ERROR_OK;
497
498 /*
499 * Select the desired bank to be programmed by writing BANK[2:0] of
500 * FMMAC2.
501 */
502 target_read_u32(target, 0xFFE8BC04, &fmmac2);
503 fmmac2 &= ~0x0007;
504 fmmac2 |= (tms470_info->ordinal & 7);
505 target_write_u32(target, 0xFFE8BC04, fmmac2);
506 LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
507
508 /*
509 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
510 */
511 target_read_u32(target, 0xFFE8BC00, &fmmac1);
512 fmmac1 |= 0x8000;
513 target_write_u32(target, 0xFFE8BC00, fmmac1);
514 LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
515
516 /*
517 * FMTCREG = 0x2fc0;
518 */
519 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
520 LOG_DEBUG("set fmtcreg = 0x2fc0");
521
522 /*
523 * MAXPP = 50
524 */
525 target_write_u32(target, 0xFFE8A07C, 50);
526 LOG_DEBUG("set fmmaxpp = 50");
527
528 /*
529 * MAXCP = 0xf000 + 2000
530 */
531 target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
532 LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
533
534 /*
535 * configure VHV
536 */
537 target_read_u32(target, 0xFFE8A080, &fmmaxep);
538 if (fmmaxep == 0xf000) {
539 fmmaxep = 0xf000 + 4095;
540 target_write_u32(target, 0xFFE8A80C, 0x9964);
541 LOG_DEBUG("set fmptr3 = 0x9964");
542 } else {
543 fmmaxep = 0xa000 + 4095;
544 target_write_u32(target, 0xFFE8A80C, 0x9b64);
545 LOG_DEBUG("set fmptr3 = 0x9b64");
546 }
547 target_write_u32(target, 0xFFE8A080, fmmaxep);
548 LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
549
550 /*
551 * FMPTR4 = 0xa000
552 */
553 target_write_u32(target, 0xFFE8A810, 0xa000);
554 LOG_DEBUG("set fmptr4 = 0xa000");
555
556 /*
557 * FMPESETUP, delay parameter selected based on clock frequency.
558 *
559 * According to the TI App Note SPNU257 and flashing code, delay is
560 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
561 * clock is usually derived from the ZPLL module, and selected by
562 * the plldis global.
563 */
564 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
565 sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * osc_mhz / (1 + (glbctrl & 7));
566 delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
567 target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
568 LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
569
570 /*
571 * FMPVEVACCESS, based on delay.
572 */
573 k = delay | (delay << 8);
574 target_write_u32(target, 0xFFE8A05C, k);
575 LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
576
577 /*
578 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
579 */
580 k <<= 1;
581 target_write_u32(target, 0xFFE8A034, k);
582 LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
583 target_write_u32(target, 0xFFE8A040, k);
584 LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
585 target_write_u32(target, 0xFFE8A024, k);
586 LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
587
588 /*
589 * FMCVACCESS, based on delay.
590 */
591 k = delay * 16;
592 target_write_u32(target, 0xFFE8A060, k);
593 LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
594
595 /*
596 * FMCSETUP, based on delay.
597 */
598 k = 0x3000 | delay * 20;
599 target_write_u32(target, 0xFFE8A020, k);
600 LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
601
602 /*
603 * FMEHOLD, based on delay.
604 */
605 k = (delay * 20) << 2;
606 target_write_u32(target, 0xFFE8A038, k);
607 LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
608
609 /*
610 * PWIDTH, CWIDTH, EWIDTH, based on delay.
611 */
612 target_write_u32(target, 0xFFE8A050, delay * 8);
613 LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
614 target_write_u32(target, 0xFFE8A058, delay * 1000);
615 LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
616 target_write_u32(target, 0xFFE8A054, delay * 5400);
617 LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
618
619 return result;
620 }
621
622 /* ---------------------------------------------------------------------- */
623
624 static int tms470_flash_status(struct flash_bank *bank)
625 {
626 struct target *target = bank->target;
627 int result = ERROR_OK;
628 uint32_t fmmstat;
629
630 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
631 LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
632
633 if (fmmstat & 0x0080) {
634 LOG_WARNING("tms470 flash command: erase still active after busy clear.");
635 result = ERROR_FLASH_OPERATION_FAILED;
636 }
637
638 if (fmmstat & 0x0040) {
639 LOG_WARNING("tms470 flash command: program still active after busy clear.");
640 result = ERROR_FLASH_OPERATION_FAILED;
641 }
642
643 if (fmmstat & 0x0020) {
644 LOG_WARNING("tms470 flash command: invalid data command.");
645 result = ERROR_FLASH_OPERATION_FAILED;
646 }
647
648 if (fmmstat & 0x0010) {
649 LOG_WARNING("tms470 flash command: program, erase or validate sector failed.");
650 result = ERROR_FLASH_OPERATION_FAILED;
651 }
652
653 if (fmmstat & 0x0008) {
654 LOG_WARNING("tms470 flash command: voltage instability detected.");
655 result = ERROR_FLASH_OPERATION_FAILED;
656 }
657
658 if (fmmstat & 0x0006) {
659 LOG_WARNING("tms470 flash command: command suspend detected.");
660 result = ERROR_FLASH_OPERATION_FAILED;
661 }
662
663 if (fmmstat & 0x0001) {
664 LOG_WARNING("tms470 flash command: sector was locked.");
665 result = ERROR_FLASH_OPERATION_FAILED;
666 }
667
668 return result;
669 }
670
671 /* ---------------------------------------------------------------------- */
672
673 static int tms470_erase_sector(struct flash_bank *bank, int sector)
674 {
675 uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
676 struct target *target = bank->target;
677 uint32_t flash_addr = bank->base + bank->sectors[sector].offset;
678 int result = ERROR_OK;
679
680 /*
681 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
682 * module) to enable writing to the flash registers }.
683 */
684 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
685 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
686 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
687
688 /* Force normal read mode. */
689 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
690 target_write_u32(target, 0xFFE89C00, 0);
691 LOG_DEBUG("set fmregopt = 0x%08x", 0);
692
693 (void)tms470_flash_initialize_internal_state_machine(bank);
694
695 /*
696 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
697 * protection for the particular sector to be erased/written.
698 */
699 assert(sector >= 0);
700 if (sector < 16) {
701 target_read_u32(target, 0xFFE88008, &fmbsea);
702 target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
703 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
704 } else {
705 target_read_u32(target, 0xFFE8800C, &fmbseb);
706 target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
707 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
708 }
709 bank->sectors[sector].is_protected = 0;
710
711 /*
712 * clear status register, sent erase command, kickoff erase
713 */
714 target_write_u16(target, flash_addr, 0x0040);
715 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flash_addr);
716 target_write_u16(target, flash_addr, 0x0020);
717 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flash_addr);
718 target_write_u16(target, flash_addr, 0xffff);
719 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flash_addr);
720
721 /*
722 * Monitor FMMSTAT, busy until clear, then check and other flags for
723 * ultimate result of the operation.
724 */
725 do {
726 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
727 if (fmmstat & 0x0100)
728 alive_sleep(1);
729 } while (fmmstat & 0x0100);
730
731 result = tms470_flash_status(bank);
732
733 if (sector < 16) {
734 target_write_u32(target, 0xFFE88008, fmbsea);
735 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
736 bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
737 } else {
738 target_write_u32(target, 0xFFE8800C, fmbseb);
739 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
740 bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
741 }
742 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
743 LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
744 target_write_u32(target, 0xFFFFFFDC, glbctrl);
745 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
746
747 return result;
748 }
749
750 /*----------------------------------------------------------------------
751 * Implementation of Flash Driver Interfaces
752 *---------------------------------------------------------------------- */
753
754 static const struct command_registration tms470_any_command_handlers[] = {
755 {
756 .name = "flash_keyset",
757 .usage = "<key0> <key1> <key2> <key3>",
758 .handler = tms470_handle_flash_keyset_command,
759 .mode = COMMAND_ANY,
760 .help = "tms470 flash_keyset <key0> <key1> <key2> <key3>",
761 },
762 {
763 .name = "osc_megahertz",
764 .usage = "<MHz>",
765 .handler = tms470_handle_osc_megahertz_command,
766 .mode = COMMAND_ANY,
767 .help = "tms470 osc_megahertz <MHz>",
768 },
769 {
770 .name = "plldis",
771 .usage = "<0 | 1>",
772 .handler = tms470_handle_plldis_command,
773 .mode = COMMAND_ANY,
774 .help = "tms470 plldis <0/1>",
775 },
776 COMMAND_REGISTRATION_DONE
777 };
778 static const struct command_registration tms470_command_handlers[] = {
779 {
780 .name = "tms470",
781 .mode = COMMAND_ANY,
782 .help = "TI tms470 flash command group",
783 .usage = "",
784 .chain = tms470_any_command_handlers,
785 },
786 COMMAND_REGISTRATION_DONE
787 };
788
789 /* ---------------------------------------------------------------------- */
790
791 static int tms470_erase(struct flash_bank *bank, unsigned int first,
792 unsigned int last)
793 {
794 struct tms470_flash_bank *tms470_info = bank->driver_priv;
795 int result = ERROR_OK;
796
797 if (bank->target->state != TARGET_HALTED) {
798 LOG_ERROR("Target not halted");
799 return ERROR_TARGET_NOT_HALTED;
800 }
801
802 tms470_read_part_info(bank);
803
804 if ((first >= bank->num_sectors) || (last >= bank->num_sectors) ||
805 (first > last)) {
806 LOG_ERROR("Sector range %u to %u invalid.", first, last);
807 return ERROR_FLASH_SECTOR_INVALID;
808 }
809
810 result = tms470_unlock_flash(bank);
811 if (result != ERROR_OK)
812 return result;
813
814 for (unsigned int sector = first; sector <= last; sector++) {
815 LOG_INFO("Erasing tms470 bank %u sector %u...", tms470_info->ordinal, sector);
816
817 result = tms470_erase_sector(bank, sector);
818
819 if (result != ERROR_OK) {
820 LOG_ERROR("tms470 could not erase flash sector.");
821 break;
822 } else
823 LOG_INFO("sector erased successfully.");
824 }
825
826 return result;
827 }
828
829 /* ---------------------------------------------------------------------- */
830
831 static int tms470_protect(struct flash_bank *bank, int set, unsigned int first,
832 unsigned int last)
833 {
834 struct tms470_flash_bank *tms470_info = bank->driver_priv;
835 struct target *target = bank->target;
836 uint32_t fmmac2, fmbsea, fmbseb;
837
838 if (target->state != TARGET_HALTED) {
839 LOG_ERROR("Target not halted");
840 return ERROR_TARGET_NOT_HALTED;
841 }
842
843 tms470_read_part_info(bank);
844
845 if ((first >= bank->num_sectors) || (last >= bank->num_sectors) ||
846 (first > last)) {
847 LOG_ERROR("Sector range %u to %u invalid.", first, last);
848 return ERROR_FLASH_SECTOR_INVALID;
849 }
850
851 /* enable the appropriate bank */
852 target_read_u32(target, 0xFFE8BC04, &fmmac2);
853 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
854
855 /* get the original sector protection flags for this bank */
856 target_read_u32(target, 0xFFE88008, &fmbsea);
857 target_read_u32(target, 0xFFE8800C, &fmbseb);
858
859 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
860 if (sector < 16) {
861 fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
862 bank->sectors[sector].is_protected = set ? 1 : 0;
863 } else {
864 fmbseb = set ? fmbseb &
865 ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
866 bank->sectors[sector].is_protected = set ? 1 : 0;
867 }
868 }
869
870 /* update the protection bits */
871 target_write_u32(target, 0xFFE88008, fmbsea);
872 target_write_u32(target, 0xFFE8800C, fmbseb);
873
874 return ERROR_OK;
875 }
876
877 /* ---------------------------------------------------------------------- */
878
879 static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
880 {
881 struct target *target = bank->target;
882 uint32_t glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
883 int result = ERROR_OK;
884 uint32_t i;
885
886 if (target->state != TARGET_HALTED) {
887 LOG_ERROR("Target not halted");
888 return ERROR_TARGET_NOT_HALTED;
889 }
890
891 tms470_read_part_info(bank);
892
893 LOG_INFO("Writing %" PRIu32 " bytes starting at " TARGET_ADDR_FMT,
894 count, bank->base + offset);
895
896 /* set GLBCTRL.4 */
897 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
898 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
899
900 (void)tms470_flash_initialize_internal_state_machine(bank);
901
902 /* force max wait states */
903 target_read_u32(target, 0xFFE88004, &fmbac2);
904 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
905
906 /* save current access mode, force normal read mode */
907 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
908 target_write_u32(target, 0xFFE89C00, 0x00);
909
910 /*
911 * Disable Level 1 protection for all sectors to be erased/written.
912 */
913 target_read_u32(target, 0xFFE88008, &fmbsea);
914 target_write_u32(target, 0xFFE88008, 0xffff);
915 target_read_u32(target, 0xFFE8800C, &fmbseb);
916 target_write_u32(target, 0xFFE8800C, 0xffff);
917
918 /* read MAXPP */
919 target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
920
921 for (i = 0; i < count; i += 2) {
922 uint32_t addr = bank->base + offset + i;
923 uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
924
925 if (word != 0xffff) {
926 LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
927
928 /* clear status register */
929 target_write_u16(target, addr, 0x0040);
930 /* program flash command */
931 target_write_u16(target, addr, 0x0010);
932 /* burn the 16-bit word (big-endian) */
933 target_write_u16(target, addr, word);
934
935 /*
936 * Monitor FMMSTAT, busy until clear, then check and other flags
937 * for ultimate result of the operation.
938 */
939 do {
940 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
941 if (fmmstat & 0x0100)
942 alive_sleep(1);
943 } while (fmmstat & 0x0100);
944
945 if (fmmstat & 0x3ff) {
946 LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
947 LOG_ERROR(
948 "Could not program word 0x%04x at address 0x%08" PRIx32 ".",
949 word,
950 addr);
951 result = ERROR_FLASH_OPERATION_FAILED;
952 break;
953 }
954 } else
955 LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
956 }
957
958 /* restore */
959 target_write_u32(target, 0xFFE88008, fmbsea);
960 target_write_u32(target, 0xFFE8800C, fmbseb);
961 target_write_u32(target, 0xFFE88004, fmbac2);
962 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
963 target_write_u32(target, 0xFFFFFFDC, glbctrl);
964
965 return result;
966 }
967
968 /* ---------------------------------------------------------------------- */
969
970 static int tms470_probe(struct flash_bank *bank)
971 {
972 if (bank->target->state != TARGET_HALTED) {
973 LOG_WARNING("Cannot communicate... target not halted.");
974 return ERROR_TARGET_NOT_HALTED;
975 }
976
977 return tms470_read_part_info(bank);
978 }
979
980 static int tms470_auto_probe(struct flash_bank *bank)
981 {
982 struct tms470_flash_bank *tms470_info = bank->driver_priv;
983
984 if (tms470_info->device_ident_reg)
985 return ERROR_OK;
986 return tms470_probe(bank);
987 }
988
989 /* ---------------------------------------------------------------------- */
990
991 static int tms470_erase_check(struct flash_bank *bank)
992 {
993 struct target *target = bank->target;
994 struct tms470_flash_bank *tms470_info = bank->driver_priv;
995 int result = ERROR_OK;
996 uint32_t fmmac2, fmbac2, glbctrl, orig_fmregopt;
997 static uint8_t buffer[64 * 1024];
998
999 if (target->state != TARGET_HALTED) {
1000 LOG_ERROR("Target not halted");
1001 return ERROR_TARGET_NOT_HALTED;
1002 }
1003
1004 if (!tms470_info->device_ident_reg)
1005 tms470_read_part_info(bank);
1006
1007 /* set GLBCTRL.4 */
1008 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
1009 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
1010
1011 /* save current access mode, force normal read mode */
1012 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
1013 target_write_u32(target, 0xFFE89C00, 0x00);
1014
1015 /* enable the appropriate bank */
1016 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1017 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1018
1019 /* TCR = 0 */
1020 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
1021
1022 /* clear TEZ in fmbrdy */
1023 target_write_u32(target, 0xFFE88010, 0x0b);
1024
1025 /* save current wait states, force max */
1026 target_read_u32(target, 0xFFE88004, &fmbac2);
1027 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
1028
1029 /*
1030 * The TI primitives inspect the flash memory by reading one 32-bit
1031 * word at a time. Here we read an entire sector and inspect it in
1032 * an attempt to reduce the JTAG overhead.
1033 */
1034 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1035 uint32_t i, addr = bank->base + bank->sectors[sector].offset;
1036
1037 LOG_INFO("checking flash bank %u sector %u", tms470_info->ordinal, sector);
1038
1039 target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
1040
1041 bank->sectors[sector].is_erased = 1;
1042 for (i = 0; i < bank->sectors[sector].size; i++) {
1043 if (buffer[i] != 0xff) {
1044 bank->sectors[sector].is_erased = 0;
1045 break;
1046 }
1047 }
1048 if (bank->sectors[sector].is_erased != 1) {
1049 result = ERROR_FLASH_SECTOR_NOT_ERASED;
1050 break;
1051 } else
1052 LOG_INFO("sector erased");
1053 }
1054
1055 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1056 target_write_u32(target, 0xFFE88010, 0x0f);
1057 target_write_u32(target, 0xFFE88004, fmbac2);
1058 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1059 target_write_u32(target, 0xFFFFFFDC, glbctrl);
1060
1061 return result;
1062 }
1063
1064 /* ---------------------------------------------------------------------- */
1065
1066 static int tms470_protect_check(struct flash_bank *bank)
1067 {
1068 struct target *target = bank->target;
1069 struct tms470_flash_bank *tms470_info = bank->driver_priv;
1070 int result = ERROR_OK;
1071 uint32_t fmmac2, fmbsea, fmbseb;
1072
1073 if (target->state != TARGET_HALTED) {
1074 LOG_ERROR("Target not halted");
1075 return ERROR_TARGET_NOT_HALTED;
1076 }
1077
1078 if (!tms470_info->device_ident_reg)
1079 tms470_read_part_info(bank);
1080
1081 /* enable the appropriate bank */
1082 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1083 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1084
1085 target_read_u32(target, 0xFFE88008, &fmbsea);
1086 target_read_u32(target, 0xFFE8800C, &fmbseb);
1087
1088 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1089 int protected;
1090
1091 if (sector < 16) {
1092 protected = fmbsea & (1 << sector) ? 0 : 1;
1093 bank->sectors[sector].is_protected = protected;
1094 } else {
1095 protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
1096 bank->sectors[sector].is_protected = protected;
1097 }
1098
1099 LOG_DEBUG("bank %u sector %u is %s",
1100 tms470_info->ordinal,
1101 sector,
1102 protected ? "protected" : "not protected");
1103 }
1104
1105 return result;
1106 }
1107
1108 /* ---------------------------------------------------------------------- */
1109
1110 static int get_tms470_info(struct flash_bank *bank, struct command_invocation *cmd)
1111 {
1112 struct tms470_flash_bank *tms470_info = bank->driver_priv;
1113
1114 if (!tms470_info->device_ident_reg)
1115 tms470_read_part_info(bank);
1116
1117 if (!tms470_info->device_ident_reg) {
1118 command_print_sameline(cmd, "Cannot identify target as a TMS470\n");
1119 return ERROR_FLASH_OPERATION_FAILED;
1120 }
1121
1122 command_print_sameline(cmd, "\ntms470 information: Chip is %s\n", tms470_info->part_name);
1123 command_print_sameline(cmd, "Flash protection level 2 is %s\n",
1124 tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
1125
1126 return ERROR_OK;
1127 }
1128
1129 /* ---------------------------------------------------------------------- */
1130
1131 /*
1132 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1133 * [options...]
1134 */
1135
1136 FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
1137 {
1138 bank->driver_priv = malloc(sizeof(struct tms470_flash_bank));
1139
1140 if (!bank->driver_priv)
1141 return ERROR_FLASH_OPERATION_FAILED;
1142
1143 (void)memset(bank->driver_priv, 0, sizeof(struct tms470_flash_bank));
1144
1145 return ERROR_OK;
1146 }
1147
1148 const struct flash_driver tms470_flash = {
1149 .name = "tms470",
1150 .commands = tms470_command_handlers,
1151 .flash_bank_command = tms470_flash_bank_command,
1152 .erase = tms470_erase,
1153 .protect = tms470_protect,
1154 .write = tms470_write,
1155 .read = default_flash_read,
1156 .probe = tms470_probe,
1157 .auto_probe = tms470_auto_probe,
1158 .erase_check = tms470_erase_check,
1159 .protect_check = tms470_protect_check,
1160 .info = get_tms470_info,
1161 .free_driver_priv = default_flash_free_driver_priv,
1162 };
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