1 /**************************************************************************
2 * Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
23 #include <helper/binarybuffer.h>
24 #include <target/algorithm.h>
25 #include <target/armv7m.h>
27 /* Maximum number of sectors */
28 #define MAX_XMC_SECTORS 12
30 /* System control unit registers */
31 #define SCU_REG_BASE 0x50004000
33 #define SCU_ID_CHIP 0x04
35 /* Base of the non-cached flash memory */
36 #define PFLASH_BASE 0x0C000000
38 /* User configuration block offsets */
39 #define UCB0_BASE 0x00000000
40 #define UCB1_BASE 0x00000400
41 #define UCB2_BASE 0x00000800
43 /* Flash register base */
44 #define FLASH_REG_BASE 0x58000000
46 /* PMU ID Registers */
47 #define FLASH_REG_PMU_ID (FLASH_REG_BASE | 0x0508)
50 #define PMU_MOD_REV_MASK 0xFF
51 #define PMU_MOD_TYPE_MASK 0xFF00
52 #define PMU_MOD_NO_MASK 0xFFFF0000
55 #define FLASH_REG_PREF_PCON (FLASH_REG_BASE | 0x4000)
58 #define PCON_IBYP (1 << 0)
59 #define PCON_IINV (1 << 1)
61 /* Flash ID Register */
62 #define FLASH_REG_FLASH0_ID (FLASH_REG_BASE | 0x2008)
64 /* Flash Status Register */
65 #define FLASH_REG_FLASH0_FSR (FLASH_REG_BASE | 0x2010)
68 #define FSR_FABUSY (1)
71 #define FSR_PFPAGE (6)
72 #define FSR_PFOPER (8)
74 #define FSR_PROER (11)
75 #define FSR_PFSBER (12)
76 #define FSR_PFDBER (14)
77 #define FSR_PROIN (16)
78 #define FSR_RPROIN (18)
79 #define FSR_RPRODIS (19)
80 #define FSR_WPROIN0 (21)
81 #define FSR_WPROIN1 (22)
82 #define FSR_WPROIN2 (23)
83 #define FSR_WPRODIS0 (25)
84 #define FSR_WPRODIS1 (26)
88 #define FSR_PBUSY_MASK (0x01 << FSR_PBUSY)
89 #define FSR_FABUSY_MASK (0x01 << FSR_FABUSY)
90 #define FSR_PROG_MASK (0x01 << FSR_PROG)
91 #define FSR_ERASE_MASK (0x01 << FSR_ERASE)
92 #define FSR_PFPAGE_MASK (0x01 << FSR_PFPAGE)
93 #define FSR_PFOPER_MASK (0x01 << FSR_PFOPER)
94 #define FSR_SQER_MASK (0x01 << FSR_SQER)
95 #define FSR_PROER_MASK (0x01 << FSR_PROER)
96 #define FSR_PFSBER_MASK (0x01 << FSR_PFSBER)
97 #define FSR_PFDBER_MASK (0x01 << FSR_PFDBER)
98 #define FSR_PROIN_MASK (0x01 << FSR_PROIN)
99 #define FSR_RPROIN_MASK (0x01 << FSR_RPROIN)
100 #define FSR_RPRODIS_MASK (0x01 << FSR_RPRODIS)
101 #define FSR_WPROIN0_MASK (0x01 << FSR_WPROIN0)
102 #define FSR_WPROIN1_MASK (0x01 << FSR_WPROIN1)
103 #define FSR_WPROIN2_MASK (0x01 << FSR_WPROIN2)
104 #define FSR_WPRODIS0_MASK (0x01 << FSR_WPRODIS0)
105 #define FSR_WPRODIS1_MASK (0x01 << FSR_WPRODIS1)
106 #define FSR_SLM_MASK (0x01 << FSR_SLM)
107 #define FSR_VER_MASK (0x01 << FSR_VER)
109 /* Flash Config Register */
110 #define FLASH_REG_FLASH0_FCON (FLASH_REG_BASE | 0x2014)
112 #define FCON_WSPFLASH (0)
113 #define FCON_WSECPF (4)
114 #define FCON_IDLE (13)
115 #define FCON_ESLDIS (14)
116 #define FCON_SLEEP (15)
117 #define FCON_RPA (16)
118 #define FCON_DCF (17)
119 #define FCON_DDF (18)
120 #define FCON_VOPERM (24)
121 #define FCON_SQERM (25)
122 #define FCON_PROERM (26)
123 #define FCON_PFSBERM (27)
124 #define FCON_PFDBERM (29)
125 #define FCON_EOBM (31)
127 #define FCON_WSPFLASH_MASK (0x0f << FCON_WSPFLASH)
128 #define FCON_WSECPF_MASK (0x01 << FCON_WSECPF)
129 #define FCON_IDLE_MASK (0x01 << FCON_IDLE)
130 #define FCON_ESLDIS_MASK (0x01 << FCON_ESLDIS)
131 #define FCON_SLEEP_MASK (0x01 << FCON_SLEEP)
132 #define FCON_RPA_MASK (0x01 << FCON_RPA)
133 #define FCON_DCF_MASK (0x01 << FCON_DCF)
134 #define FCON_DDF_MASK (0x01 << FCON_DDF)
135 #define FCON_VOPERM_MASK (0x01 << FCON_VOPERM)
136 #define FCON_SQERM_MASK (0x01 << FCON_SQERM)
137 #define FCON_PROERM_MASK (0x01 << FCON_PROERM)
138 #define FCON_PFSBERM_MASK (0x01 << FCON_PFSBERM)
139 #define FCON_PFDBERM_MASK (0x01 << FCON_PFDBERM)
140 #define FCON_EOBM_MASK (0x01 << FCON_EOBM)
142 /* Flash Margin Control Register */
143 #define FLASH_REG_FLASH0_MARP (FLASH_REG_BASE | 0x2018)
145 #define MARP_MARGIN (0)
146 #define MARP_TRAPDIS (15)
148 #define MARP_MARGIN_MASK (0x0f << MARP_MARGIN)
149 #define MARP_TRAPDIS_MASK (0x01 << MARP_TRAPDIS)
151 /* Flash Protection Registers */
152 #define FLASH_REG_FLASH0_PROCON0 (FLASH_REG_BASE | 0x2020)
153 #define FLASH_REG_FLASH0_PROCON1 (FLASH_REG_BASE | 0x2024)
154 #define FLASH_REG_FLASH0_PROCON2 (FLASH_REG_BASE | 0x2028)
156 #define PROCON_S0L (0)
157 #define PROCON_S1L (1)
158 #define PROCON_S2L (2)
159 #define PROCON_S3L (3)
160 #define PROCON_S4L (4)
161 #define PROCON_S5L (5)
162 #define PROCON_S6L (6)
163 #define PROCON_S7L (7)
164 #define PROCON_S8L (8)
165 #define PROCON_S9L (9)
166 #define PROCON_S10_S11L (10)
167 #define PROCON_RPRO (15)
169 #define PROCON_S0L_MASK (0x01 << PROCON_S0L)
170 #define PROCON_S1L_MASK (0x01 << PROCON_S1L)
171 #define PROCON_S2L_MASK (0x01 << PROCON_S2L)
172 #define PROCON_S3L_MASK (0x01 << PROCON_S3L)
173 #define PROCON_S4L_MASK (0x01 << PROCON_S4L)
174 #define PROCON_S5L_MASK (0x01 << PROCON_S5L)
175 #define PROCON_S6L_MASK (0x01 << PROCON_S6L)
176 #define PROCON_S7L_MASK (0x01 << PROCON_S7L)
177 #define PROCON_S8L_MASK (0x01 << PROCON_S8L)
178 #define PROCON_S9L_MASK (0x01 << PROCON_S9L)
179 #define PROCON_S10_S11L_MASK (0x01 << PROCON_S10_S11L)
180 #define PROCON_RPRO_MASK (0x01 << PROCON_RPRO)
182 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
184 /* Flash controller configuration values */
185 #define FLASH_ID_XMC4500 0xA2
186 #define FLASH_ID_XMC4300_XMC4700_4800 0x92
187 #define FLASH_ID_XMC4100_4200 0x9C
188 #define FLASH_ID_XMC4400 0x9F
191 #define FLASH_OP_TIMEOUT 5000
193 /* Flash commands (write/erase/protect) are performed using special
194 * command sequences that are written to magic addresses in the flash controller */
195 /* Command sequence addresses. See reference manual, section 8: Flash Command Sequences */
196 #define FLASH_CMD_ERASE_1 0x0C005554
197 #define FLASH_CMD_ERASE_2 0x0C00AAA8
198 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
199 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
200 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
201 /* ERASE_6 is the sector base address */
203 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
205 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
207 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
208 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
210 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
211 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
212 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
213 /* WRITE_PAGE_4 is the page base address */
215 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
216 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
217 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
218 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
219 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
220 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
222 struct xmc4xxx_flash_bank
{
225 /* We need the flash controller ID to choose the sector layout */
228 /* Passwords used for protection operations */
233 /* Protection flags */
236 bool write_prot_otp
[MAX_XMC_SECTORS
];
239 struct xmc4xxx_command_seq
{
244 /* Sector capacities. See section 8 of xmc4x00_rm */
245 static const unsigned int sector_capacity_8
[8] = {
246 16, 16, 16, 16, 16, 16, 16, 128
249 static const unsigned int sector_capacity_9
[9] = {
250 16, 16, 16, 16, 16, 16, 16, 128, 256
253 static const unsigned int sector_capacity_12
[12] = {
254 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
257 static const unsigned int sector_capacity_16
[16] = {
258 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256, 256, 256, 256, 256
261 static int xmc4xxx_write_command_sequence(struct flash_bank
*bank
,
262 struct xmc4xxx_command_seq
*seq
,
267 for (int i
= 0; i
< seq_len
; i
++) {
268 res
= target_write_u32(bank
->target
, seq
[i
].address
,
277 static int xmc4xxx_load_bank_layout(struct flash_bank
*bank
)
279 const unsigned int *capacity
= NULL
;
281 /* At this point, we know which flash controller ID we're
282 * talking to and simply need to fill out the bank structure accordingly */
283 LOG_DEBUG("%u sectors", bank
->num_sectors
);
285 switch (bank
->num_sectors
) {
287 capacity
= sector_capacity_8
;
290 capacity
= sector_capacity_9
;
293 capacity
= sector_capacity_12
;
296 capacity
= sector_capacity_16
;
299 LOG_ERROR("Unexpected number of sectors, %u\n",
304 /* This looks like a bank that we understand, now we know the
305 * corresponding sector capacities and we can add those up into the
307 uint32_t total_offset
= 0;
308 bank
->sectors
= calloc(bank
->num_sectors
,
309 sizeof(struct flash_sector
));
310 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
311 bank
->sectors
[i
].size
= capacity
[i
] * 1024;
312 bank
->sectors
[i
].offset
= total_offset
;
313 bank
->sectors
[i
].is_erased
= -1;
314 bank
->sectors
[i
].is_protected
= -1;
316 bank
->size
+= bank
->sectors
[i
].size
;
317 LOG_DEBUG("\t%d: %uk", i
, capacity
[i
]);
318 total_offset
+= bank
->sectors
[i
].size
;
321 /* This part doesn't follow the typical standard of 0xff
322 * being the erased value.*/
323 bank
->default_padded_value
= bank
->erased_value
= 0x00;
328 static int xmc4xxx_probe(struct flash_bank
*bank
)
331 uint32_t devid
, config
;
332 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
338 /* It's not possible for the DAP to access the OTP locations needed for
339 * probing the part info and Flash geometry so we require that the target
340 * be halted before proceeding. */
341 if (bank
->target
->state
!= TARGET_HALTED
) {
342 LOG_WARNING("Cannot communicate... target not halted.");
343 return ERROR_TARGET_NOT_HALTED
;
346 /* The SCU registers contain the ID of the chip */
347 res
= target_read_u32(bank
->target
, SCU_REG_BASE
+ SCU_ID_CHIP
, &devid
);
348 if (res
!= ERROR_OK
) {
349 LOG_ERROR("Cannot read device identification register.");
353 /* Make sure this is a XMC4000 family device */
354 if ((devid
& 0xF0000) != 0x40000 && devid
!= 0) {
355 LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32
, devid
);
359 LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32
, devid
);
361 /* Now sanity-check the Flash controller itself. */
362 res
= target_read_u32(bank
->target
, FLASH_REG_FLASH0_ID
,
364 if (res
!= ERROR_OK
) {
365 LOG_ERROR("Cannot read Flash bank configuration.");
368 flash_id
= (config
& 0xff0000) >> 16;
370 /* The Flash configuration register is our only means of
371 * determining the sector layout. We need to make sure that
372 * we understand the type of controller we're dealing with */
374 case FLASH_ID_XMC4100_4200
:
375 bank
->num_sectors
= 8;
376 LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
378 case FLASH_ID_XMC4400
:
379 bank
->num_sectors
= 9;
380 LOG_DEBUG("XMC4xxx: XMC4400 detected.");
382 case FLASH_ID_XMC4500
:
383 bank
->num_sectors
= 12;
384 LOG_DEBUG("XMC4xxx: XMC4500 detected.");
386 case FLASH_ID_XMC4300_XMC4700_4800
:
387 bank
->num_sectors
= 16;
388 LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
391 LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8
,
396 /* Retrieve information about the particular bank we're probing and fill in
397 * the bank structure accordingly. */
398 res
= xmc4xxx_load_bank_layout(bank
);
399 if (res
== ERROR_OK
) {
403 LOG_ERROR("Unable to load bank information.");
410 static int xmc4xxx_get_sector_start_addr(struct flash_bank
*bank
,
411 unsigned int sector
, uint32_t *ret_addr
)
413 /* Make sure we understand this sector */
414 if (sector
> bank
->num_sectors
)
417 *ret_addr
= bank
->base
+ bank
->sectors
[sector
].offset
;
423 static int xmc4xxx_clear_flash_status(struct flash_bank
*bank
)
426 /* TODO: Do we need to check for sequence error? */
427 LOG_INFO("Clearing flash status");
428 res
= target_write_u32(bank
->target
, FLASH_CMD_CLEAR_STATUS
,
430 if (res
!= ERROR_OK
) {
431 LOG_ERROR("Unable to write erase command sequence");
438 static int xmc4xxx_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
442 res
= target_read_u32(bank
->target
, FLASH_REG_FLASH0_FSR
, status
);
445 LOG_ERROR("Cannot read flash status register.");
450 static int xmc4xxx_wait_status_busy(struct flash_bank
*bank
, int timeout
)
455 res
= xmc4xxx_get_flash_status(bank
, &status
);
459 /* While the flash controller is busy, wait */
460 while (status
& FSR_PBUSY_MASK
) {
461 res
= xmc4xxx_get_flash_status(bank
, &status
);
465 if (timeout
-- <= 0) {
466 LOG_ERROR("Timed out waiting for flash");
473 if (status
& FSR_PROER_MASK
) {
474 LOG_ERROR("XMC4xxx flash protected");
481 static int xmc4xxx_erase_sector(struct flash_bank
*bank
, uint32_t address
,
487 /* See reference manual table 8.4: Command Sequences for Flash Control */
488 struct xmc4xxx_command_seq erase_cmd_seq
[6] = {
489 {FLASH_CMD_ERASE_1
, 0xAA},
490 {FLASH_CMD_ERASE_2
, 0x55},
491 {FLASH_CMD_ERASE_3
, 0x80},
492 {FLASH_CMD_ERASE_4
, 0xAA},
493 {FLASH_CMD_ERASE_5
, 0x55},
494 {0xFF, 0xFF} /* Needs filled in */
497 /* We need to fill in the base address of the sector we'll be
498 * erasing, as well as the magic code that determines whether
499 * this is a standard flash sector or a user configuration block */
501 erase_cmd_seq
[5].address
= address
;
503 /* Removing flash protection requires the addition of
504 * the base address */
505 erase_cmd_seq
[5].address
+= bank
->base
;
506 erase_cmd_seq
[5].magic
= 0xC0;
508 erase_cmd_seq
[5].magic
= 0x30;
511 res
= xmc4xxx_write_command_sequence(bank
, erase_cmd_seq
,
512 ARRAY_SIZE(erase_cmd_seq
));
516 /* Read the flash status register */
517 res
= target_read_u32(bank
->target
, FLASH_REG_FLASH0_FSR
, &status
);
518 if (res
!= ERROR_OK
) {
519 LOG_ERROR("Cannot read flash status register.");
523 /* Check for a sequence error */
524 if (status
& FSR_SQER_MASK
) {
525 LOG_ERROR("Error with flash erase sequence");
529 /* Make sure a flash erase was triggered */
530 if (!(status
& FSR_ERASE_MASK
)) {
531 LOG_ERROR("Flash failed to erase");
535 /* Now we must wait for the erase operation to end */
536 res
= xmc4xxx_wait_status_busy(bank
, FLASH_OP_TIMEOUT
);
541 static int xmc4xxx_erase(struct flash_bank
*bank
, unsigned int first
,
544 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
547 if (bank
->target
->state
!= TARGET_HALTED
) {
548 LOG_ERROR("Unable to erase, target is not halted");
549 return ERROR_TARGET_NOT_HALTED
;
553 res
= xmc4xxx_probe(bank
);
559 /* Loop through the sectors and erase each one */
560 for (unsigned int i
= first
; i
<= last
; i
++) {
561 res
= xmc4xxx_get_sector_start_addr(bank
, i
, &tmp_addr
);
562 if (res
!= ERROR_OK
) {
563 LOG_ERROR("Invalid sector %u", i
);
567 LOG_DEBUG("Erasing sector %u @ 0x%08"PRIx32
, i
, tmp_addr
);
569 res
= xmc4xxx_erase_sector(bank
, tmp_addr
, false);
570 if (res
!= ERROR_OK
) {
571 LOG_ERROR("Unable to write erase command sequence");
572 goto clear_status_and_exit
;
575 /* Now we must wait for the erase operation to end */
576 res
= xmc4xxx_wait_status_busy(bank
, FLASH_OP_TIMEOUT
);
579 goto clear_status_and_exit
;
582 clear_status_and_exit
:
583 res
= xmc4xxx_clear_flash_status(bank
);
588 static int xmc4xxx_enter_page_mode(struct flash_bank
*bank
)
593 res
= target_write_u32(bank
->target
, FLASH_CMD_ENTER_PAGEMODE
, 0x50);
594 if (res
!= ERROR_OK
) {
595 LOG_ERROR("Unable to write enter page mode command");
599 res
= xmc4xxx_get_flash_status(bank
, &status
);
604 /* Make sure we're in page mode */
605 if (!(status
& FSR_PFPAGE_MASK
)) {
606 LOG_ERROR("Unable to enter page mode");
610 /* Make sure we didn't encounter a sequence error */
611 if (status
& FSR_SQER_MASK
) {
612 LOG_ERROR("Sequence error while entering page mode");
619 static int xmc4xxx_write_page(struct flash_bank
*bank
, const uint8_t *pg_buf
,
620 uint32_t offset
, bool user_config
)
625 /* Base of the flash write command */
626 struct xmc4xxx_command_seq write_cmd_seq
[4] = {
627 {FLASH_CMD_WRITE_PAGE_1
, 0xAA},
628 {FLASH_CMD_WRITE_PAGE_2
, 0x55},
629 {FLASH_CMD_WRITE_PAGE_3
, 0xFF}, /* Needs filled in */
630 {0xFF, 0xFF} /* Needs filled in */
633 /* The command sequence differs depending on whether this is
634 * being written to standard flash or the user configuration
637 write_cmd_seq
[2].magic
= 0xC0;
639 write_cmd_seq
[2].magic
= 0xA0;
641 /* Finally, we need to add the address that this page will be
643 write_cmd_seq
[3].address
= bank
->base
+ offset
;
644 write_cmd_seq
[3].magic
= 0xAA;
647 /* Flash pages are written 256 bytes at a time. For each 256
648 * byte chunk, we need to:
649 * 1. Enter page mode. This activates the flash write buffer
650 * 2. Load the page buffer with data (2x 32 bit words at a time)
651 * 3. Burn the page buffer into its intended location
652 * If the starting offset is not on a 256 byte boundary, we
653 * will need to pad the beginning of the write buffer
654 * accordingly. Likewise, if the last page does not fill the
655 * buffer, we should pad it to avoid leftover data from being
658 res
= xmc4xxx_enter_page_mode(bank
);
662 /* Copy the data into the page buffer*/
663 for (int i
= 0; i
< 256; i
+= 8) {
664 uint32_t w_lo
= target_buffer_get_u32(bank
->target
, &pg_buf
[i
]);
665 uint32_t w_hi
= target_buffer_get_u32(bank
->target
, &pg_buf
[i
+ 4]);
666 LOG_DEBUG("WLO: %08"PRIx32
, w_lo
);
667 LOG_DEBUG("WHI: %08"PRIx32
, w_hi
);
669 /* Data is loaded 2x 32 bit words at a time */
670 res
= target_write_u32(bank
->target
, FLASH_CMD_LOAD_PAGE_1
, w_lo
);
674 res
= target_write_u32(bank
->target
, FLASH_CMD_LOAD_PAGE_2
, w_hi
);
678 /* Check for an error */
679 res
= xmc4xxx_get_flash_status(bank
, &status
);
683 if (status
& FSR_SQER_MASK
) {
684 LOG_ERROR("Error loading page buffer");
689 /* The page buffer is now full, time to commit it to flash */
691 res
= xmc4xxx_write_command_sequence(bank
, write_cmd_seq
, ARRAY_SIZE(write_cmd_seq
));
692 if (res
!= ERROR_OK
) {
693 LOG_ERROR("Unable to enter write command sequence");
697 /* Read the flash status register */
698 res
= xmc4xxx_get_flash_status(bank
, &status
);
702 /* Check for a sequence error */
703 if (status
& FSR_SQER_MASK
) {
704 LOG_ERROR("Error with flash write sequence");
708 /* Make sure a flash write was triggered */
709 if (!(status
& FSR_PROG_MASK
)) {
710 LOG_ERROR("Failed to write flash page");
714 /* Wait for the write operation to end */
715 res
= xmc4xxx_wait_status_busy(bank
, FLASH_OP_TIMEOUT
);
719 /* TODO: Verify that page was written without error */
723 static int xmc4xxx_write(struct flash_bank
*bank
, const uint8_t *buffer
,
724 uint32_t offset
, uint32_t count
)
726 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
729 if (bank
->target
->state
!= TARGET_HALTED
) {
730 LOG_ERROR("Unable to erase, target is not halted");
731 return ERROR_TARGET_NOT_HALTED
;
735 res
= xmc4xxx_probe(bank
);
740 /* Make sure we won't run off the end of the flash bank */
741 if ((offset
+ count
) > (bank
->size
)) {
742 LOG_ERROR("Attempting to write past the end of flash");
747 /* Attempt to write the passed in buffer to flash */
748 /* Pages are written 256 bytes at a time, we need to handle
749 * scenarios where padding is required at the beginning and
752 /* page working area */
753 uint8_t tmp_buf
[256] = {0};
755 /* Amount of data we'll be writing to this page */
759 remaining
= MIN(count
, sizeof(tmp_buf
));
760 end_pad
= sizeof(tmp_buf
) - remaining
;
762 /* Make sure we're starting on a page boundary */
763 int start_pad
= offset
% 256;
765 LOG_INFO("Write does not start on a 256 byte boundary. "
766 "Padding by %d bytes", start_pad
);
767 memset(tmp_buf
, 0xff, start_pad
);
768 /* Subtract the amount of start offset from
769 * the amount of data we'll need to write */
770 remaining
-= start_pad
;
773 /* Remove the amount we'll be writing from the total count */
776 /* Now copy in the remaining data */
777 memcpy(&tmp_buf
[start_pad
], buffer
, remaining
);
780 LOG_INFO("Padding end of page @" TARGET_ADDR_FMT
" by %d bytes",
781 bank
->base
+ offset
, end_pad
);
782 memset(&tmp_buf
[256 - end_pad
], 0xff, end_pad
);
785 /* Now commit this page to flash, if there was start
786 * padding, we should subtract that from the target offset */
787 res
= xmc4xxx_write_page(bank
, tmp_buf
, (offset
- start_pad
), false);
788 if (res
!= ERROR_OK
) {
789 LOG_ERROR("Unable to write flash page");
790 goto abort_write_and_exit
;
793 /* Advance the buffer pointer */
796 /* Advance the offset */
800 abort_write_and_exit
:
801 xmc4xxx_clear_flash_status(bank
);
806 static int xmc4xxx_get_info_command(struct flash_bank
*bank
, struct command_invocation
*cmd
)
808 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
811 if (bank
->target
->state
!= TARGET_HALTED
) {
812 LOG_WARNING("Cannot communicate... target not halted.");
813 return ERROR_TARGET_NOT_HALTED
;
816 /* The SCU registers contain the ID of the chip */
817 int res
= target_read_u32(bank
->target
, SCU_REG_BASE
+ SCU_ID_CHIP
, &scu_idcode
);
818 if (res
!= ERROR_OK
) {
819 LOG_ERROR("Cannot read device identification register.");
823 uint16_t dev_id
= (scu_idcode
& 0xfff0) >> 4;
824 uint16_t rev_id
= scu_idcode
& 0xf;
826 const char *rev_str
= NULL
;
874 /* XMC4500 EES AA13 with date codes before GE212
875 * had zero SCU_IDCHIP
877 dev_str
= "XMC4500 EES";
915 command_print_sameline(cmd
, "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32
"\n", scu_idcode
);
919 /* String to declare protection data held in the private driver */
920 char prot_str
[512] = {0};
921 if (fb
->read_protected
)
922 snprintf(prot_str
, sizeof(prot_str
), "\nFlash is read protected");
924 bool otp_enabled
= false;
925 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
926 if (fb
->write_prot_otp
[i
])
929 /* If OTP Write protection is enabled (User 2), list each
930 * sector that has it enabled */
933 strcat(prot_str
, "\nOTP Protection is enabled for sectors:\n");
934 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
935 if (fb
->write_prot_otp
[i
]) {
936 snprintf(otp_str
, sizeof(otp_str
), "- %d\n", i
);
937 strncat(prot_str
, otp_str
, sizeof(prot_str
) - strlen(prot_str
) - 1);
943 command_print_sameline(cmd
, "%s - Rev: %s%s", dev_str
, rev_str
, prot_str
);
945 command_print_sameline(cmd
, "%s - Rev: unknown (0x%01x)%s", dev_str
, rev_id
, prot_str
);
950 static int xmc4xxx_temp_unprotect(struct flash_bank
*bank
, int user_level
)
952 struct xmc4xxx_flash_bank
*fb
;
956 struct xmc4xxx_command_seq temp_unprot_seq
[6] = {
957 {FLASH_CMD_TEMP_UNPROT_1
, 0xAA},
958 {FLASH_CMD_TEMP_UNPROT_2
, 0x55},
959 {FLASH_CMD_TEMP_UNPROT_3
, 0xFF}, /* Needs filled in */
960 {FLASH_CMD_TEMP_UNPROT_4
, 0xFF}, /* Needs filled in */
961 {FLASH_CMD_TEMP_UNPROT_5
, 0xFF}, /* Needs filled in */
962 {FLASH_CMD_TEMP_UNPROT_6
, 0x05}
965 if (user_level
< 0 || user_level
> 2) {
966 LOG_ERROR("Invalid user level, must be 0-2");
970 fb
= bank
->driver_priv
;
972 /* Fill in the user level and passwords */
973 temp_unprot_seq
[2].magic
= user_level
;
974 temp_unprot_seq
[3].magic
= fb
->pw1
;
975 temp_unprot_seq
[4].magic
= fb
->pw2
;
977 res
= xmc4xxx_write_command_sequence(bank
, temp_unprot_seq
,
978 ARRAY_SIZE(temp_unprot_seq
));
979 if (res
!= ERROR_OK
) {
980 LOG_ERROR("Unable to write temp unprotect sequence");
984 res
= xmc4xxx_get_flash_status(bank
, &status
);
988 if (status
& FSR_WPRODIS0
) {
989 LOG_INFO("Flash is temporarily unprotected");
991 LOG_INFO("Unable to disable flash protection");
999 static int xmc4xxx_flash_unprotect(struct flash_bank
*bank
, int32_t level
)
1012 LOG_ERROR("Invalid user level. Must be 0-1");
1016 res
= xmc4xxx_erase_sector(bank
, addr
, true);
1018 if (res
!= ERROR_OK
)
1019 LOG_ERROR("Error erasing user configuration block");
1024 /* Reference: "XMC4500 Flash Protection.pptx" app note */
1025 static int xmc4xxx_flash_protect(struct flash_bank
*bank
, int level
, bool read_protect
,
1026 unsigned int first
, unsigned int last
)
1028 /* User configuration block buffers */
1029 uint8_t ucp0_buf
[8 * sizeof(uint32_t)] = {0};
1030 uint32_t ucb_base
= 0;
1031 uint32_t procon
= 0;
1033 uint32_t status
= 0;
1036 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
1038 /* Read protect only works for user 0, make sure we don't try
1039 * to do something silly */
1040 if (level
!= 0 && read_protect
) {
1041 LOG_ERROR("Read protection is for user level 0 only!");
1045 /* Check to see if protection is already installed for the
1046 * specified user level. If it is, the user configuration
1047 * block will need to be erased before we can continue */
1049 /* Grab the flash status register*/
1050 res
= xmc4xxx_get_flash_status(bank
, &status
);
1051 if (res
!= ERROR_OK
)
1056 if ((status
& FSR_RPROIN_MASK
) || (status
& FSR_WPROIN0_MASK
))
1060 if (status
& FSR_WPROIN1_MASK
)
1064 if (status
& FSR_WPROIN2_MASK
)
1070 LOG_ERROR("Flash protection is installed for user %d"
1071 " and must be removed before continuing", level
);
1075 /* If this device has 12 flash sectors, protection for
1076 * sectors 10 & 11 are handled jointly. If we are trying to
1077 * write all sectors, we should decrement
1078 * last to ensure we don't write to a register bit that
1080 if ((bank
->num_sectors
== 12) && (last
== 12))
1083 /* We need to fill out the procon register representation
1084 * that we will be writing to the device */
1085 for (unsigned int i
= first
; i
<= last
; i
++)
1088 /* If read protection is requested, set the appropriate bit
1089 * (we checked that this is allowed above) */
1091 procon
|= PROCON_RPRO_MASK
;
1093 LOG_DEBUG("Setting flash protection with procon:");
1094 LOG_DEBUG("PROCON: %"PRIx32
, procon
);
1096 /* First we need to copy in the procon register to the buffer
1097 * we're going to attempt to write. This is written twice */
1098 target_buffer_set_u32(bank
->target
, &ucp0_buf
[0 * 4], procon
);
1099 target_buffer_set_u32(bank
->target
, &ucp0_buf
[2 * 4], procon
);
1101 /* Now we must copy in both flash passwords. As with the
1102 * procon data, this must be written twice (4 total words
1104 target_buffer_set_u32(bank
->target
, &ucp0_buf
[4 * 4], fb
->pw1
);
1105 target_buffer_set_u32(bank
->target
, &ucp0_buf
[5 * 4], fb
->pw2
);
1106 target_buffer_set_u32(bank
->target
, &ucp0_buf
[6 * 4], fb
->pw1
);
1107 target_buffer_set_u32(bank
->target
, &ucp0_buf
[7 * 4], fb
->pw2
);
1109 /* Finally, (if requested) we copy in the confirmation
1110 * code so that the protection is permanent and will
1111 * require a password to undo. */
1112 target_buffer_set_u32(bank
->target
, &ucp0_buf
[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE
);
1113 target_buffer_set_u32(bank
->target
, &ucp0_buf
[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE
);
1115 /* Now that the data is copied into place, we must write
1116 * these pages into flash */
1118 /* The user configuration block base depends on what level of
1119 * protection we're trying to install, select the proper one */
1122 ucb_base
= UCB0_BASE
;
1125 ucb_base
= UCB1_BASE
;
1128 ucb_base
= UCB2_BASE
;
1132 /* Write the user config pages */
1133 res
= xmc4xxx_write_page(bank
, ucp0_buf
, ucb_base
, true);
1134 if (res
!= ERROR_OK
) {
1135 LOG_ERROR("Error writing user configuration block 0");
1142 static int xmc4xxx_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
1146 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
1148 /* Check for flash passwords */
1150 LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
1154 /* We want to clear flash protection temporarily*/
1156 LOG_WARNING("Flash protection will be temporarily disabled"
1157 " for all pages (User 0 only)!");
1158 ret
= xmc4xxx_temp_unprotect(bank
, 0);
1162 /* Install write protection for user 0 on the specified pages */
1163 ret
= xmc4xxx_flash_protect(bank
, 0, false, first
, last
);
1168 static int xmc4xxx_protect_check(struct flash_bank
*bank
)
1171 uint32_t protection
[3] = {0};
1172 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
1174 ret
= target_read_u32(bank
->target
, FLASH_REG_FLASH0_PROCON0
, &protection
[0]);
1175 if (ret
!= ERROR_OK
) {
1176 LOG_ERROR("Unable to read flash User0 protection register");
1180 ret
= target_read_u32(bank
->target
, FLASH_REG_FLASH0_PROCON1
, &protection
[1]);
1181 if (ret
!= ERROR_OK
) {
1182 LOG_ERROR("Unable to read flash User1 protection register");
1186 ret
= target_read_u32(bank
->target
, FLASH_REG_FLASH0_PROCON2
, &protection
[2]);
1187 if (ret
!= ERROR_OK
) {
1188 LOG_ERROR("Unable to read flash User2 protection register");
1192 unsigned int sectors
= bank
->num_sectors
;
1194 /* On devices with 12 sectors, sectors 10 & 11 are protected
1195 * together instead of individually */
1199 /* Clear the protection status */
1200 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
1201 bank
->sectors
[i
].is_protected
= 0;
1202 fb
->write_prot_otp
[i
] = false;
1204 fb
->read_protected
= false;
1206 /* The xmc4xxx series supports 3 levels of user protection
1207 * (User0, User1 (low priority), and User 2(OTP), we need to
1209 for (unsigned int i
= 0; i
< ARRAY_SIZE(protection
); i
++) {
1211 /* Check for write protection on every available
1213 for (unsigned int j
= 0; j
< sectors
; j
++) {
1214 int set
= (protection
[i
] & (1 << j
)) ? 1 : 0;
1215 bank
->sectors
[j
].is_protected
|= set
;
1217 /* Handle sector 11 */
1219 bank
->sectors
[j
+ 1].is_protected
|= set
;
1221 /* User 2 indicates this protection is
1222 * permanent, make note in the private driver structure */
1223 if (i
== 2 && set
) {
1224 fb
->write_prot_otp
[j
] = true;
1226 /* Handle sector 11 */
1228 fb
->write_prot_otp
[j
+ 1] = true;
1234 /* XMC4xxx also supports read protection, make a note
1235 * in the private driver structure */
1236 if (protection
[0] & PROCON_RPRO_MASK
)
1237 fb
->read_protected
= true;
1242 FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command
)
1244 bank
->driver_priv
= malloc(sizeof(struct xmc4xxx_flash_bank
));
1246 if (!bank
->driver_priv
)
1247 return ERROR_FLASH_OPERATION_FAILED
;
1249 (void)memset(bank
->driver_priv
, 0, sizeof(struct xmc4xxx_flash_bank
));
1254 COMMAND_HANDLER(xmc4xxx_handle_flash_password_command
)
1257 struct flash_bank
*bank
;
1260 return ERROR_COMMAND_SYNTAX_ERROR
;
1262 res
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1263 if (res
!= ERROR_OK
)
1266 struct xmc4xxx_flash_bank
*fb
= bank
->driver_priv
;
1270 /* We skip over the flash bank */
1271 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], fb
->pw1
);
1274 return ERROR_COMMAND_SYNTAX_ERROR
;
1276 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], fb
->pw2
);
1279 return ERROR_COMMAND_SYNTAX_ERROR
;
1283 command_print(CMD
, "XMC4xxx flash passwords set to:\n");
1284 command_print(CMD
, "-0x%08"PRIx32
"\n", fb
->pw1
);
1285 command_print(CMD
, "-0x%08"PRIx32
"\n", fb
->pw2
);
1289 COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command
)
1291 struct flash_bank
*bank
;
1296 return ERROR_COMMAND_SYNTAX_ERROR
;
1298 res
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1299 if (res
!= ERROR_OK
)
1302 COMMAND_PARSE_NUMBER(s32
, CMD_ARGV
[1], level
);
1304 res
= xmc4xxx_flash_unprotect(bank
, level
);
1309 static const struct command_registration xmc4xxx_exec_command_handlers
[] = {
1311 .name
= "flash_password",
1312 .handler
= xmc4xxx_handle_flash_password_command
,
1313 .mode
= COMMAND_EXEC
,
1314 .usage
= "bank_id password1 password2",
1315 .help
= "Set the flash passwords used for protect operations. "
1316 "Passwords should be in standard hex form (0x00000000). "
1317 "(You must call this before any other protect commands) "
1318 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1319 "Please use protection carefully!",
1322 .name
= "flash_unprotect",
1323 .handler
= xmc4xxx_handle_flash_unprotect_command
,
1324 .mode
= COMMAND_EXEC
,
1325 .usage
= "bank_id user_level[0-1]",
1326 .help
= "Permanently Removes flash protection (read and write) "
1327 "for the specified user level",
1329 COMMAND_REGISTRATION_DONE
1332 static const struct command_registration xmc4xxx_command_handlers
[] = {
1335 .mode
= COMMAND_ANY
,
1336 .help
= "xmc4xxx flash command group",
1338 .chain
= xmc4xxx_exec_command_handlers
,
1340 COMMAND_REGISTRATION_DONE
1343 const struct flash_driver xmc4xxx_flash
= {
1345 .commands
= xmc4xxx_command_handlers
,
1346 .flash_bank_command
= xmc4xxx_flash_bank_command
,
1347 .erase
= xmc4xxx_erase
,
1348 .write
= xmc4xxx_write
,
1349 .read
= default_flash_read
,
1350 .probe
= xmc4xxx_probe
,
1351 .auto_probe
= xmc4xxx_probe
,
1352 .erase_check
= default_flash_blank_check
,
1353 .info
= xmc4xxx_get_info_command
,
1354 .protect_check
= xmc4xxx_protect_check
,
1355 .protect
= xmc4xxx_protect
,
1356 .free_driver_priv
= default_flash_free_driver_priv
,
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