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Cortex-M3 cleanup and performance patch
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "stm32x.h"
30 #include "flash.h"
31 #include "target.h"
32 #include "log.h"
33 #include "armv7m.h"
34 #include "algorithm.h"
35 #include "binarybuffer.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 int stm32x_register_commands(struct command_context_s *cmd_ctx);
41 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
42 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
43 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
44 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
45 int stm32x_probe(struct flash_bank_s *bank);
46 int stm32x_auto_probe(struct flash_bank_s *bank);
47 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int stm32x_protect_check(struct flash_bank_s *bank);
49 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
50
51 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int stm32x_mass_erase(struct flash_bank_s *bank);
57
58 flash_driver_t stm32x_flash =
59 {
60 .name = "stm32x",
61 .register_commands = stm32x_register_commands,
62 .flash_bank_command = stm32x_flash_bank_command,
63 .erase = stm32x_erase,
64 .protect = stm32x_protect,
65 .write = stm32x_write,
66 .probe = stm32x_probe,
67 .auto_probe = stm32x_auto_probe,
68 .erase_check = default_flash_mem_blank_check,
69 .protect_check = stm32x_protect_check,
70 .info = stm32x_info
71 };
72
73 int stm32x_register_commands(struct command_context_s *cmd_ctx)
74 {
75 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
76
77 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
78 "lock device");
79 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
80 "unlock protected device");
81 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
82 "mass erase device");
83 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
84 "read device option bytes");
85 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
86 "write device option bytes");
87 return ERROR_OK;
88 }
89
90 /* flash bank stm32x <base> <size> 0 0 <target#>
91 */
92 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
93 {
94 stm32x_flash_bank_t *stm32x_info;
95
96 if (argc < 6)
97 {
98 LOG_WARNING("incomplete flash_bank stm32x configuration");
99 return ERROR_FLASH_BANK_INVALID;
100 }
101
102 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
103 bank->driver_priv = stm32x_info;
104
105 stm32x_info->write_algorithm = NULL;
106 stm32x_info->probed = 0;
107
108 return ERROR_OK;
109 }
110
111 u32 stm32x_get_flash_status(flash_bank_t *bank)
112 {
113 target_t *target = bank->target;
114 u32 status;
115
116 target_read_u32(target, STM32_FLASH_SR, &status);
117
118 return status;
119 }
120
121 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
122 {
123 u32 status;
124
125 /* wait for busy to clear */
126 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
127 {
128 LOG_DEBUG("status: 0x%x", status);
129 alive_sleep(1);
130 }
131
132 return status;
133 }
134
135 int stm32x_read_options(struct flash_bank_s *bank)
136 {
137 u32 optiondata;
138 stm32x_flash_bank_t *stm32x_info = NULL;
139 target_t *target = bank->target;
140
141 stm32x_info = bank->driver_priv;
142
143 /* read current option bytes */
144 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
145
146 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
147 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
148
149 if (optiondata & (1 << OPT_READOUT))
150 LOG_INFO("Device Security Bit Set");
151
152 /* each bit refers to a 4bank protection */
153 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
154
155 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
156 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
157 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
158 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
159
160 return ERROR_OK;
161 }
162
163 int stm32x_erase_options(struct flash_bank_s *bank)
164 {
165 stm32x_flash_bank_t *stm32x_info = NULL;
166 target_t *target = bank->target;
167 u32 status;
168
169 stm32x_info = bank->driver_priv;
170
171 /* read current options */
172 stm32x_read_options(bank);
173
174 /* unlock flash registers */
175 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
176 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
177
178 /* unlock option flash registers */
179 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
180 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
181
182 /* erase option bytes */
183 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
184 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
185
186 status = stm32x_wait_status_busy(bank, 10);
187
188 if( status & FLASH_WRPRTERR )
189 return ERROR_FLASH_OPERATION_FAILED;
190 if( status & FLASH_PGERR )
191 return ERROR_FLASH_OPERATION_FAILED;
192
193 /* clear readout protection and complementary option bytes
194 * this will also force a device unlock if set */
195 stm32x_info->option_bytes.RDP = 0x5AA5;
196
197 return ERROR_OK;
198 }
199
200 int stm32x_write_options(struct flash_bank_s *bank)
201 {
202 stm32x_flash_bank_t *stm32x_info = NULL;
203 target_t *target = bank->target;
204 u32 status;
205
206 stm32x_info = bank->driver_priv;
207
208 /* unlock flash registers */
209 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
210 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
211
212 /* unlock option flash registers */
213 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
214 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
215
216 /* program option bytes */
217 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
218
219 /* write user option byte */
220 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
221
222 status = stm32x_wait_status_busy(bank, 10);
223
224 if( status & FLASH_WRPRTERR )
225 return ERROR_FLASH_OPERATION_FAILED;
226 if( status & FLASH_PGERR )
227 return ERROR_FLASH_OPERATION_FAILED;
228
229 /* write protection byte 1 */
230 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
231
232 status = stm32x_wait_status_busy(bank, 10);
233
234 if( status & FLASH_WRPRTERR )
235 return ERROR_FLASH_OPERATION_FAILED;
236 if( status & FLASH_PGERR )
237 return ERROR_FLASH_OPERATION_FAILED;
238
239 /* write protection byte 2 */
240 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
241
242 status = stm32x_wait_status_busy(bank, 10);
243
244 if( status & FLASH_WRPRTERR )
245 return ERROR_FLASH_OPERATION_FAILED;
246 if( status & FLASH_PGERR )
247 return ERROR_FLASH_OPERATION_FAILED;
248
249 /* write protection byte 3 */
250 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
251
252 status = stm32x_wait_status_busy(bank, 10);
253
254 if( status & FLASH_WRPRTERR )
255 return ERROR_FLASH_OPERATION_FAILED;
256 if( status & FLASH_PGERR )
257 return ERROR_FLASH_OPERATION_FAILED;
258
259 /* write protection byte 4 */
260 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
261
262 status = stm32x_wait_status_busy(bank, 10);
263
264 if( status & FLASH_WRPRTERR )
265 return ERROR_FLASH_OPERATION_FAILED;
266 if( status & FLASH_PGERR )
267 return ERROR_FLASH_OPERATION_FAILED;
268
269 /* write readout protection bit */
270 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
271
272 status = stm32x_wait_status_busy(bank, 10);
273
274 if( status & FLASH_WRPRTERR )
275 return ERROR_FLASH_OPERATION_FAILED;
276 if( status & FLASH_PGERR )
277 return ERROR_FLASH_OPERATION_FAILED;
278
279 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
280
281 return ERROR_OK;
282 }
283
284 int stm32x_protect_check(struct flash_bank_s *bank)
285 {
286 target_t *target = bank->target;
287 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
288
289 u32 protection;
290 int i, s;
291 int num_bits;
292 int set;
293
294 if (target->state != TARGET_HALTED)
295 {
296 LOG_ERROR("Target not halted");
297 return ERROR_TARGET_NOT_HALTED;
298 }
299
300 /* medium density - each bit refers to a 4bank protection
301 * high density - each bit refers to a 2bank protection */
302 target_read_u32(target, STM32_FLASH_WRPR, &protection);
303
304 /* medium density - each protection bit is for 4 * 1K pages
305 * high density - each protection bit is for 2 * 2K pages */
306 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
307
308 if (stm32x_info->ppage_size == 2)
309 {
310 /* high density flash */
311
312 set = 1;
313
314 if (protection & (1 << 31))
315 set = 0;
316
317 /* bit 31 controls sector 62 - 255 protection */
318 for (s = 62; s < bank->num_sectors; s++)
319 {
320 bank->sectors[s].is_protected = set;
321 }
322
323 if (bank->num_sectors > 61)
324 num_bits = 31;
325
326 for (i = 0; i < num_bits; i++)
327 {
328 set = 1;
329
330 if (protection & (1 << i))
331 set = 0;
332
333 for (s = 0; s < stm32x_info->ppage_size; s++)
334 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
335 }
336 }
337 else
338 {
339 /* medium density flash */
340 for (i = 0; i < num_bits; i++)
341 {
342 set = 1;
343
344 if( protection & (1 << i))
345 set = 0;
346
347 for (s = 0; s < stm32x_info->ppage_size; s++)
348 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
349 }
350 }
351
352 return ERROR_OK;
353 }
354
355 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
356 {
357 target_t *target = bank->target;
358 int i;
359 u32 status;
360
361 if (bank->target->state != TARGET_HALTED)
362 {
363 LOG_ERROR("Target not halted");
364 return ERROR_TARGET_NOT_HALTED;
365 }
366
367 if ((first == 0) && (last == (bank->num_sectors - 1)))
368 {
369 return stm32x_mass_erase(bank);
370 }
371
372 /* unlock flash registers */
373 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
374 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
375
376 for (i = first; i <= last; i++)
377 {
378 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
379 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
380 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
381
382 status = stm32x_wait_status_busy(bank, 10);
383
384 if( status & FLASH_WRPRTERR )
385 return ERROR_FLASH_OPERATION_FAILED;
386 if( status & FLASH_PGERR )
387 return ERROR_FLASH_OPERATION_FAILED;
388 bank->sectors[i].is_erased = 1;
389 }
390
391 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
392
393 return ERROR_OK;
394 }
395
396 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
397 {
398 stm32x_flash_bank_t *stm32x_info = NULL;
399 target_t *target = bank->target;
400 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
401 int i, reg, bit;
402 int status;
403 u32 protection;
404
405 stm32x_info = bank->driver_priv;
406
407 if (target->state != TARGET_HALTED)
408 {
409 LOG_ERROR("Target not halted");
410 return ERROR_TARGET_NOT_HALTED;
411 }
412
413 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
414 {
415 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
416 return ERROR_FLASH_SECTOR_INVALID;
417 }
418
419 /* medium density - each bit refers to a 4bank protection
420 * high density - each bit refers to a 2bank protection */
421 target_read_u32(target, STM32_FLASH_WRPR, &protection);
422
423 prot_reg[0] = (u16)protection;
424 prot_reg[1] = (u16)(protection >> 8);
425 prot_reg[2] = (u16)(protection >> 16);
426 prot_reg[3] = (u16)(protection >> 24);
427
428 if (stm32x_info->ppage_size == 2)
429 {
430 /* high density flash */
431
432 /* bit 7 controls sector 62 - 255 protection */
433 if (last > 61)
434 {
435 if (set)
436 prot_reg[3] &= ~(1 << 7);
437 else
438 prot_reg[3] |= (1 << 7);
439 }
440
441 if (first > 61)
442 first = 62;
443 if (last > 61)
444 last = 61;
445
446 for (i = first; i <= last; i++)
447 {
448 reg = (i / stm32x_info->ppage_size) / 8;
449 bit = (i / stm32x_info->ppage_size) - (reg * 8);
450
451 if( set )
452 prot_reg[reg] &= ~(1 << bit);
453 else
454 prot_reg[reg] |= (1 << bit);
455 }
456 }
457 else
458 {
459 /* medium density flash */
460 for (i = first; i <= last; i++)
461 {
462 reg = (i / stm32x_info->ppage_size) / 8;
463 bit = (i / stm32x_info->ppage_size) - (reg * 8);
464
465 if( set )
466 prot_reg[reg] &= ~(1 << bit);
467 else
468 prot_reg[reg] |= (1 << bit);
469 }
470 }
471
472 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
473 return status;
474
475 stm32x_info->option_bytes.protection[0] = prot_reg[0];
476 stm32x_info->option_bytes.protection[1] = prot_reg[1];
477 stm32x_info->option_bytes.protection[2] = prot_reg[2];
478 stm32x_info->option_bytes.protection[3] = prot_reg[3];
479
480 return stm32x_write_options(bank);
481 }
482
483 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
484 {
485 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
486 target_t *target = bank->target;
487 u32 buffer_size = 16384;
488 working_area_t *source;
489 u32 address = bank->base + offset;
490 reg_param_t reg_params[4];
491 armv7m_algorithm_t armv7m_info;
492 int retval = ERROR_OK;
493
494 u8 stm32x_flash_write_code[] = {
495 /* write: */
496 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
497 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
498 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
499 0x23, 0x60, /* str r3, [r4, #0] */
500 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
501 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
502 /* busy: */
503 0x2B, 0x68, /* ldr r3, [r5, #0] */
504 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
505 0xFB, 0xD0, /* beq busy */
506 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
507 0x01, 0xD1, /* bne exit */
508 0x01, 0x3A, /* subs r2, r2, #1 */
509 0xED, 0xD1, /* bne write */
510 /* exit: */
511 0xFE, 0xE7, /* b exit */
512 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
513 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
514 };
515
516 /* flash write code */
517 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
518 {
519 LOG_WARNING("no working area available, can't do block memory writes");
520 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
521 };
522
523 if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
524 return retval;
525
526 /* memory buffer */
527 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
528 {
529 buffer_size /= 2;
530 if (buffer_size <= 256)
531 {
532 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
533 if (stm32x_info->write_algorithm)
534 target_free_working_area(target, stm32x_info->write_algorithm);
535
536 LOG_WARNING("no large enough working area available, can't do block memory writes");
537 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
538 }
539 };
540
541 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
542 armv7m_info.core_mode = ARMV7M_MODE_ANY;
543
544 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
545 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
546 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
547 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
548
549 while (count > 0)
550 {
551 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
552
553 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
554 break;
555
556 buf_set_u32(reg_params[0].value, 0, 32, source->address);
557 buf_set_u32(reg_params[1].value, 0, 32, address);
558 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
559
560 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
561 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
562 {
563 LOG_ERROR("error executing stm32x flash write algorithm");
564 retval = ERROR_FLASH_OPERATION_FAILED;
565 break;
566 }
567
568 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
569 {
570 retval = ERROR_FLASH_OPERATION_FAILED;
571 break;
572 }
573
574 buffer += thisrun_count * 2;
575 address += thisrun_count * 2;
576 count -= thisrun_count;
577 }
578
579 target_free_working_area(target, source);
580 target_free_working_area(target, stm32x_info->write_algorithm);
581
582 destroy_reg_param(&reg_params[0]);
583 destroy_reg_param(&reg_params[1]);
584 destroy_reg_param(&reg_params[2]);
585 destroy_reg_param(&reg_params[3]);
586
587 return retval;
588 }
589
590 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
591 {
592 target_t *target = bank->target;
593 u32 words_remaining = (count / 2);
594 u32 bytes_remaining = (count & 0x00000001);
595 u32 address = bank->base + offset;
596 u32 bytes_written = 0;
597 u8 status;
598 u32 retval;
599
600 if (bank->target->state != TARGET_HALTED)
601 {
602 LOG_ERROR("Target not halted");
603 return ERROR_TARGET_NOT_HALTED;
604 }
605
606 if (offset & 0x1)
607 {
608 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
609 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
610 }
611
612 /* unlock flash registers */
613 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
614 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
615
616 /* multiple half words (2-byte) to be programmed? */
617 if (words_remaining > 0)
618 {
619 /* try using a block write */
620 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
621 {
622 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
623 {
624 /* if block write failed (no sufficient working area),
625 * we use normal (slow) single dword accesses */
626 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
627 }
628 else if (retval == ERROR_FLASH_OPERATION_FAILED)
629 {
630 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
631 return ERROR_FLASH_OPERATION_FAILED;
632 }
633 }
634 else
635 {
636 buffer += words_remaining * 2;
637 address += words_remaining * 2;
638 words_remaining = 0;
639 }
640 }
641
642 while (words_remaining > 0)
643 {
644 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
645 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
646
647 status = stm32x_wait_status_busy(bank, 5);
648
649 if( status & FLASH_WRPRTERR )
650 return ERROR_FLASH_OPERATION_FAILED;
651 if( status & FLASH_PGERR )
652 return ERROR_FLASH_OPERATION_FAILED;
653
654 bytes_written += 2;
655 words_remaining--;
656 address += 2;
657 }
658
659 if (bytes_remaining)
660 {
661 u8 last_halfword[2] = {0xff, 0xff};
662 int i = 0;
663
664 while(bytes_remaining > 0)
665 {
666 last_halfword[i++] = *(buffer + bytes_written);
667 bytes_remaining--;
668 bytes_written++;
669 }
670
671 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
672 target_write_u16(target, address, *(u16*)last_halfword);
673
674 status = stm32x_wait_status_busy(bank, 5);
675
676 if( status & FLASH_WRPRTERR )
677 return ERROR_FLASH_OPERATION_FAILED;
678 if( status & FLASH_PGERR )
679 return ERROR_FLASH_OPERATION_FAILED;
680 }
681
682 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
683
684 return ERROR_OK;
685 }
686
687 int stm32x_probe(struct flash_bank_s *bank)
688 {
689 target_t *target = bank->target;
690 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
691 int i;
692 u16 num_pages;
693 u32 device_id;
694 int page_size;
695
696 if (bank->target->state != TARGET_HALTED)
697 {
698 LOG_ERROR("Target not halted");
699 return ERROR_TARGET_NOT_HALTED;
700 }
701
702 stm32x_info->probed = 0;
703
704 /* read stm32 device id register */
705 target_read_u32(target, 0xE0042000, &device_id);
706 LOG_INFO( "device id = 0x%08x", device_id );
707
708 /* get flash size from target */
709 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
710 {
711 /* failed reading flash size, default to max target family */
712 num_pages = 0xffff;
713 }
714
715 if ((device_id & 0x7ff) == 0x410)
716 {
717 /* medium density - we have 1k pages
718 * 4 pages for a protection area */
719 page_size = 1024;
720 stm32x_info->ppage_size = 4;
721
722 /* check for early silicon */
723 if (num_pages == 0xffff)
724 {
725 /* number of sectors incorrect on revA */
726 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
727 num_pages = 128;
728 }
729 }
730 else if ((device_id & 0x7ff) == 0x412)
731 {
732 /* low density - we have 1k pages
733 * 4 pages for a protection area */
734 page_size = 1024;
735 stm32x_info->ppage_size = 4;
736
737 /* check for early silicon */
738 if (num_pages == 0xffff)
739 {
740 /* number of sectors incorrect on revA */
741 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 32k flash" );
742 num_pages = 32;
743 }
744 }
745 else if ((device_id & 0x7ff) == 0x414)
746 {
747 /* high density - we have 2k pages
748 * 2 pages for a protection area */
749 page_size = 2048;
750 stm32x_info->ppage_size = 2;
751
752 /* check for early silicon */
753 if (num_pages == 0xffff)
754 {
755 /* number of sectors incorrect on revZ */
756 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
757 num_pages = 512;
758 }
759 }
760 else if ((device_id & 0x7ff) == 0x418)
761 {
762 /* connectivity line density - we have 1k pages
763 * 4 pages for a protection area */
764 page_size = 1024;
765 stm32x_info->ppage_size = 4;
766
767 /* check for early silicon */
768 if (num_pages == 0xffff)
769 {
770 /* number of sectors incorrect on revZ */
771 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 256k flash" );
772 num_pages = 256;
773 }
774 }
775 else
776 {
777 LOG_WARNING( "Cannot identify target as a STM32 family." );
778 return ERROR_FLASH_OPERATION_FAILED;
779 }
780
781 LOG_INFO( "flash size = %dkbytes", num_pages );
782
783 /* calculate numbers of pages */
784 num_pages /= (page_size / 1024);
785
786 bank->base = 0x08000000;
787 bank->size = (num_pages * page_size);
788 bank->num_sectors = num_pages;
789 bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
790
791 for (i = 0; i < num_pages; i++)
792 {
793 bank->sectors[i].offset = i * page_size;
794 bank->sectors[i].size = page_size;
795 bank->sectors[i].is_erased = -1;
796 bank->sectors[i].is_protected = 1;
797 }
798
799 stm32x_info->probed = 1;
800
801 return ERROR_OK;
802 }
803
804 int stm32x_auto_probe(struct flash_bank_s *bank)
805 {
806 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
807 if (stm32x_info->probed)
808 return ERROR_OK;
809 return stm32x_probe(bank);
810 }
811
812 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
813 {
814 return ERROR_OK;
815 }
816
817 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
818 {
819 target_t *target = bank->target;
820 u32 device_id;
821 int printed;
822
823 /* read stm32 device id register */
824 target_read_u32(target, 0xE0042000, &device_id);
825
826 if ((device_id & 0x7ff) == 0x410)
827 {
828 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
829 buf += printed;
830 buf_size -= printed;
831
832 switch(device_id >> 16)
833 {
834 case 0x0000:
835 snprintf(buf, buf_size, "A");
836 break;
837
838 case 0x2000:
839 snprintf(buf, buf_size, "B");
840 break;
841
842 case 0x2001:
843 snprintf(buf, buf_size, "Z");
844 break;
845
846 case 0x2003:
847 snprintf(buf, buf_size, "Y");
848 break;
849
850 default:
851 snprintf(buf, buf_size, "unknown");
852 break;
853 }
854 }
855 else if ((device_id & 0x7ff) == 0x412)
856 {
857 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
858 buf += printed;
859 buf_size -= printed;
860
861 switch(device_id >> 16)
862 {
863 case 0x1000:
864 snprintf(buf, buf_size, "A");
865 break;
866
867 default:
868 snprintf(buf, buf_size, "unknown");
869 break;
870 }
871 }
872 else if ((device_id & 0x7ff) == 0x414)
873 {
874 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
875 buf += printed;
876 buf_size -= printed;
877
878 switch(device_id >> 16)
879 {
880 case 0x1000:
881 snprintf(buf, buf_size, "A");
882 break;
883
884 case 0x1001:
885 snprintf(buf, buf_size, "Z");
886 break;
887
888 default:
889 snprintf(buf, buf_size, "unknown");
890 break;
891 }
892 }
893 else if ((device_id & 0x7ff) == 0x418)
894 {
895 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
896 buf += printed;
897 buf_size -= printed;
898
899 switch(device_id >> 16)
900 {
901 case 0x1000:
902 snprintf(buf, buf_size, "A");
903 break;
904
905 default:
906 snprintf(buf, buf_size, "unknown");
907 break;
908 }
909 }
910 else
911 {
912 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
913 return ERROR_FLASH_OPERATION_FAILED;
914 }
915
916 return ERROR_OK;
917 }
918
919 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
920 {
921 flash_bank_t *bank;
922 target_t *target = NULL;
923 stm32x_flash_bank_t *stm32x_info = NULL;
924
925 if (argc < 1)
926 {
927 command_print(cmd_ctx, "stm32x lock <bank>");
928 return ERROR_OK;
929 }
930
931 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
932 if (!bank)
933 {
934 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
935 return ERROR_OK;
936 }
937
938 stm32x_info = bank->driver_priv;
939
940 target = bank->target;
941
942 if (target->state != TARGET_HALTED)
943 {
944 LOG_ERROR("Target not halted");
945 return ERROR_TARGET_NOT_HALTED;
946 }
947
948 if (stm32x_erase_options(bank) != ERROR_OK)
949 {
950 command_print(cmd_ctx, "stm32x failed to erase options");
951 return ERROR_OK;
952 }
953
954 /* set readout protection */
955 stm32x_info->option_bytes.RDP = 0;
956
957 if (stm32x_write_options(bank) != ERROR_OK)
958 {
959 command_print(cmd_ctx, "stm32x failed to lock device");
960 return ERROR_OK;
961 }
962
963 command_print(cmd_ctx, "stm32x locked");
964
965 return ERROR_OK;
966 }
967
968 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
969 {
970 flash_bank_t *bank;
971 target_t *target = NULL;
972 stm32x_flash_bank_t *stm32x_info = NULL;
973
974 if (argc < 1)
975 {
976 command_print(cmd_ctx, "stm32x unlock <bank>");
977 return ERROR_OK;
978 }
979
980 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
981 if (!bank)
982 {
983 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
984 return ERROR_OK;
985 }
986
987 stm32x_info = bank->driver_priv;
988
989 target = bank->target;
990
991 if (target->state != TARGET_HALTED)
992 {
993 LOG_ERROR("Target not halted");
994 return ERROR_TARGET_NOT_HALTED;
995 }
996
997 if (stm32x_erase_options(bank) != ERROR_OK)
998 {
999 command_print(cmd_ctx, "stm32x failed to unlock device");
1000 return ERROR_OK;
1001 }
1002
1003 if (stm32x_write_options(bank) != ERROR_OK)
1004 {
1005 command_print(cmd_ctx, "stm32x failed to lock device");
1006 return ERROR_OK;
1007 }
1008
1009 command_print(cmd_ctx, "stm32x unlocked");
1010
1011 return ERROR_OK;
1012 }
1013
1014 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1015 {
1016 flash_bank_t *bank;
1017 u32 optionbyte;
1018 target_t *target = NULL;
1019 stm32x_flash_bank_t *stm32x_info = NULL;
1020
1021 if (argc < 1)
1022 {
1023 command_print(cmd_ctx, "stm32x options_read <bank>");
1024 return ERROR_OK;
1025 }
1026
1027 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1028 if (!bank)
1029 {
1030 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1031 return ERROR_OK;
1032 }
1033
1034 stm32x_info = bank->driver_priv;
1035
1036 target = bank->target;
1037
1038 if (target->state != TARGET_HALTED)
1039 {
1040 LOG_ERROR("Target not halted");
1041 return ERROR_TARGET_NOT_HALTED;
1042 }
1043
1044 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1045 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
1046
1047 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
1048 command_print(cmd_ctx, "Option Byte Complement Error");
1049
1050 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
1051 command_print(cmd_ctx, "Readout Protection On");
1052 else
1053 command_print(cmd_ctx, "Readout Protection Off");
1054
1055 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
1056 command_print(cmd_ctx, "Software Watchdog");
1057 else
1058 command_print(cmd_ctx, "Hardware Watchdog");
1059
1060 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
1061 command_print(cmd_ctx, "Stop: No reset generated");
1062 else
1063 command_print(cmd_ctx, "Stop: Reset generated");
1064
1065 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
1066 command_print(cmd_ctx, "Standby: No reset generated");
1067 else
1068 command_print(cmd_ctx, "Standby: Reset generated");
1069
1070 return ERROR_OK;
1071 }
1072
1073 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1074 {
1075 flash_bank_t *bank;
1076 target_t *target = NULL;
1077 stm32x_flash_bank_t *stm32x_info = NULL;
1078 u16 optionbyte = 0xF8;
1079
1080 if (argc < 4)
1081 {
1082 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
1083 return ERROR_OK;
1084 }
1085
1086 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1087 if (!bank)
1088 {
1089 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1090 return ERROR_OK;
1091 }
1092
1093 stm32x_info = bank->driver_priv;
1094
1095 target = bank->target;
1096
1097 if (target->state != TARGET_HALTED)
1098 {
1099 LOG_ERROR("Target not halted");
1100 return ERROR_TARGET_NOT_HALTED;
1101 }
1102
1103 if (strcmp(args[1], "SWWDG") == 0)
1104 {
1105 optionbyte |= (1<<0);
1106 }
1107 else
1108 {
1109 optionbyte &= ~(1<<0);
1110 }
1111
1112 if (strcmp(args[2], "NORSTSTNDBY") == 0)
1113 {
1114 optionbyte |= (1<<1);
1115 }
1116 else
1117 {
1118 optionbyte &= ~(1<<1);
1119 }
1120
1121 if (strcmp(args[3], "NORSTSTOP") == 0)
1122 {
1123 optionbyte |= (1<<2);
1124 }
1125 else
1126 {
1127 optionbyte &= ~(1<<2);
1128 }
1129
1130 if (stm32x_erase_options(bank) != ERROR_OK)
1131 {
1132 command_print(cmd_ctx, "stm32x failed to erase options");
1133 return ERROR_OK;
1134 }
1135
1136 stm32x_info->option_bytes.user_options = optionbyte;
1137
1138 if (stm32x_write_options(bank) != ERROR_OK)
1139 {
1140 command_print(cmd_ctx, "stm32x failed to write options");
1141 return ERROR_OK;
1142 }
1143
1144 command_print(cmd_ctx, "stm32x write options complete");
1145
1146 return ERROR_OK;
1147 }
1148
1149 int stm32x_mass_erase(struct flash_bank_s *bank)
1150 {
1151 target_t *target = bank->target;
1152 u32 status;
1153
1154 if (target->state != TARGET_HALTED)
1155 {
1156 LOG_ERROR("Target not halted");
1157 return ERROR_TARGET_NOT_HALTED;
1158 }
1159
1160 /* unlock option flash registers */
1161 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1162 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1163
1164 /* mass erase flash memory */
1165 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1166 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
1167
1168 status = stm32x_wait_status_busy(bank, 10);
1169
1170 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1171
1172 if( status & FLASH_WRPRTERR )
1173 {
1174 LOG_ERROR("stm32x device protected");
1175 return ERROR_OK;
1176 }
1177
1178 if( status & FLASH_PGERR )
1179 {
1180 LOG_ERROR("stm32x device programming failed");
1181 return ERROR_OK;
1182 }
1183
1184 return ERROR_OK;
1185 }
1186
1187 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1188 {
1189 flash_bank_t *bank;
1190 int i;
1191
1192 if (argc < 1)
1193 {
1194 command_print(cmd_ctx, "stm32x mass_erase <bank>");
1195 return ERROR_OK;
1196 }
1197
1198 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1199 if (!bank)
1200 {
1201 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1202 return ERROR_OK;
1203 }
1204
1205 if (stm32x_mass_erase(bank) == ERROR_OK)
1206 {
1207 /* set all sectors as erased */
1208 for (i = 0; i < bank->num_sectors; i++)
1209 {
1210 bank->sectors[i].is_erased = 1;
1211 }
1212
1213 command_print(cmd_ctx, "stm32x mass erase complete");
1214 }
1215 else
1216 {
1217 command_print(cmd_ctx, "stm32x mass erase failed");
1218 }
1219
1220 return ERROR_OK;
1221 }
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