1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
37 int stm32x_register_commands(struct command_context_s
*cmd_ctx
);
38 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
39 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
);
40 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
41 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
42 int stm32x_probe(struct flash_bank_s
*bank
);
43 int stm32x_auto_probe(struct flash_bank_s
*bank
);
44 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int stm32x_protect_check(struct flash_bank_s
*bank
);
46 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
48 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 flash_driver_t stm32x_flash
=
57 .register_commands
= stm32x_register_commands
,
58 .flash_bank_command
= stm32x_flash_bank_command
,
59 .erase
= stm32x_erase
,
60 .protect
= stm32x_protect
,
61 .write
= stm32x_write
,
62 .probe
= stm32x_probe
,
63 .auto_probe
= stm32x_auto_probe
,
64 .erase_check
= default_flash_blank_check
,
65 .protect_check
= stm32x_protect_check
,
69 int stm32x_register_commands(struct command_context_s
*cmd_ctx
)
71 command_t
*stm32x_cmd
= register_command(cmd_ctx
, NULL
, "stm32x", NULL
, COMMAND_ANY
, "stm32x flash specific commands");
73 register_command(cmd_ctx
, stm32x_cmd
, "lock", stm32x_handle_lock_command
, COMMAND_EXEC
,
75 register_command(cmd_ctx
, stm32x_cmd
, "unlock", stm32x_handle_unlock_command
, COMMAND_EXEC
,
76 "unlock protected device");
77 register_command(cmd_ctx
, stm32x_cmd
, "mass_erase", stm32x_handle_mass_erase_command
, COMMAND_EXEC
,
79 register_command(cmd_ctx
, stm32x_cmd
, "options_read", stm32x_handle_options_read_command
, COMMAND_EXEC
,
80 "read device option bytes");
81 register_command(cmd_ctx
, stm32x_cmd
, "options_write", stm32x_handle_options_write_command
, COMMAND_EXEC
,
82 "write device option bytes");
86 /* flash bank stm32x <base> <size> 0 0 <target#>
88 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
90 stm32x_flash_bank_t
*stm32x_info
;
94 LOG_WARNING("incomplete flash_bank stm32x configuration");
95 return ERROR_FLASH_BANK_INVALID
;
98 stm32x_info
= malloc(sizeof(stm32x_flash_bank_t
));
99 bank
->driver_priv
= stm32x_info
;
101 stm32x_info
->write_algorithm
= NULL
;
102 stm32x_info
->probed
= 0;
107 u32
stm32x_get_flash_status(flash_bank_t
*bank
)
109 target_t
*target
= bank
->target
;
112 target_read_u32(target
, STM32_FLASH_SR
, &status
);
117 u32
stm32x_wait_status_busy(flash_bank_t
*bank
, int timeout
)
121 /* wait for busy to clear */
122 while (((status
= stm32x_get_flash_status(bank
)) & FLASH_BSY
) && (timeout
-- > 0))
124 LOG_DEBUG("status: 0x%x", status
);
131 int stm32x_read_options(struct flash_bank_s
*bank
)
134 stm32x_flash_bank_t
*stm32x_info
= NULL
;
135 target_t
*target
= bank
->target
;
137 stm32x_info
= bank
->driver_priv
;
139 /* read current option bytes */
140 target_read_u32(target
, STM32_FLASH_OBR
, &optiondata
);
142 stm32x_info
->option_bytes
.user_options
= (u16
)0xFFF8|((optiondata
>> 2) & 0x07);
143 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
145 if (optiondata
& (1 << OPT_READOUT
))
146 LOG_INFO("Device Security Bit Set");
148 /* each bit refers to a 4bank protection */
149 target_read_u32(target
, STM32_FLASH_WRPR
, &optiondata
);
151 stm32x_info
->option_bytes
.protection
[0] = (u16
)optiondata
;
152 stm32x_info
->option_bytes
.protection
[1] = (u16
)(optiondata
>> 8);
153 stm32x_info
->option_bytes
.protection
[2] = (u16
)(optiondata
>> 16);
154 stm32x_info
->option_bytes
.protection
[3] = (u16
)(optiondata
>> 24);
159 int stm32x_erase_options(struct flash_bank_s
*bank
)
161 stm32x_flash_bank_t
*stm32x_info
= NULL
;
162 target_t
*target
= bank
->target
;
165 stm32x_info
= bank
->driver_priv
;
167 /* read current options */
168 stm32x_read_options(bank
);
170 /* unlock flash registers */
171 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
172 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
174 /* unlock option flash registers */
175 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
176 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
178 /* erase option bytes */
179 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
180 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
182 status
= stm32x_wait_status_busy(bank
, 10);
184 if( status
& FLASH_WRPRTERR
)
185 return ERROR_FLASH_OPERATION_FAILED
;
186 if( status
& FLASH_PGERR
)
187 return ERROR_FLASH_OPERATION_FAILED
;
189 /* clear readout protection and complementary option bytes
190 * this will also force a device unlock if set */
191 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
196 int stm32x_write_options(struct flash_bank_s
*bank
)
198 stm32x_flash_bank_t
*stm32x_info
= NULL
;
199 target_t
*target
= bank
->target
;
202 stm32x_info
= bank
->driver_priv
;
204 /* unlock flash registers */
205 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
206 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
208 /* unlock option flash registers */
209 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
210 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
212 /* program option bytes */
213 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
215 /* write user option byte */
216 target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
218 status
= stm32x_wait_status_busy(bank
, 10);
220 if( status
& FLASH_WRPRTERR
)
221 return ERROR_FLASH_OPERATION_FAILED
;
222 if( status
& FLASH_PGERR
)
223 return ERROR_FLASH_OPERATION_FAILED
;
225 /* write protection byte 1 */
226 target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
228 status
= stm32x_wait_status_busy(bank
, 10);
230 if( status
& FLASH_WRPRTERR
)
231 return ERROR_FLASH_OPERATION_FAILED
;
232 if( status
& FLASH_PGERR
)
233 return ERROR_FLASH_OPERATION_FAILED
;
235 /* write protection byte 2 */
236 target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
238 status
= stm32x_wait_status_busy(bank
, 10);
240 if( status
& FLASH_WRPRTERR
)
241 return ERROR_FLASH_OPERATION_FAILED
;
242 if( status
& FLASH_PGERR
)
243 return ERROR_FLASH_OPERATION_FAILED
;
245 /* write protection byte 3 */
246 target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
248 status
= stm32x_wait_status_busy(bank
, 10);
250 if( status
& FLASH_WRPRTERR
)
251 return ERROR_FLASH_OPERATION_FAILED
;
252 if( status
& FLASH_PGERR
)
253 return ERROR_FLASH_OPERATION_FAILED
;
255 /* write protection byte 4 */
256 target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
258 status
= stm32x_wait_status_busy(bank
, 10);
260 if( status
& FLASH_WRPRTERR
)
261 return ERROR_FLASH_OPERATION_FAILED
;
262 if( status
& FLASH_PGERR
)
263 return ERROR_FLASH_OPERATION_FAILED
;
265 /* write readout protection bit */
266 target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
268 status
= stm32x_wait_status_busy(bank
, 10);
270 if( status
& FLASH_WRPRTERR
)
271 return ERROR_FLASH_OPERATION_FAILED
;
272 if( status
& FLASH_PGERR
)
273 return ERROR_FLASH_OPERATION_FAILED
;
275 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
280 int stm32x_protect_check(struct flash_bank_s
*bank
)
282 target_t
*target
= bank
->target
;
283 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
289 if (target
->state
!= TARGET_HALTED
)
291 return ERROR_TARGET_NOT_HALTED
;
294 /* medium density - each bit refers to a 4bank protection
295 * high density - each bit refers to a 2bank protection */
296 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
298 /* medium density - each protection bit is for 4 * 1K pages
299 * high density - each protection bit is for 2 * 2K pages */
300 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
302 for (i
= 0; i
< num_bits
; i
++)
306 if( protection
& (1 << i
))
309 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
310 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
316 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
)
318 target_t
*target
= bank
->target
;
323 if (bank
->target
->state
!= TARGET_HALTED
)
325 return ERROR_TARGET_NOT_HALTED
;
328 /* unlock flash registers */
329 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
330 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
332 for (i
= first
; i
<= last
; i
++)
334 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
335 target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
336 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
|FLASH_STRT
);
338 status
= stm32x_wait_status_busy(bank
, 10);
340 if( status
& FLASH_WRPRTERR
)
341 return ERROR_FLASH_OPERATION_FAILED
;
342 if( status
& FLASH_PGERR
)
343 return ERROR_FLASH_OPERATION_FAILED
;
344 bank
->sectors
[i
].is_erased
= 1;
347 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
352 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
354 stm32x_flash_bank_t
*stm32x_info
= NULL
;
355 target_t
*target
= bank
->target
;
356 u16 prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
361 stm32x_info
= bank
->driver_priv
;
363 if (target
->state
!= TARGET_HALTED
)
365 return ERROR_TARGET_NOT_HALTED
;
368 if ((first
&& (first
% stm32x_info
->ppage_size
)) || ((last
+ 1) && (last
+ 1) % stm32x_info
->ppage_size
))
370 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info
->ppage_size
);
371 return ERROR_FLASH_SECTOR_INVALID
;
374 /* medium density - each bit refers to a 4bank protection
375 * high density - each bit refers to a 2bank protection */
376 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
378 prot_reg
[0] = (u16
)protection
;
379 prot_reg
[1] = (u16
)(protection
>> 8);
380 prot_reg
[2] = (u16
)(protection
>> 16);
381 prot_reg
[3] = (u16
)(protection
>> 24);
383 for (i
= first
; i
<= last
; i
++)
385 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
386 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
389 prot_reg
[reg
] &= ~(1 << bit
);
391 prot_reg
[reg
] |= (1 << bit
);
394 if ((status
= stm32x_erase_options(bank
)) != ERROR_OK
)
397 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
398 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
399 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
400 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
402 return stm32x_write_options(bank
);
405 int stm32x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
407 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
408 target_t
*target
= bank
->target
;
409 u32 buffer_size
= 8192;
410 working_area_t
*source
;
411 u32 address
= bank
->base
+ offset
;
412 reg_param_t reg_params
[4];
413 armv7m_algorithm_t armv7m_info
;
414 int retval
= ERROR_OK
;
416 u8 stm32x_flash_write_code
[] = {
418 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
419 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
420 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
421 0x23, 0x60, /* str r3, [r4, #0] */
422 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
423 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
425 0x2B, 0x68, /* ldr r3, [r5, #0] */
426 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
427 0xFB, 0xD0, /* beq busy */
428 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
429 0x01, 0xD1, /* bne exit */
430 0x01, 0x3A, /* subs r2, r2, #1 */
431 0xED, 0xD1, /* bne write */
433 0xFE, 0xE7, /* b exit */
434 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
435 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
438 /* flash write code */
439 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
), &stm32x_info
->write_algorithm
) != ERROR_OK
)
441 LOG_WARNING("no working area available, can't do block memory writes");
442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
445 if ((retval
=target_write_buffer(target
, stm32x_info
->write_algorithm
->address
, sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
))!=ERROR_OK
)
449 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
452 if (buffer_size
<= 256)
454 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
455 if (stm32x_info
->write_algorithm
)
456 target_free_working_area(target
, stm32x_info
->write_algorithm
);
458 LOG_WARNING("no large enough working area available, can't do block memory writes");
459 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
463 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
464 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
466 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
467 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
468 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
469 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
473 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
475 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
))!=ERROR_OK
)
478 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
479 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
480 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
482 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 4, reg_params
, stm32x_info
->write_algorithm
->address
, \
483 stm32x_info
->write_algorithm
->address
+ (sizeof(stm32x_flash_write_code
) - 10), 10000, &armv7m_info
)) != ERROR_OK
)
485 LOG_ERROR("error executing stm32x flash write algorithm");
489 if (buf_get_u32(reg_params
[3].value
, 0, 32) & 0x14)
491 retval
= ERROR_FLASH_OPERATION_FAILED
;
495 buffer
+= thisrun_count
* 2;
496 address
+= thisrun_count
* 2;
497 count
-= thisrun_count
;
500 target_free_working_area(target
, source
);
501 target_free_working_area(target
, stm32x_info
->write_algorithm
);
503 destroy_reg_param(®_params
[0]);
504 destroy_reg_param(®_params
[1]);
505 destroy_reg_param(®_params
[2]);
506 destroy_reg_param(®_params
[3]);
511 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
513 target_t
*target
= bank
->target
;
514 u32 words_remaining
= (count
/ 2);
515 u32 bytes_remaining
= (count
& 0x00000001);
516 u32 address
= bank
->base
+ offset
;
517 u32 bytes_written
= 0;
521 if (bank
->target
->state
!= TARGET_HALTED
)
523 return ERROR_TARGET_NOT_HALTED
;
528 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
529 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
532 /* unlock flash registers */
533 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
534 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
536 /* multiple half words (2-byte) to be programmed? */
537 if (words_remaining
> 0)
539 /* try using a block write */
540 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
542 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
544 /* if block write failed (no sufficient working area),
545 * we use normal (slow) single dword accesses */
546 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
548 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
550 LOG_ERROR("flash writing failed with error code: 0x%x", retval
);
551 return ERROR_FLASH_OPERATION_FAILED
;
556 buffer
+= words_remaining
* 2;
557 address
+= words_remaining
* 2;
562 while (words_remaining
> 0)
564 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
565 target_write_u16(target
, address
, *(u16
*)(buffer
+ bytes_written
));
567 status
= stm32x_wait_status_busy(bank
, 5);
569 if( status
& FLASH_WRPRTERR
)
570 return ERROR_FLASH_OPERATION_FAILED
;
571 if( status
& FLASH_PGERR
)
572 return ERROR_FLASH_OPERATION_FAILED
;
581 u8 last_halfword
[2] = {0xff, 0xff};
584 while(bytes_remaining
> 0)
586 last_halfword
[i
++] = *(buffer
+ bytes_written
);
591 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
592 target_write_u16(target
, address
, *(u16
*)last_halfword
);
594 status
= stm32x_wait_status_busy(bank
, 5);
596 if( status
& FLASH_WRPRTERR
)
597 return ERROR_FLASH_OPERATION_FAILED
;
598 if( status
& FLASH_PGERR
)
599 return ERROR_FLASH_OPERATION_FAILED
;
602 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
607 int stm32x_probe(struct flash_bank_s
*bank
)
609 target_t
*target
= bank
->target
;
610 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
616 if (bank
->target
->state
!= TARGET_HALTED
)
618 return ERROR_TARGET_NOT_HALTED
;
621 stm32x_info
->probed
= 0;
623 /* read stm32 device id register */
624 target_read_u32(target
, 0xE0042000, &device_id
);
625 LOG_INFO( "device id = 0x%08x", device_id
);
627 switch (device_id
& 0x7ff)
630 /* medium density - we have 1k pages
631 * 4 pages for a protection area */
633 stm32x_info
->ppage_size
= 4;
637 /* high density - we have 2k pages
638 * 2 pages for a protection area */
640 stm32x_info
->ppage_size
= 2;
644 LOG_WARNING( "Cannot identify target as a STM32 family." );
645 return ERROR_FLASH_OPERATION_FAILED
;
648 /* get flash size from target */
649 if (target_read_u16(target
, 0x1FFFF7E0, &num_pages
) != ERROR_OK
)
651 /* failed reading flash size, default to 128k */
652 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
656 /* check for early silicon rev A */
657 if ((device_id
>> 16) == 0 )
659 /* number of sectors incorrect on revA */
660 LOG_WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
664 LOG_INFO( "flash size = %dkbytes", num_pages
);
666 /* calculate numbers of pages */
667 num_pages
/= (page_size
- 1024);
669 bank
->base
= 0x08000000;
670 bank
->size
= (num_pages
* page_size
);
671 bank
->num_sectors
= num_pages
;
672 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_pages
);
674 for (i
= 0; i
< num_pages
; i
++)
676 bank
->sectors
[i
].offset
= i
* page_size
;
677 bank
->sectors
[i
].size
= page_size
;
678 bank
->sectors
[i
].is_erased
= -1;
679 bank
->sectors
[i
].is_protected
= 1;
682 stm32x_info
->probed
= 1;
687 int stm32x_auto_probe(struct flash_bank_s
*bank
)
689 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
690 if (stm32x_info
->probed
)
692 return stm32x_probe(bank
);
695 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
700 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
702 snprintf(buf
, buf_size
, "stm32x flash driver info" );
706 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
709 target_t
*target
= NULL
;
710 stm32x_flash_bank_t
*stm32x_info
= NULL
;
714 command_print(cmd_ctx
, "stm32x lock <bank>");
718 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
721 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
725 stm32x_info
= bank
->driver_priv
;
727 target
= bank
->target
;
729 if (target
->state
!= TARGET_HALTED
)
731 return ERROR_TARGET_NOT_HALTED
;
734 if (stm32x_erase_options(bank
) != ERROR_OK
)
736 command_print(cmd_ctx
, "stm32x failed to erase options");
740 /* set readout protection */
741 stm32x_info
->option_bytes
.RDP
= 0;
743 if (stm32x_write_options(bank
) != ERROR_OK
)
745 command_print(cmd_ctx
, "stm32x failed to lock device");
749 command_print(cmd_ctx
, "stm32x locked");
754 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
757 target_t
*target
= NULL
;
758 stm32x_flash_bank_t
*stm32x_info
= NULL
;
762 command_print(cmd_ctx
, "stm32x unlock <bank>");
766 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
769 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
773 stm32x_info
= bank
->driver_priv
;
775 target
= bank
->target
;
777 if (target
->state
!= TARGET_HALTED
)
779 return ERROR_TARGET_NOT_HALTED
;
782 if (stm32x_erase_options(bank
) != ERROR_OK
)
784 command_print(cmd_ctx
, "stm32x failed to unlock device");
788 if (stm32x_write_options(bank
) != ERROR_OK
)
790 command_print(cmd_ctx
, "stm32x failed to lock device");
794 command_print(cmd_ctx
, "stm32x unlocked");
799 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
803 target_t
*target
= NULL
;
804 stm32x_flash_bank_t
*stm32x_info
= NULL
;
808 command_print(cmd_ctx
, "stm32x options_read <bank>");
812 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
815 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
819 stm32x_info
= bank
->driver_priv
;
821 target
= bank
->target
;
823 if (target
->state
!= TARGET_HALTED
)
825 return ERROR_TARGET_NOT_HALTED
;
828 target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
829 command_print(cmd_ctx
, "Option Byte: 0x%x", optionbyte
);
831 if (buf_get_u32((u8
*)&optionbyte
, OPT_ERROR
, 1))
832 command_print(cmd_ctx
, "Option Byte Complement Error");
834 if (buf_get_u32((u8
*)&optionbyte
, OPT_READOUT
, 1))
835 command_print(cmd_ctx
, "Readout Protection On");
837 command_print(cmd_ctx
, "Readout Protection Off");
839 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDWDGSW
, 1))
840 command_print(cmd_ctx
, "Software Watchdog");
842 command_print(cmd_ctx
, "Hardware Watchdog");
844 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTOP
, 1))
845 command_print(cmd_ctx
, "Stop: No reset generated");
847 command_print(cmd_ctx
, "Stop: Reset generated");
849 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
850 command_print(cmd_ctx
, "Standby: No reset generated");
852 command_print(cmd_ctx
, "Standby: Reset generated");
857 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
860 target_t
*target
= NULL
;
861 stm32x_flash_bank_t
*stm32x_info
= NULL
;
862 u16 optionbyte
= 0xF8;
866 command_print(cmd_ctx
, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
870 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
873 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
877 stm32x_info
= bank
->driver_priv
;
879 target
= bank
->target
;
881 if (target
->state
!= TARGET_HALTED
)
883 return ERROR_TARGET_NOT_HALTED
;
886 if (strcmp(args
[1], "SWWDG") == 0)
888 optionbyte
|= (1<<0);
892 optionbyte
&= ~(1<<0);
895 if (strcmp(args
[2], "NORSTSTNDBY") == 0)
897 optionbyte
|= (1<<1);
901 optionbyte
&= ~(1<<1);
904 if (strcmp(args
[3], "NORSTSTOP") == 0)
906 optionbyte
|= (1<<2);
910 optionbyte
&= ~(1<<2);
913 if (stm32x_erase_options(bank
) != ERROR_OK
)
915 command_print(cmd_ctx
, "stm32x failed to erase options");
919 stm32x_info
->option_bytes
.user_options
= optionbyte
;
921 if (stm32x_write_options(bank
) != ERROR_OK
)
923 command_print(cmd_ctx
, "stm32x failed to write options");
927 command_print(cmd_ctx
, "stm32x write options complete");
932 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
934 target_t
*target
= NULL
;
935 stm32x_flash_bank_t
*stm32x_info
= NULL
;
942 command_print(cmd_ctx
, "stm32x mass_erase <bank>");
946 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
949 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
953 stm32x_info
= bank
->driver_priv
;
955 target
= bank
->target
;
957 if (target
->state
!= TARGET_HALTED
)
959 return ERROR_TARGET_NOT_HALTED
;
962 /* unlock option flash registers */
963 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
964 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
966 /* mass erase flash memory */
967 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
968 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
|FLASH_STRT
);
970 status
= stm32x_wait_status_busy(bank
, 10);
972 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
974 if( status
& FLASH_WRPRTERR
)
976 command_print(cmd_ctx
, "stm32x device protected");
980 if( status
& FLASH_PGERR
)
982 command_print(cmd_ctx
, "stm32x device programming failed");
986 /* set all sectors as erased */
987 for (i
= 0; i
< bank
->num_sectors
; i
++)
989 bank
->sectors
[i
].is_erased
= 1;
992 command_print(cmd_ctx
, "stm32x mass erase complete");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)