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- stm32 flash driver correctly handles early silicon
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "stm32x.h"
27 #include "flash.h"
28 #include "target.h"
29 #include "log.h"
30 #include "armv7m.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
33
34 #include <stdlib.h>
35 #include <string.h>
36
37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
42 int stm32x_probe(struct flash_bank_s *bank);
43 int stm32x_auto_probe(struct flash_bank_s *bank);
44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int stm32x_protect_check(struct flash_bank_s *bank);
46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
47
48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int stm32x_mass_erase(struct flash_bank_s *bank);
54
55 flash_driver_t stm32x_flash =
56 {
57 .name = "stm32x",
58 .register_commands = stm32x_register_commands,
59 .flash_bank_command = stm32x_flash_bank_command,
60 .erase = stm32x_erase,
61 .protect = stm32x_protect,
62 .write = stm32x_write,
63 .probe = stm32x_probe,
64 .auto_probe = stm32x_auto_probe,
65 .erase_check = default_flash_mem_blank_check,
66 .protect_check = stm32x_protect_check,
67 .info = stm32x_info
68 };
69
70 int stm32x_register_commands(struct command_context_s *cmd_ctx)
71 {
72 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
73
74 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
75 "lock device");
76 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
77 "unlock protected device");
78 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
79 "mass erase device");
80 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
81 "read device option bytes");
82 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
83 "write device option bytes");
84 return ERROR_OK;
85 }
86
87 /* flash bank stm32x <base> <size> 0 0 <target#>
88 */
89 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
90 {
91 stm32x_flash_bank_t *stm32x_info;
92
93 if (argc < 6)
94 {
95 LOG_WARNING("incomplete flash_bank stm32x configuration");
96 return ERROR_FLASH_BANK_INVALID;
97 }
98
99 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
100 bank->driver_priv = stm32x_info;
101
102 stm32x_info->write_algorithm = NULL;
103 stm32x_info->probed = 0;
104
105 return ERROR_OK;
106 }
107
108 u32 stm32x_get_flash_status(flash_bank_t *bank)
109 {
110 target_t *target = bank->target;
111 u32 status;
112
113 target_read_u32(target, STM32_FLASH_SR, &status);
114
115 return status;
116 }
117
118 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
119 {
120 u32 status;
121
122 /* wait for busy to clear */
123 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
124 {
125 LOG_DEBUG("status: 0x%x", status);
126 usleep(1000);
127 }
128
129 return status;
130 }
131
132 int stm32x_read_options(struct flash_bank_s *bank)
133 {
134 u32 optiondata;
135 stm32x_flash_bank_t *stm32x_info = NULL;
136 target_t *target = bank->target;
137
138 stm32x_info = bank->driver_priv;
139
140 /* read current option bytes */
141 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
142
143 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
144 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
145
146 if (optiondata & (1 << OPT_READOUT))
147 LOG_INFO("Device Security Bit Set");
148
149 /* each bit refers to a 4bank protection */
150 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
151
152 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
153 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
154 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
155 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
156
157 return ERROR_OK;
158 }
159
160 int stm32x_erase_options(struct flash_bank_s *bank)
161 {
162 stm32x_flash_bank_t *stm32x_info = NULL;
163 target_t *target = bank->target;
164 u32 status;
165
166 stm32x_info = bank->driver_priv;
167
168 /* read current options */
169 stm32x_read_options(bank);
170
171 /* unlock flash registers */
172 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
173 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
174
175 /* unlock option flash registers */
176 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
177 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
178
179 /* erase option bytes */
180 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
181 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
182
183 status = stm32x_wait_status_busy(bank, 10);
184
185 if( status & FLASH_WRPRTERR )
186 return ERROR_FLASH_OPERATION_FAILED;
187 if( status & FLASH_PGERR )
188 return ERROR_FLASH_OPERATION_FAILED;
189
190 /* clear readout protection and complementary option bytes
191 * this will also force a device unlock if set */
192 stm32x_info->option_bytes.RDP = 0x5AA5;
193
194 return ERROR_OK;
195 }
196
197 int stm32x_write_options(struct flash_bank_s *bank)
198 {
199 stm32x_flash_bank_t *stm32x_info = NULL;
200 target_t *target = bank->target;
201 u32 status;
202
203 stm32x_info = bank->driver_priv;
204
205 /* unlock flash registers */
206 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
207 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
208
209 /* unlock option flash registers */
210 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
211 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
212
213 /* program option bytes */
214 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
215
216 /* write user option byte */
217 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
218
219 status = stm32x_wait_status_busy(bank, 10);
220
221 if( status & FLASH_WRPRTERR )
222 return ERROR_FLASH_OPERATION_FAILED;
223 if( status & FLASH_PGERR )
224 return ERROR_FLASH_OPERATION_FAILED;
225
226 /* write protection byte 1 */
227 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
228
229 status = stm32x_wait_status_busy(bank, 10);
230
231 if( status & FLASH_WRPRTERR )
232 return ERROR_FLASH_OPERATION_FAILED;
233 if( status & FLASH_PGERR )
234 return ERROR_FLASH_OPERATION_FAILED;
235
236 /* write protection byte 2 */
237 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
238
239 status = stm32x_wait_status_busy(bank, 10);
240
241 if( status & FLASH_WRPRTERR )
242 return ERROR_FLASH_OPERATION_FAILED;
243 if( status & FLASH_PGERR )
244 return ERROR_FLASH_OPERATION_FAILED;
245
246 /* write protection byte 3 */
247 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
248
249 status = stm32x_wait_status_busy(bank, 10);
250
251 if( status & FLASH_WRPRTERR )
252 return ERROR_FLASH_OPERATION_FAILED;
253 if( status & FLASH_PGERR )
254 return ERROR_FLASH_OPERATION_FAILED;
255
256 /* write protection byte 4 */
257 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
258
259 status = stm32x_wait_status_busy(bank, 10);
260
261 if( status & FLASH_WRPRTERR )
262 return ERROR_FLASH_OPERATION_FAILED;
263 if( status & FLASH_PGERR )
264 return ERROR_FLASH_OPERATION_FAILED;
265
266 /* write readout protection bit */
267 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
268
269 status = stm32x_wait_status_busy(bank, 10);
270
271 if( status & FLASH_WRPRTERR )
272 return ERROR_FLASH_OPERATION_FAILED;
273 if( status & FLASH_PGERR )
274 return ERROR_FLASH_OPERATION_FAILED;
275
276 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
277
278 return ERROR_OK;
279 }
280
281 int stm32x_protect_check(struct flash_bank_s *bank)
282 {
283 target_t *target = bank->target;
284 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
285
286 u32 protection;
287 int i, s;
288 int num_bits;
289
290 if (target->state != TARGET_HALTED)
291 {
292 return ERROR_TARGET_NOT_HALTED;
293 }
294
295 /* medium density - each bit refers to a 4bank protection
296 * high density - each bit refers to a 2bank protection */
297 target_read_u32(target, STM32_FLASH_WRPR, &protection);
298
299 /* medium density - each protection bit is for 4 * 1K pages
300 * high density - each protection bit is for 2 * 2K pages */
301 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
302
303 for (i = 0; i < num_bits; i++)
304 {
305 int set = 1;
306
307 if( protection & (1 << i))
308 set = 0;
309
310 for (s = 0; s < stm32x_info->ppage_size; s++)
311 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
312 }
313
314 return ERROR_OK;
315 }
316
317 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
318 {
319 target_t *target = bank->target;
320 int i;
321 u32 status;
322
323 if (bank->target->state != TARGET_HALTED)
324 {
325 return ERROR_TARGET_NOT_HALTED;
326 }
327
328 if ((first == 0) && (last == (bank->num_sectors - 1)))
329 {
330 return stm32x_mass_erase(bank);
331 }
332
333 /* unlock flash registers */
334 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
335 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
336
337 for (i = first; i <= last; i++)
338 {
339 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
340 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
341 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
342
343 status = stm32x_wait_status_busy(bank, 10);
344
345 if( status & FLASH_WRPRTERR )
346 return ERROR_FLASH_OPERATION_FAILED;
347 if( status & FLASH_PGERR )
348 return ERROR_FLASH_OPERATION_FAILED;
349 bank->sectors[i].is_erased = 1;
350 }
351
352 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
353
354 return ERROR_OK;
355 }
356
357 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
358 {
359 stm32x_flash_bank_t *stm32x_info = NULL;
360 target_t *target = bank->target;
361 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
362 int i, reg, bit;
363 int status;
364 u32 protection;
365
366 stm32x_info = bank->driver_priv;
367
368 if (target->state != TARGET_HALTED)
369 {
370 return ERROR_TARGET_NOT_HALTED;
371 }
372
373 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
374 {
375 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
376 return ERROR_FLASH_SECTOR_INVALID;
377 }
378
379 /* medium density - each bit refers to a 4bank protection
380 * high density - each bit refers to a 2bank protection */
381 target_read_u32(target, STM32_FLASH_WRPR, &protection);
382
383 prot_reg[0] = (u16)protection;
384 prot_reg[1] = (u16)(protection >> 8);
385 prot_reg[2] = (u16)(protection >> 16);
386 prot_reg[3] = (u16)(protection >> 24);
387
388 for (i = first; i <= last; i++)
389 {
390 reg = (i / stm32x_info->ppage_size) / 8;
391 bit = (i / stm32x_info->ppage_size) - (reg * 8);
392
393 if( set )
394 prot_reg[reg] &= ~(1 << bit);
395 else
396 prot_reg[reg] |= (1 << bit);
397 }
398
399 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
400 return status;
401
402 stm32x_info->option_bytes.protection[0] = prot_reg[0];
403 stm32x_info->option_bytes.protection[1] = prot_reg[1];
404 stm32x_info->option_bytes.protection[2] = prot_reg[2];
405 stm32x_info->option_bytes.protection[3] = prot_reg[3];
406
407 return stm32x_write_options(bank);
408 }
409
410 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
411 {
412 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
413 target_t *target = bank->target;
414 u32 buffer_size = 8192;
415 working_area_t *source;
416 u32 address = bank->base + offset;
417 reg_param_t reg_params[4];
418 armv7m_algorithm_t armv7m_info;
419 int retval = ERROR_OK;
420
421 u8 stm32x_flash_write_code[] = {
422 /* write: */
423 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
424 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
425 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
426 0x23, 0x60, /* str r3, [r4, #0] */
427 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
428 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
429 /* busy: */
430 0x2B, 0x68, /* ldr r3, [r5, #0] */
431 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
432 0xFB, 0xD0, /* beq busy */
433 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
434 0x01, 0xD1, /* bne exit */
435 0x01, 0x3A, /* subs r2, r2, #1 */
436 0xED, 0xD1, /* bne write */
437 /* exit: */
438 0xFE, 0xE7, /* b exit */
439 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
440 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
441 };
442
443 /* flash write code */
444 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
445 {
446 LOG_WARNING("no working area available, can't do block memory writes");
447 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
448 };
449
450 if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
451 return retval;
452
453 /* memory buffer */
454 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
455 {
456 buffer_size /= 2;
457 if (buffer_size <= 256)
458 {
459 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
460 if (stm32x_info->write_algorithm)
461 target_free_working_area(target, stm32x_info->write_algorithm);
462
463 LOG_WARNING("no large enough working area available, can't do block memory writes");
464 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
465 }
466 };
467
468 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
469 armv7m_info.core_mode = ARMV7M_MODE_ANY;
470
471 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
472 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
473 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
474 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
475
476 while (count > 0)
477 {
478 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
479
480 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
481 break;
482
483 buf_set_u32(reg_params[0].value, 0, 32, source->address);
484 buf_set_u32(reg_params[1].value, 0, 32, address);
485 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
486
487 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
488 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
489 {
490 LOG_ERROR("error executing stm32x flash write algorithm");
491 retval = ERROR_FLASH_OPERATION_FAILED;
492 break;
493 }
494
495 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
496 {
497 retval = ERROR_FLASH_OPERATION_FAILED;
498 break;
499 }
500
501 buffer += thisrun_count * 2;
502 address += thisrun_count * 2;
503 count -= thisrun_count;
504 }
505
506 target_free_working_area(target, source);
507 target_free_working_area(target, stm32x_info->write_algorithm);
508
509 destroy_reg_param(&reg_params[0]);
510 destroy_reg_param(&reg_params[1]);
511 destroy_reg_param(&reg_params[2]);
512 destroy_reg_param(&reg_params[3]);
513
514 return retval;
515 }
516
517 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
518 {
519 target_t *target = bank->target;
520 u32 words_remaining = (count / 2);
521 u32 bytes_remaining = (count & 0x00000001);
522 u32 address = bank->base + offset;
523 u32 bytes_written = 0;
524 u8 status;
525 u32 retval;
526
527 if (bank->target->state != TARGET_HALTED)
528 {
529 return ERROR_TARGET_NOT_HALTED;
530 }
531
532 if (offset & 0x1)
533 {
534 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
535 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
536 }
537
538 /* unlock flash registers */
539 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
540 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
541
542 /* multiple half words (2-byte) to be programmed? */
543 if (words_remaining > 0)
544 {
545 /* try using a block write */
546 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
547 {
548 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
549 {
550 /* if block write failed (no sufficient working area),
551 * we use normal (slow) single dword accesses */
552 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
553 }
554 else if (retval == ERROR_FLASH_OPERATION_FAILED)
555 {
556 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
557 return ERROR_FLASH_OPERATION_FAILED;
558 }
559 }
560 else
561 {
562 buffer += words_remaining * 2;
563 address += words_remaining * 2;
564 words_remaining = 0;
565 }
566 }
567
568 while (words_remaining > 0)
569 {
570 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
571 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
572
573 status = stm32x_wait_status_busy(bank, 5);
574
575 if( status & FLASH_WRPRTERR )
576 return ERROR_FLASH_OPERATION_FAILED;
577 if( status & FLASH_PGERR )
578 return ERROR_FLASH_OPERATION_FAILED;
579
580 bytes_written += 2;
581 words_remaining--;
582 address += 2;
583 }
584
585 if (bytes_remaining)
586 {
587 u8 last_halfword[2] = {0xff, 0xff};
588 int i = 0;
589
590 while(bytes_remaining > 0)
591 {
592 last_halfword[i++] = *(buffer + bytes_written);
593 bytes_remaining--;
594 bytes_written++;
595 }
596
597 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
598 target_write_u16(target, address, *(u16*)last_halfword);
599
600 status = stm32x_wait_status_busy(bank, 5);
601
602 if( status & FLASH_WRPRTERR )
603 return ERROR_FLASH_OPERATION_FAILED;
604 if( status & FLASH_PGERR )
605 return ERROR_FLASH_OPERATION_FAILED;
606 }
607
608 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
609
610 return ERROR_OK;
611 }
612
613 int stm32x_probe(struct flash_bank_s *bank)
614 {
615 target_t *target = bank->target;
616 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
617 int i;
618 u16 num_pages;
619 u32 device_id;
620 int page_size;
621
622 if (bank->target->state != TARGET_HALTED)
623 {
624 return ERROR_TARGET_NOT_HALTED;
625 }
626
627 stm32x_info->probed = 0;
628
629 /* read stm32 device id register */
630 target_read_u32(target, 0xE0042000, &device_id);
631 LOG_INFO( "device id = 0x%08x", device_id );
632
633 /* get flash size from target */
634 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
635 {
636 /* failed reading flash size, default to max target family */
637 num_pages = 0xffff;
638 }
639
640 if ((device_id & 0x7ff) == 0x410)
641 {
642 /* medium density - we have 1k pages
643 * 4 pages for a protection area */
644 page_size = 1024;
645 stm32x_info->ppage_size = 4;
646
647 /* check for early silicon */
648 if (num_pages == 0xffff)
649 {
650 /* number of sectors incorrect on revA */
651 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
652 num_pages = 128;
653 }
654 }
655 else if ((device_id & 0x7ff) == 0x414)
656 {
657 /* high density - we have 2k pages
658 * 2 pages for a protection area */
659 page_size = 2048;
660 stm32x_info->ppage_size = 2;
661
662 /* check for early silicon */
663 if (num_pages == 0xffff)
664 {
665 /* number of sectors incorrect on revZ */
666 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
667 num_pages = 512;
668 }
669 }
670 else
671 {
672 LOG_WARNING( "Cannot identify target as a STM32 family." );
673 return ERROR_FLASH_OPERATION_FAILED;
674 }
675
676 LOG_INFO( "flash size = %dkbytes", num_pages );
677
678 /* calculate numbers of pages */
679 num_pages /= (page_size / 1024);
680
681 bank->base = 0x08000000;
682 bank->size = (num_pages * page_size);
683 bank->num_sectors = num_pages;
684 bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
685
686 for (i = 0; i < num_pages; i++)
687 {
688 bank->sectors[i].offset = i * page_size;
689 bank->sectors[i].size = page_size;
690 bank->sectors[i].is_erased = -1;
691 bank->sectors[i].is_protected = 1;
692 }
693
694 stm32x_info->probed = 1;
695
696 return ERROR_OK;
697 }
698
699 int stm32x_auto_probe(struct flash_bank_s *bank)
700 {
701 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
702 if (stm32x_info->probed)
703 return ERROR_OK;
704 return stm32x_probe(bank);
705 }
706
707 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
708 {
709 return ERROR_OK;
710 }
711
712 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
713 {
714 snprintf(buf, buf_size, "stm32x flash driver info" );
715 return ERROR_OK;
716 }
717
718 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
719 {
720 flash_bank_t *bank;
721 target_t *target = NULL;
722 stm32x_flash_bank_t *stm32x_info = NULL;
723
724 if (argc < 1)
725 {
726 command_print(cmd_ctx, "stm32x lock <bank>");
727 return ERROR_OK;
728 }
729
730 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
731 if (!bank)
732 {
733 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
734 return ERROR_OK;
735 }
736
737 stm32x_info = bank->driver_priv;
738
739 target = bank->target;
740
741 if (target->state != TARGET_HALTED)
742 {
743 return ERROR_TARGET_NOT_HALTED;
744 }
745
746 if (stm32x_erase_options(bank) != ERROR_OK)
747 {
748 command_print(cmd_ctx, "stm32x failed to erase options");
749 return ERROR_OK;
750 }
751
752 /* set readout protection */
753 stm32x_info->option_bytes.RDP = 0;
754
755 if (stm32x_write_options(bank) != ERROR_OK)
756 {
757 command_print(cmd_ctx, "stm32x failed to lock device");
758 return ERROR_OK;
759 }
760
761 command_print(cmd_ctx, "stm32x locked");
762
763 return ERROR_OK;
764 }
765
766 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
767 {
768 flash_bank_t *bank;
769 target_t *target = NULL;
770 stm32x_flash_bank_t *stm32x_info = NULL;
771
772 if (argc < 1)
773 {
774 command_print(cmd_ctx, "stm32x unlock <bank>");
775 return ERROR_OK;
776 }
777
778 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
779 if (!bank)
780 {
781 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
782 return ERROR_OK;
783 }
784
785 stm32x_info = bank->driver_priv;
786
787 target = bank->target;
788
789 if (target->state != TARGET_HALTED)
790 {
791 return ERROR_TARGET_NOT_HALTED;
792 }
793
794 if (stm32x_erase_options(bank) != ERROR_OK)
795 {
796 command_print(cmd_ctx, "stm32x failed to unlock device");
797 return ERROR_OK;
798 }
799
800 if (stm32x_write_options(bank) != ERROR_OK)
801 {
802 command_print(cmd_ctx, "stm32x failed to lock device");
803 return ERROR_OK;
804 }
805
806 command_print(cmd_ctx, "stm32x unlocked");
807
808 return ERROR_OK;
809 }
810
811 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
812 {
813 flash_bank_t *bank;
814 u32 optionbyte;
815 target_t *target = NULL;
816 stm32x_flash_bank_t *stm32x_info = NULL;
817
818 if (argc < 1)
819 {
820 command_print(cmd_ctx, "stm32x options_read <bank>");
821 return ERROR_OK;
822 }
823
824 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
825 if (!bank)
826 {
827 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
828 return ERROR_OK;
829 }
830
831 stm32x_info = bank->driver_priv;
832
833 target = bank->target;
834
835 if (target->state != TARGET_HALTED)
836 {
837 return ERROR_TARGET_NOT_HALTED;
838 }
839
840 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
841 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
842
843 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
844 command_print(cmd_ctx, "Option Byte Complement Error");
845
846 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
847 command_print(cmd_ctx, "Readout Protection On");
848 else
849 command_print(cmd_ctx, "Readout Protection Off");
850
851 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
852 command_print(cmd_ctx, "Software Watchdog");
853 else
854 command_print(cmd_ctx, "Hardware Watchdog");
855
856 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
857 command_print(cmd_ctx, "Stop: No reset generated");
858 else
859 command_print(cmd_ctx, "Stop: Reset generated");
860
861 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
862 command_print(cmd_ctx, "Standby: No reset generated");
863 else
864 command_print(cmd_ctx, "Standby: Reset generated");
865
866 return ERROR_OK;
867 }
868
869 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
870 {
871 flash_bank_t *bank;
872 target_t *target = NULL;
873 stm32x_flash_bank_t *stm32x_info = NULL;
874 u16 optionbyte = 0xF8;
875
876 if (argc < 4)
877 {
878 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
879 return ERROR_OK;
880 }
881
882 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
883 if (!bank)
884 {
885 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
886 return ERROR_OK;
887 }
888
889 stm32x_info = bank->driver_priv;
890
891 target = bank->target;
892
893 if (target->state != TARGET_HALTED)
894 {
895 return ERROR_TARGET_NOT_HALTED;
896 }
897
898 if (strcmp(args[1], "SWWDG") == 0)
899 {
900 optionbyte |= (1<<0);
901 }
902 else
903 {
904 optionbyte &= ~(1<<0);
905 }
906
907 if (strcmp(args[2], "NORSTSTNDBY") == 0)
908 {
909 optionbyte |= (1<<1);
910 }
911 else
912 {
913 optionbyte &= ~(1<<1);
914 }
915
916 if (strcmp(args[3], "NORSTSTOP") == 0)
917 {
918 optionbyte |= (1<<2);
919 }
920 else
921 {
922 optionbyte &= ~(1<<2);
923 }
924
925 if (stm32x_erase_options(bank) != ERROR_OK)
926 {
927 command_print(cmd_ctx, "stm32x failed to erase options");
928 return ERROR_OK;
929 }
930
931 stm32x_info->option_bytes.user_options = optionbyte;
932
933 if (stm32x_write_options(bank) != ERROR_OK)
934 {
935 command_print(cmd_ctx, "stm32x failed to write options");
936 return ERROR_OK;
937 }
938
939 command_print(cmd_ctx, "stm32x write options complete");
940
941 return ERROR_OK;
942 }
943
944 int stm32x_mass_erase(struct flash_bank_s *bank)
945 {
946 target_t *target = bank->target;
947 u32 status;
948
949 if (target->state != TARGET_HALTED)
950 {
951 return ERROR_TARGET_NOT_HALTED;
952 }
953
954 /* unlock option flash registers */
955 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
956 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
957
958 /* mass erase flash memory */
959 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
960 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
961
962 status = stm32x_wait_status_busy(bank, 10);
963
964 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
965
966 if( status & FLASH_WRPRTERR )
967 {
968 LOG_ERROR("stm32x device protected");
969 return ERROR_OK;
970 }
971
972 if( status & FLASH_PGERR )
973 {
974 LOG_ERROR("stm32x device programming failed");
975 return ERROR_OK;
976 }
977
978 return ERROR_OK;
979 }
980
981 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
982 {
983 flash_bank_t *bank;
984 int i;
985
986 if (argc < 1)
987 {
988 command_print(cmd_ctx, "stm32x mass_erase <bank>");
989 return ERROR_OK;
990 }
991
992 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
993 if (!bank)
994 {
995 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
996 return ERROR_OK;
997 }
998
999 if (stm32x_mass_erase(bank) == ERROR_OK)
1000 {
1001 /* set all sectors as erased */
1002 for (i = 0; i < bank->num_sectors; i++)
1003 {
1004 bank->sectors[i].is_erased = 1;
1005 }
1006
1007 command_print(cmd_ctx, "stm32x mass erase complete");
1008 }
1009 else
1010 {
1011 command_print(cmd_ctx, "stm32x mass erase failed");
1012 }
1013
1014 return ERROR_OK;
1015 }
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