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- more fixes to high density stm32x flash driver
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "stm32x.h"
30 #include "flash.h"
31 #include "target.h"
32 #include "log.h"
33 #include "armv7m.h"
34 #include "algorithm.h"
35 #include "binarybuffer.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 int stm32x_register_commands(struct command_context_s *cmd_ctx);
41 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
42 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
43 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
44 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
45 int stm32x_probe(struct flash_bank_s *bank);
46 int stm32x_auto_probe(struct flash_bank_s *bank);
47 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int stm32x_protect_check(struct flash_bank_s *bank);
49 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
50
51 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int stm32x_mass_erase(struct flash_bank_s *bank);
57
58 flash_driver_t stm32x_flash =
59 {
60 .name = "stm32x",
61 .register_commands = stm32x_register_commands,
62 .flash_bank_command = stm32x_flash_bank_command,
63 .erase = stm32x_erase,
64 .protect = stm32x_protect,
65 .write = stm32x_write,
66 .probe = stm32x_probe,
67 .auto_probe = stm32x_auto_probe,
68 .erase_check = default_flash_mem_blank_check,
69 .protect_check = stm32x_protect_check,
70 .info = stm32x_info
71 };
72
73 int stm32x_register_commands(struct command_context_s *cmd_ctx)
74 {
75 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
76
77 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
78 "lock device");
79 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
80 "unlock protected device");
81 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
82 "mass erase device");
83 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
84 "read device option bytes");
85 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
86 "write device option bytes");
87 return ERROR_OK;
88 }
89
90 /* flash bank stm32x <base> <size> 0 0 <target#>
91 */
92 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
93 {
94 stm32x_flash_bank_t *stm32x_info;
95
96 if (argc < 6)
97 {
98 LOG_WARNING("incomplete flash_bank stm32x configuration");
99 return ERROR_FLASH_BANK_INVALID;
100 }
101
102 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
103 bank->driver_priv = stm32x_info;
104
105 stm32x_info->write_algorithm = NULL;
106 stm32x_info->probed = 0;
107
108 return ERROR_OK;
109 }
110
111 u32 stm32x_get_flash_status(flash_bank_t *bank)
112 {
113 target_t *target = bank->target;
114 u32 status;
115
116 target_read_u32(target, STM32_FLASH_SR, &status);
117
118 return status;
119 }
120
121 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
122 {
123 u32 status;
124
125 /* wait for busy to clear */
126 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
127 {
128 LOG_DEBUG("status: 0x%x", status);
129 usleep(1000);
130 }
131
132 return status;
133 }
134
135 int stm32x_read_options(struct flash_bank_s *bank)
136 {
137 u32 optiondata;
138 stm32x_flash_bank_t *stm32x_info = NULL;
139 target_t *target = bank->target;
140
141 stm32x_info = bank->driver_priv;
142
143 /* read current option bytes */
144 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
145
146 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
147 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
148
149 if (optiondata & (1 << OPT_READOUT))
150 LOG_INFO("Device Security Bit Set");
151
152 /* each bit refers to a 4bank protection */
153 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
154
155 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
156 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
157 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
158 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
159
160 return ERROR_OK;
161 }
162
163 int stm32x_erase_options(struct flash_bank_s *bank)
164 {
165 stm32x_flash_bank_t *stm32x_info = NULL;
166 target_t *target = bank->target;
167 u32 status;
168
169 stm32x_info = bank->driver_priv;
170
171 /* read current options */
172 stm32x_read_options(bank);
173
174 /* unlock flash registers */
175 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
176 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
177
178 /* unlock option flash registers */
179 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
180 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
181
182 /* erase option bytes */
183 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
184 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
185
186 status = stm32x_wait_status_busy(bank, 10);
187
188 if( status & FLASH_WRPRTERR )
189 return ERROR_FLASH_OPERATION_FAILED;
190 if( status & FLASH_PGERR )
191 return ERROR_FLASH_OPERATION_FAILED;
192
193 /* clear readout protection and complementary option bytes
194 * this will also force a device unlock if set */
195 stm32x_info->option_bytes.RDP = 0x5AA5;
196
197 return ERROR_OK;
198 }
199
200 int stm32x_write_options(struct flash_bank_s *bank)
201 {
202 stm32x_flash_bank_t *stm32x_info = NULL;
203 target_t *target = bank->target;
204 u32 status;
205
206 stm32x_info = bank->driver_priv;
207
208 /* unlock flash registers */
209 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
210 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
211
212 /* unlock option flash registers */
213 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
214 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
215
216 /* program option bytes */
217 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
218
219 /* write user option byte */
220 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
221
222 status = stm32x_wait_status_busy(bank, 10);
223
224 if( status & FLASH_WRPRTERR )
225 return ERROR_FLASH_OPERATION_FAILED;
226 if( status & FLASH_PGERR )
227 return ERROR_FLASH_OPERATION_FAILED;
228
229 /* write protection byte 1 */
230 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
231
232 status = stm32x_wait_status_busy(bank, 10);
233
234 if( status & FLASH_WRPRTERR )
235 return ERROR_FLASH_OPERATION_FAILED;
236 if( status & FLASH_PGERR )
237 return ERROR_FLASH_OPERATION_FAILED;
238
239 /* write protection byte 2 */
240 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
241
242 status = stm32x_wait_status_busy(bank, 10);
243
244 if( status & FLASH_WRPRTERR )
245 return ERROR_FLASH_OPERATION_FAILED;
246 if( status & FLASH_PGERR )
247 return ERROR_FLASH_OPERATION_FAILED;
248
249 /* write protection byte 3 */
250 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
251
252 status = stm32x_wait_status_busy(bank, 10);
253
254 if( status & FLASH_WRPRTERR )
255 return ERROR_FLASH_OPERATION_FAILED;
256 if( status & FLASH_PGERR )
257 return ERROR_FLASH_OPERATION_FAILED;
258
259 /* write protection byte 4 */
260 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
261
262 status = stm32x_wait_status_busy(bank, 10);
263
264 if( status & FLASH_WRPRTERR )
265 return ERROR_FLASH_OPERATION_FAILED;
266 if( status & FLASH_PGERR )
267 return ERROR_FLASH_OPERATION_FAILED;
268
269 /* write readout protection bit */
270 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
271
272 status = stm32x_wait_status_busy(bank, 10);
273
274 if( status & FLASH_WRPRTERR )
275 return ERROR_FLASH_OPERATION_FAILED;
276 if( status & FLASH_PGERR )
277 return ERROR_FLASH_OPERATION_FAILED;
278
279 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
280
281 return ERROR_OK;
282 }
283
284 int stm32x_protect_check(struct flash_bank_s *bank)
285 {
286 target_t *target = bank->target;
287 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
288
289 u32 protection;
290 int i, s;
291 int num_bits;
292 int set;
293
294 if (target->state != TARGET_HALTED)
295 {
296 return ERROR_TARGET_NOT_HALTED;
297 }
298
299 /* medium density - each bit refers to a 4bank protection
300 * high density - each bit refers to a 2bank protection */
301 target_read_u32(target, STM32_FLASH_WRPR, &protection);
302
303 /* medium density - each protection bit is for 4 * 1K pages
304 * high density - each protection bit is for 2 * 2K pages */
305 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
306
307 if (stm32x_info->ppage_size == 2)
308 {
309 /* high density flash */
310
311 set = 1;
312
313 if (protection & (1 << 31))
314 set = 0;
315
316 /* bit 31 controls sector 62 - 255 protection */
317 for (s = 62; s < bank->num_sectors; s++)
318 {
319 bank->sectors[s].is_protected = set;
320 }
321
322 if (bank->num_sectors > 61)
323 num_bits = 31;
324
325 for (i = 0; i < num_bits; i++)
326 {
327 set = 1;
328
329 if (protection & (1 << i))
330 set = 0;
331
332 for (s = 0; s < stm32x_info->ppage_size; s++)
333 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
334 }
335 }
336 else
337 {
338 /* medium density flash */
339 for (i = 0; i < num_bits; i++)
340 {
341 set = 1;
342
343 if( protection & (1 << i))
344 set = 0;
345
346 for (s = 0; s < stm32x_info->ppage_size; s++)
347 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
348 }
349 }
350
351 return ERROR_OK;
352 }
353
354 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
355 {
356 target_t *target = bank->target;
357 int i;
358 u32 status;
359
360 if (bank->target->state != TARGET_HALTED)
361 {
362 return ERROR_TARGET_NOT_HALTED;
363 }
364
365 if ((first == 0) && (last == (bank->num_sectors - 1)))
366 {
367 return stm32x_mass_erase(bank);
368 }
369
370 /* unlock flash registers */
371 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
372 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
373
374 for (i = first; i <= last; i++)
375 {
376 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
377 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
378 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
379
380 status = stm32x_wait_status_busy(bank, 10);
381
382 if( status & FLASH_WRPRTERR )
383 return ERROR_FLASH_OPERATION_FAILED;
384 if( status & FLASH_PGERR )
385 return ERROR_FLASH_OPERATION_FAILED;
386 bank->sectors[i].is_erased = 1;
387 }
388
389 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
390
391 return ERROR_OK;
392 }
393
394 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
395 {
396 stm32x_flash_bank_t *stm32x_info = NULL;
397 target_t *target = bank->target;
398 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
399 int i, reg, bit;
400 int status;
401 u32 protection;
402
403 stm32x_info = bank->driver_priv;
404
405 if (target->state != TARGET_HALTED)
406 {
407 return ERROR_TARGET_NOT_HALTED;
408 }
409
410 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
411 {
412 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
413 return ERROR_FLASH_SECTOR_INVALID;
414 }
415
416 /* medium density - each bit refers to a 4bank protection
417 * high density - each bit refers to a 2bank protection */
418 target_read_u32(target, STM32_FLASH_WRPR, &protection);
419
420 prot_reg[0] = (u16)protection;
421 prot_reg[1] = (u16)(protection >> 8);
422 prot_reg[2] = (u16)(protection >> 16);
423 prot_reg[3] = (u16)(protection >> 24);
424
425 if (stm32x_info->ppage_size == 2)
426 {
427 /* high density flash */
428
429 /* bit 7 controls sector 62 - 255 protection */
430 if (last > 61)
431 {
432 if (set)
433 prot_reg[3] &= ~(1 << 7);
434 else
435 prot_reg[3] |= (1 << 7);
436 }
437
438 if (first > 61)
439 first = 62;
440 if (last > 61)
441 last = 61;
442
443 for (i = first; i <= last; i++)
444 {
445 reg = (i / stm32x_info->ppage_size) / 8;
446 bit = (i / stm32x_info->ppage_size) - (reg * 8);
447
448 if( set )
449 prot_reg[reg] &= ~(1 << bit);
450 else
451 prot_reg[reg] |= (1 << bit);
452 }
453 }
454 else
455 {
456 /* medium density flash */
457 for (i = first; i <= last; i++)
458 {
459 reg = (i / stm32x_info->ppage_size) / 8;
460 bit = (i / stm32x_info->ppage_size) - (reg * 8);
461
462 if( set )
463 prot_reg[reg] &= ~(1 << bit);
464 else
465 prot_reg[reg] |= (1 << bit);
466 }
467 }
468
469 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
470 return status;
471
472 stm32x_info->option_bytes.protection[0] = prot_reg[0];
473 stm32x_info->option_bytes.protection[1] = prot_reg[1];
474 stm32x_info->option_bytes.protection[2] = prot_reg[2];
475 stm32x_info->option_bytes.protection[3] = prot_reg[3];
476
477 return stm32x_write_options(bank);
478 }
479
480 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
481 {
482 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
483 target_t *target = bank->target;
484 u32 buffer_size = 8192;
485 working_area_t *source;
486 u32 address = bank->base + offset;
487 reg_param_t reg_params[4];
488 armv7m_algorithm_t armv7m_info;
489 int retval = ERROR_OK;
490
491 u8 stm32x_flash_write_code[] = {
492 /* write: */
493 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
494 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
495 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
496 0x23, 0x60, /* str r3, [r4, #0] */
497 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
498 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
499 /* busy: */
500 0x2B, 0x68, /* ldr r3, [r5, #0] */
501 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
502 0xFB, 0xD0, /* beq busy */
503 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
504 0x01, 0xD1, /* bne exit */
505 0x01, 0x3A, /* subs r2, r2, #1 */
506 0xED, 0xD1, /* bne write */
507 /* exit: */
508 0xFE, 0xE7, /* b exit */
509 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
510 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
511 };
512
513 /* flash write code */
514 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
515 {
516 LOG_WARNING("no working area available, can't do block memory writes");
517 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
518 };
519
520 if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
521 return retval;
522
523 /* memory buffer */
524 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
525 {
526 buffer_size /= 2;
527 if (buffer_size <= 256)
528 {
529 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
530 if (stm32x_info->write_algorithm)
531 target_free_working_area(target, stm32x_info->write_algorithm);
532
533 LOG_WARNING("no large enough working area available, can't do block memory writes");
534 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
535 }
536 };
537
538 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
539 armv7m_info.core_mode = ARMV7M_MODE_ANY;
540
541 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
542 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
543 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
544 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
545
546 while (count > 0)
547 {
548 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
549
550 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
551 break;
552
553 buf_set_u32(reg_params[0].value, 0, 32, source->address);
554 buf_set_u32(reg_params[1].value, 0, 32, address);
555 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
556
557 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
558 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
559 {
560 LOG_ERROR("error executing stm32x flash write algorithm");
561 retval = ERROR_FLASH_OPERATION_FAILED;
562 break;
563 }
564
565 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
566 {
567 retval = ERROR_FLASH_OPERATION_FAILED;
568 break;
569 }
570
571 buffer += thisrun_count * 2;
572 address += thisrun_count * 2;
573 count -= thisrun_count;
574 }
575
576 target_free_working_area(target, source);
577 target_free_working_area(target, stm32x_info->write_algorithm);
578
579 destroy_reg_param(&reg_params[0]);
580 destroy_reg_param(&reg_params[1]);
581 destroy_reg_param(&reg_params[2]);
582 destroy_reg_param(&reg_params[3]);
583
584 return retval;
585 }
586
587 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
588 {
589 target_t *target = bank->target;
590 u32 words_remaining = (count / 2);
591 u32 bytes_remaining = (count & 0x00000001);
592 u32 address = bank->base + offset;
593 u32 bytes_written = 0;
594 u8 status;
595 u32 retval;
596
597 if (bank->target->state != TARGET_HALTED)
598 {
599 return ERROR_TARGET_NOT_HALTED;
600 }
601
602 if (offset & 0x1)
603 {
604 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
605 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
606 }
607
608 /* unlock flash registers */
609 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
610 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
611
612 /* multiple half words (2-byte) to be programmed? */
613 if (words_remaining > 0)
614 {
615 /* try using a block write */
616 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
617 {
618 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
619 {
620 /* if block write failed (no sufficient working area),
621 * we use normal (slow) single dword accesses */
622 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
623 }
624 else if (retval == ERROR_FLASH_OPERATION_FAILED)
625 {
626 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
627 return ERROR_FLASH_OPERATION_FAILED;
628 }
629 }
630 else
631 {
632 buffer += words_remaining * 2;
633 address += words_remaining * 2;
634 words_remaining = 0;
635 }
636 }
637
638 while (words_remaining > 0)
639 {
640 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
641 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
642
643 status = stm32x_wait_status_busy(bank, 5);
644
645 if( status & FLASH_WRPRTERR )
646 return ERROR_FLASH_OPERATION_FAILED;
647 if( status & FLASH_PGERR )
648 return ERROR_FLASH_OPERATION_FAILED;
649
650 bytes_written += 2;
651 words_remaining--;
652 address += 2;
653 }
654
655 if (bytes_remaining)
656 {
657 u8 last_halfword[2] = {0xff, 0xff};
658 int i = 0;
659
660 while(bytes_remaining > 0)
661 {
662 last_halfword[i++] = *(buffer + bytes_written);
663 bytes_remaining--;
664 bytes_written++;
665 }
666
667 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
668 target_write_u16(target, address, *(u16*)last_halfword);
669
670 status = stm32x_wait_status_busy(bank, 5);
671
672 if( status & FLASH_WRPRTERR )
673 return ERROR_FLASH_OPERATION_FAILED;
674 if( status & FLASH_PGERR )
675 return ERROR_FLASH_OPERATION_FAILED;
676 }
677
678 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
679
680 return ERROR_OK;
681 }
682
683 int stm32x_probe(struct flash_bank_s *bank)
684 {
685 target_t *target = bank->target;
686 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
687 int i;
688 u16 num_pages;
689 u32 device_id;
690 int page_size;
691
692 if (bank->target->state != TARGET_HALTED)
693 {
694 return ERROR_TARGET_NOT_HALTED;
695 }
696
697 stm32x_info->probed = 0;
698
699 /* read stm32 device id register */
700 target_read_u32(target, 0xE0042000, &device_id);
701 LOG_INFO( "device id = 0x%08x", device_id );
702
703 /* get flash size from target */
704 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
705 {
706 /* failed reading flash size, default to max target family */
707 num_pages = 0xffff;
708 }
709
710 if ((device_id & 0x7ff) == 0x410)
711 {
712 /* medium density - we have 1k pages
713 * 4 pages for a protection area */
714 page_size = 1024;
715 stm32x_info->ppage_size = 4;
716
717 /* check for early silicon */
718 if (num_pages == 0xffff)
719 {
720 /* number of sectors incorrect on revA */
721 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
722 num_pages = 128;
723 }
724 }
725 else if ((device_id & 0x7ff) == 0x414)
726 {
727 /* high density - we have 2k pages
728 * 2 pages for a protection area */
729 page_size = 2048;
730 stm32x_info->ppage_size = 2;
731
732 /* check for early silicon */
733 if (num_pages == 0xffff)
734 {
735 /* number of sectors incorrect on revZ */
736 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
737 num_pages = 512;
738 }
739 }
740 else
741 {
742 LOG_WARNING( "Cannot identify target as a STM32 family." );
743 return ERROR_FLASH_OPERATION_FAILED;
744 }
745
746 LOG_INFO( "flash size = %dkbytes", num_pages );
747
748 /* calculate numbers of pages */
749 num_pages /= (page_size / 1024);
750
751 bank->base = 0x08000000;
752 bank->size = (num_pages * page_size);
753 bank->num_sectors = num_pages;
754 bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
755
756 for (i = 0; i < num_pages; i++)
757 {
758 bank->sectors[i].offset = i * page_size;
759 bank->sectors[i].size = page_size;
760 bank->sectors[i].is_erased = -1;
761 bank->sectors[i].is_protected = 1;
762 }
763
764 stm32x_info->probed = 1;
765
766 return ERROR_OK;
767 }
768
769 int stm32x_auto_probe(struct flash_bank_s *bank)
770 {
771 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
772 if (stm32x_info->probed)
773 return ERROR_OK;
774 return stm32x_probe(bank);
775 }
776
777 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
778 {
779 return ERROR_OK;
780 }
781
782 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
783 {
784 target_t *target = bank->target;
785 u32 device_id;
786 int printed;
787
788 /* read stm32 device id register */
789 target_read_u32(target, 0xE0042000, &device_id);
790
791 if ((device_id & 0x7ff) == 0x410)
792 {
793 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
794 buf += printed;
795 buf_size -= printed;
796
797 switch(device_id >> 16)
798 {
799 case 0x0000:
800 snprintf(buf, buf_size, "A");
801 break;
802
803 case 0x2000:
804 snprintf(buf, buf_size, "B");
805 break;
806
807 case 0x2001:
808 snprintf(buf, buf_size, "Z");
809 break;
810
811 case 0x2003:
812 snprintf(buf, buf_size, "Y");
813 break;
814
815 default:
816 snprintf(buf, buf_size, "unknown");
817 break;
818 }
819 }
820 else if ((device_id & 0x7ff) == 0x414)
821 {
822 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
823 buf += printed;
824 buf_size -= printed;
825
826 switch(device_id >> 16)
827 {
828 case 0x1000:
829 snprintf(buf, buf_size, "A");
830 break;
831
832 case 0x1001:
833 snprintf(buf, buf_size, "Z");
834 break;
835
836 default:
837 snprintf(buf, buf_size, "unknown");
838 break;
839 }
840 }
841 else
842 {
843 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
844 return ERROR_FLASH_OPERATION_FAILED;
845 }
846
847 return ERROR_OK;
848 }
849
850 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
851 {
852 flash_bank_t *bank;
853 target_t *target = NULL;
854 stm32x_flash_bank_t *stm32x_info = NULL;
855
856 if (argc < 1)
857 {
858 command_print(cmd_ctx, "stm32x lock <bank>");
859 return ERROR_OK;
860 }
861
862 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
863 if (!bank)
864 {
865 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
866 return ERROR_OK;
867 }
868
869 stm32x_info = bank->driver_priv;
870
871 target = bank->target;
872
873 if (target->state != TARGET_HALTED)
874 {
875 return ERROR_TARGET_NOT_HALTED;
876 }
877
878 if (stm32x_erase_options(bank) != ERROR_OK)
879 {
880 command_print(cmd_ctx, "stm32x failed to erase options");
881 return ERROR_OK;
882 }
883
884 /* set readout protection */
885 stm32x_info->option_bytes.RDP = 0;
886
887 if (stm32x_write_options(bank) != ERROR_OK)
888 {
889 command_print(cmd_ctx, "stm32x failed to lock device");
890 return ERROR_OK;
891 }
892
893 command_print(cmd_ctx, "stm32x locked");
894
895 return ERROR_OK;
896 }
897
898 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
899 {
900 flash_bank_t *bank;
901 target_t *target = NULL;
902 stm32x_flash_bank_t *stm32x_info = NULL;
903
904 if (argc < 1)
905 {
906 command_print(cmd_ctx, "stm32x unlock <bank>");
907 return ERROR_OK;
908 }
909
910 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
911 if (!bank)
912 {
913 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
914 return ERROR_OK;
915 }
916
917 stm32x_info = bank->driver_priv;
918
919 target = bank->target;
920
921 if (target->state != TARGET_HALTED)
922 {
923 return ERROR_TARGET_NOT_HALTED;
924 }
925
926 if (stm32x_erase_options(bank) != ERROR_OK)
927 {
928 command_print(cmd_ctx, "stm32x failed to unlock device");
929 return ERROR_OK;
930 }
931
932 if (stm32x_write_options(bank) != ERROR_OK)
933 {
934 command_print(cmd_ctx, "stm32x failed to lock device");
935 return ERROR_OK;
936 }
937
938 command_print(cmd_ctx, "stm32x unlocked");
939
940 return ERROR_OK;
941 }
942
943 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
944 {
945 flash_bank_t *bank;
946 u32 optionbyte;
947 target_t *target = NULL;
948 stm32x_flash_bank_t *stm32x_info = NULL;
949
950 if (argc < 1)
951 {
952 command_print(cmd_ctx, "stm32x options_read <bank>");
953 return ERROR_OK;
954 }
955
956 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
957 if (!bank)
958 {
959 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
960 return ERROR_OK;
961 }
962
963 stm32x_info = bank->driver_priv;
964
965 target = bank->target;
966
967 if (target->state != TARGET_HALTED)
968 {
969 return ERROR_TARGET_NOT_HALTED;
970 }
971
972 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
973 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
974
975 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
976 command_print(cmd_ctx, "Option Byte Complement Error");
977
978 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
979 command_print(cmd_ctx, "Readout Protection On");
980 else
981 command_print(cmd_ctx, "Readout Protection Off");
982
983 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
984 command_print(cmd_ctx, "Software Watchdog");
985 else
986 command_print(cmd_ctx, "Hardware Watchdog");
987
988 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
989 command_print(cmd_ctx, "Stop: No reset generated");
990 else
991 command_print(cmd_ctx, "Stop: Reset generated");
992
993 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
994 command_print(cmd_ctx, "Standby: No reset generated");
995 else
996 command_print(cmd_ctx, "Standby: Reset generated");
997
998 return ERROR_OK;
999 }
1000
1001 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1002 {
1003 flash_bank_t *bank;
1004 target_t *target = NULL;
1005 stm32x_flash_bank_t *stm32x_info = NULL;
1006 u16 optionbyte = 0xF8;
1007
1008 if (argc < 4)
1009 {
1010 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
1011 return ERROR_OK;
1012 }
1013
1014 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1015 if (!bank)
1016 {
1017 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1018 return ERROR_OK;
1019 }
1020
1021 stm32x_info = bank->driver_priv;
1022
1023 target = bank->target;
1024
1025 if (target->state != TARGET_HALTED)
1026 {
1027 return ERROR_TARGET_NOT_HALTED;
1028 }
1029
1030 if (strcmp(args[1], "SWWDG") == 0)
1031 {
1032 optionbyte |= (1<<0);
1033 }
1034 else
1035 {
1036 optionbyte &= ~(1<<0);
1037 }
1038
1039 if (strcmp(args[2], "NORSTSTNDBY") == 0)
1040 {
1041 optionbyte |= (1<<1);
1042 }
1043 else
1044 {
1045 optionbyte &= ~(1<<1);
1046 }
1047
1048 if (strcmp(args[3], "NORSTSTOP") == 0)
1049 {
1050 optionbyte |= (1<<2);
1051 }
1052 else
1053 {
1054 optionbyte &= ~(1<<2);
1055 }
1056
1057 if (stm32x_erase_options(bank) != ERROR_OK)
1058 {
1059 command_print(cmd_ctx, "stm32x failed to erase options");
1060 return ERROR_OK;
1061 }
1062
1063 stm32x_info->option_bytes.user_options = optionbyte;
1064
1065 if (stm32x_write_options(bank) != ERROR_OK)
1066 {
1067 command_print(cmd_ctx, "stm32x failed to write options");
1068 return ERROR_OK;
1069 }
1070
1071 command_print(cmd_ctx, "stm32x write options complete");
1072
1073 return ERROR_OK;
1074 }
1075
1076 int stm32x_mass_erase(struct flash_bank_s *bank)
1077 {
1078 target_t *target = bank->target;
1079 u32 status;
1080
1081 if (target->state != TARGET_HALTED)
1082 {
1083 return ERROR_TARGET_NOT_HALTED;
1084 }
1085
1086 /* unlock option flash registers */
1087 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1088 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1089
1090 /* mass erase flash memory */
1091 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1092 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
1093
1094 status = stm32x_wait_status_busy(bank, 10);
1095
1096 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1097
1098 if( status & FLASH_WRPRTERR )
1099 {
1100 LOG_ERROR("stm32x device protected");
1101 return ERROR_OK;
1102 }
1103
1104 if( status & FLASH_PGERR )
1105 {
1106 LOG_ERROR("stm32x device programming failed");
1107 return ERROR_OK;
1108 }
1109
1110 return ERROR_OK;
1111 }
1112
1113 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1114 {
1115 flash_bank_t *bank;
1116 int i;
1117
1118 if (argc < 1)
1119 {
1120 command_print(cmd_ctx, "stm32x mass_erase <bank>");
1121 return ERROR_OK;
1122 }
1123
1124 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1125 if (!bank)
1126 {
1127 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1128 return ERROR_OK;
1129 }
1130
1131 if (stm32x_mass_erase(bank) == ERROR_OK)
1132 {
1133 /* set all sectors as erased */
1134 for (i = 0; i < bank->num_sectors; i++)
1135 {
1136 bank->sectors[i].is_erased = 1;
1137 }
1138
1139 command_print(cmd_ctx, "stm32x mass erase complete");
1140 }
1141 else
1142 {
1143 command_print(cmd_ctx, "stm32x mass erase failed");
1144 }
1145
1146 return ERROR_OK;
1147 }
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