1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "arm7_9_common.h"
33 #include "binarybuffer.h"
40 str9xpec_mem_layout_t mem_layout_str9pec
[] = {
41 {0x00000000, 0x10000, 0},
42 {0x00010000, 0x10000, 1},
43 {0x00020000, 0x10000, 2},
44 {0x00030000, 0x10000, 3},
45 {0x00040000, 0x10000, 4},
46 {0x00050000, 0x10000, 5},
47 {0x00060000, 0x10000, 6},
48 {0x00070000, 0x10000, 7},
49 {0x00080000, 0x02000, 32},
50 {0x00082000, 0x02000, 33},
51 {0x00084000, 0x02000, 34},
52 {0x00086000, 0x02000, 35}
55 int str9xpec_register_commands(struct command_context_s
*cmd_ctx
);
56 int str9xpec_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
57 int str9xpec_erase(struct flash_bank_s
*bank
, int first
, int last
);
58 int str9xpec_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
59 int str9xpec_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
60 int str9xpec_probe(struct flash_bank_s
*bank
);
61 int str9xpec_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
62 int str9xpec_protect_check(struct flash_bank_s
*bank
);
63 int str9xpec_erase_check(struct flash_bank_s
*bank
);
64 int str9xpec_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
66 int str9xpec_erase_area(struct flash_bank_s
*bank
, int first
, int last
);
67 int str9xpec_set_address(struct flash_bank_s
*bank
, u8 sector
);
68 int str9xpec_write_options(struct flash_bank_s
*bank
);
70 int str9xpec_handle_flash_options_cmap_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
71 int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
72 int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
73 int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
74 int str9xpec_handle_flash_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
75 int str9xpec_handle_flash_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
76 int str9xpec_handle_flash_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
77 int str9xpec_handle_flash_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
78 int str9xpec_handle_flash_enable_turbo_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
79 int str9xpec_handle_flash_disable_turbo_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
81 flash_driver_t str9xpec_flash
=
84 .register_commands
= str9xpec_register_commands
,
85 .flash_bank_command
= str9xpec_flash_bank_command
,
86 .erase
= str9xpec_erase
,
87 .protect
= str9xpec_protect
,
88 .write
= str9xpec_write
,
89 .probe
= str9xpec_probe
,
90 .erase_check
= str9xpec_erase_check
,
91 .protect_check
= str9xpec_protect_check
,
95 int str9xpec_register_commands(struct command_context_s
*cmd_ctx
)
97 command_t
*str9xpec_cmd
= register_command(cmd_ctx
, NULL
, "str9xpec", NULL
, COMMAND_ANY
, "str9xpec flash specific commands");
99 register_command(cmd_ctx
, str9xpec_cmd
, "enable_turbo", str9xpec_handle_flash_enable_turbo_command
, COMMAND_EXEC
,
100 "enable str9xpec turbo mode");
101 register_command(cmd_ctx
, str9xpec_cmd
, "disable_turbo", str9xpec_handle_flash_disable_turbo_command
, COMMAND_EXEC
,
102 "disable str9xpec turbo mode");
103 register_command(cmd_ctx
, str9xpec_cmd
, "options_cmap", str9xpec_handle_flash_options_cmap_command
, COMMAND_EXEC
,
104 "configure str9xpec boot sector");
105 register_command(cmd_ctx
, str9xpec_cmd
, "options_lvdthd", str9xpec_handle_flash_options_lvdthd_command
, COMMAND_EXEC
,
106 "configure str9xpec lvd threshold");
107 register_command(cmd_ctx
, str9xpec_cmd
, "options_lvdsel", str9xpec_handle_flash_options_lvdsel_command
, COMMAND_EXEC
,
108 "configure str9xpec lvd selection");
109 register_command(cmd_ctx
, str9xpec_cmd
, "options_lvdwarn", str9xpec_handle_flash_options_lvdwarn_command
, COMMAND_EXEC
,
110 "configure str9xpec lvd warning");
111 register_command(cmd_ctx
, str9xpec_cmd
, "options_read", str9xpec_handle_flash_options_read_command
, COMMAND_EXEC
,
112 "read str9xpec options");
113 register_command(cmd_ctx
, str9xpec_cmd
, "options_write", str9xpec_handle_flash_options_write_command
, COMMAND_EXEC
,
114 "write str9xpec options");
115 register_command(cmd_ctx
, str9xpec_cmd
, "lock", str9xpec_handle_flash_lock_command
, COMMAND_EXEC
,
116 "lock str9xpec device");
117 register_command(cmd_ctx
, str9xpec_cmd
, "unlock", str9xpec_handle_flash_unlock_command
, COMMAND_EXEC
,
118 "unlock str9xpec device");
119 register_command(cmd_ctx
, str9xpec_cmd
, "part_id", str9xpec_handle_part_id_command
, COMMAND_EXEC
,
120 "print part id of str9xpec flash bank <num>");
125 int str9xpec_set_instr(int chain_pos
, u32 new_instr
, enum tap_state end_state
)
127 jtag_device_t
*device
= jtag_get_device(chain_pos
);
131 DEBUG("Invalid Target");
132 return ERROR_TARGET_INVALID
;
135 if (buf_get_u32(device
->cur_instr
, 0, device
->ir_length
) != new_instr
)
139 field
.device
= chain_pos
;
140 field
.num_bits
= device
->ir_length
;
141 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
142 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
143 field
.out_mask
= NULL
;
144 field
.in_value
= NULL
;
145 field
.in_check_value
= NULL
;
146 field
.in_check_mask
= NULL
;
147 field
.in_handler
= NULL
;
148 field
.in_handler_priv
= NULL
;
150 jtag_add_ir_scan(1, &field
, end_state
, NULL
);
152 free(field
.out_value
);
158 u8
str9xpec_isc_status(int chain_pos
)
163 if (str9xpec_set_instr(chain_pos
, ISC_NOOP
, TAP_PI
) != ERROR_OK
)
164 return ISC_STATUS_ERROR
;
166 field
.device
= chain_pos
;
168 field
.out_value
= NULL
;
169 field
.out_mask
= NULL
;
170 field
.in_value
= &status
;
171 field
.in_check_value
= NULL
;
172 field
.in_check_mask
= NULL
;
173 field
.in_handler
= NULL
;
174 field
.in_handler_priv
= NULL
;
176 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
177 jtag_execute_queue();
179 DEBUG("status: 0x%2.2x", status
);
181 if (status
& ISC_STATUS_SECURITY
)
182 INFO("Device Security Bit Set");
187 int str9xpec_isc_enable(struct flash_bank_s
*bank
)
191 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
193 chain_pos
= str9xpec_info
->chain_pos
;
195 if (str9xpec_info
->isc_enable
)
199 if (str9xpec_set_instr(chain_pos
, ISC_ENABLE
, TAP_RTI
) != ERROR_OK
)
200 return ERROR_TARGET_INVALID
;
202 /* check ISC status */
203 status
= str9xpec_isc_status(chain_pos
);
204 if (status
& ISC_STATUS_MODE
)
206 /* we have entered isc mode */
207 str9xpec_info
->isc_enable
= 1;
208 DEBUG("ISC_MODE Enabled");
214 int str9xpec_isc_disable(struct flash_bank_s
*bank
)
218 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
220 chain_pos
= str9xpec_info
->chain_pos
;
222 if (!str9xpec_info
->isc_enable
)
225 if (str9xpec_set_instr(chain_pos
, ISC_DISABLE
, TAP_RTI
) != ERROR_OK
)
226 return ERROR_TARGET_INVALID
;
228 /* delay to handle aborts */
231 /* check ISC status */
232 status
= str9xpec_isc_status(chain_pos
);
233 if (!(status
& ISC_STATUS_MODE
))
235 /* we have left isc mode */
236 str9xpec_info
->isc_enable
= 0;
237 DEBUG("ISC_MODE Disabled");
243 int str9xpec_read_config(struct flash_bank_s
*bank
)
249 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
251 chain_pos
= str9xpec_info
->chain_pos
;
253 DEBUG("ISC_CONFIGURATION");
255 /* execute ISC_CONFIGURATION command */
256 str9xpec_set_instr(chain_pos
, ISC_CONFIGURATION
, TAP_PI
);
258 field
.device
= chain_pos
;
260 field
.out_value
= NULL
;
261 field
.out_mask
= NULL
;
262 field
.in_value
= str9xpec_info
->options
;
263 field
.in_check_value
= NULL
;
264 field
.in_check_mask
= NULL
;
265 field
.in_handler
= NULL
;
266 field
.in_handler_priv
= NULL
;
268 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
269 jtag_execute_queue();
271 status
= str9xpec_isc_status(chain_pos
);
276 int str9xpec_build_block_list(struct flash_bank_s
*bank
)
278 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
281 int num_sectors
= 0, b0_sectors
= 0;
292 ERROR("BUG: unknown bank->size encountered");
296 /* include bank 1 sectors */
297 num_sectors
= b0_sectors
+ 4;
298 bank
->size
+= (32 * 1024);
300 bank
->num_sectors
= num_sectors
;
301 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
302 str9xpec_info
->sector_bits
= malloc(sizeof(u32
) * num_sectors
);
306 for (i
= 0; i
< b0_sectors
; i
++)
308 bank
->sectors
[num_sectors
].offset
= mem_layout_str9pec
[i
].sector_start
;
309 bank
->sectors
[num_sectors
].size
= mem_layout_str9pec
[i
].sector_size
;
310 bank
->sectors
[num_sectors
].is_erased
= -1;
311 bank
->sectors
[num_sectors
].is_protected
= 1;
312 str9xpec_info
->sector_bits
[num_sectors
++] = mem_layout_str9pec
[i
].sector_bit
;
315 for (i
= 8; i
< 12; i
++)
317 bank
->sectors
[num_sectors
].offset
= mem_layout_str9pec
[i
].sector_start
;
318 bank
->sectors
[num_sectors
].size
= mem_layout_str9pec
[i
].sector_size
;
319 bank
->sectors
[num_sectors
].is_erased
= -1;
320 bank
->sectors
[num_sectors
].is_protected
= 1;
321 str9xpec_info
->sector_bits
[num_sectors
++] = mem_layout_str9pec
[i
].sector_bit
;
327 /* flash bank str9x <base> <size> 0 0 <target#>
329 int str9xpec_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
331 str9xpec_flash_controller_t
*str9xpec_info
;
332 armv4_5_common_t
*armv4_5
= NULL
;
333 arm7_9_common_t
*arm7_9
= NULL
;
334 arm_jtag_t
*jtag_info
= NULL
;
338 WARNING("incomplete flash_bank str9x configuration");
339 return ERROR_FLASH_BANK_INVALID
;
342 str9xpec_info
= malloc(sizeof(str9xpec_flash_controller_t
));
343 bank
->driver_priv
= str9xpec_info
;
345 if (bank
->base
!= 0x00000000)
347 WARNING("overriding flash base address for STR91x device with 0x00000000");
348 bank
->base
= 0x00000000;
351 /* find out jtag position of flash controller
352 * it is always after the arm966 core */
354 armv4_5
= bank
->target
->arch_info
;
355 arm7_9
= armv4_5
->arch_info
;
356 jtag_info
= &arm7_9
->jtag_info
;
358 str9xpec_info
->chain_pos
= (jtag_info
->chain_pos
- 1);
359 str9xpec_info
->isc_enable
= 0;
360 str9xpec_info
->devarm
= NULL
;
362 str9xpec_build_block_list(bank
);
364 /* clear option byte register */
365 buf_set_u32(str9xpec_info
->options
, 0, 64, 0);
370 int str9xpec_blank_check(struct flash_bank_s
*bank
, int first
, int last
)
378 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
380 chain_pos
= str9xpec_info
->chain_pos
;
382 if (!str9xpec_info
->isc_enable
) {
383 str9xpec_isc_enable( bank
);
386 if (!str9xpec_info
->isc_enable
) {
387 return ERROR_FLASH_OPERATION_FAILED
;
390 buffer
= calloc(CEIL(64, 8), 1);
392 DEBUG("blank check: first_bank: %i, last_bank: %i", first
, last
);
394 for (i
= first
; i
<= last
; i
++) {
395 buf_set_u32(buffer
, str9xpec_info
->sector_bits
[i
], 1, 1);
398 /* execute ISC_BLANK_CHECK command */
399 str9xpec_set_instr(chain_pos
, ISC_BLANK_CHECK
, TAP_PI
);
401 field
.device
= chain_pos
;
403 field
.out_value
= buffer
;
404 field
.out_mask
= NULL
;
405 field
.in_value
= NULL
;
406 field
.in_check_value
= NULL
;
407 field
.in_check_mask
= NULL
;
408 field
.in_handler
= NULL
;
409 field
.in_handler_priv
= NULL
;
411 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
412 jtag_add_sleep(40000);
414 /* read blank check result */
415 field
.device
= chain_pos
;
417 field
.out_value
= NULL
;
418 field
.out_mask
= NULL
;
419 field
.in_value
= buffer
;
420 field
.in_check_value
= NULL
;
421 field
.in_check_mask
= NULL
;
422 field
.in_handler
= NULL
;
423 field
.in_handler_priv
= NULL
;
425 jtag_add_dr_scan(1, &field
, TAP_PI
, NULL
);
426 jtag_execute_queue();
428 status
= str9xpec_isc_status(chain_pos
);
430 for (i
= first
; i
<= last
; i
++)
432 if (buf_get_u32(buffer
, str9xpec_info
->sector_bits
[i
], 1))
433 bank
->sectors
[i
].is_erased
= 0;
435 bank
->sectors
[i
].is_erased
= 1;
440 str9xpec_isc_disable(bank
);
442 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
443 return ERROR_FLASH_OPERATION_FAILED
;
447 int str9xpec_protect_check(struct flash_bank_s
*bank
)
452 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
454 status
= str9xpec_read_config(bank
);
456 for (i
= 0; i
< bank
->num_sectors
; i
++)
458 if (buf_get_u32(str9xpec_info
->options
, str9xpec_info
->sector_bits
[i
], 1))
459 bank
->sectors
[i
].is_protected
= 1;
461 bank
->sectors
[i
].is_protected
= 0;
464 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
465 return ERROR_FLASH_OPERATION_FAILED
;
469 int str9xpec_erase_area(struct flash_bank_s
*bank
, int first
, int last
)
477 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
479 chain_pos
= str9xpec_info
->chain_pos
;
481 if (!str9xpec_info
->isc_enable
) {
482 str9xpec_isc_enable( bank
);
485 if (!str9xpec_info
->isc_enable
) {
486 return ISC_STATUS_ERROR
;
489 buffer
= calloc(CEIL(64, 8), 1);
491 DEBUG("erase: first_bank: %i, last_bank: %i", first
, last
);
493 /* last bank: 0xFF signals a full erase (unlock complete device) */
494 /* last bank: 0xFE signals a option byte erase */
497 for (i
= 0; i
< 64; i
++) {
498 buf_set_u32(buffer
, i
, 1, 1);
501 else if (last
== 0xFE)
503 buf_set_u32(buffer
, 49, 1, 1);
507 for (i
= first
; i
<= last
; i
++) {
508 buf_set_u32(buffer
, str9xpec_info
->sector_bits
[i
], 1, 1);
514 /* execute ISC_ERASE command */
515 str9xpec_set_instr(chain_pos
, ISC_ERASE
, TAP_PI
);
517 field
.device
= chain_pos
;
519 field
.out_value
= buffer
;
520 field
.out_mask
= NULL
;
521 field
.in_value
= NULL
;
522 field
.in_check_value
= NULL
;
523 field
.in_check_mask
= NULL
;
524 field
.in_handler
= NULL
;
525 field
.in_handler_priv
= NULL
;
527 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
528 jtag_execute_queue();
532 /* wait for erase completion */
533 while (!((status
= str9xpec_isc_status(chain_pos
)) & ISC_STATUS_BUSY
)) {
539 str9xpec_isc_disable(bank
);
544 int str9xpec_erase(struct flash_bank_s
*bank
, int first
, int last
)
548 status
= str9xpec_erase_area(bank
, first
, last
);
550 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
551 return ERROR_FLASH_OPERATION_FAILED
;
556 int str9xpec_lock_device(struct flash_bank_s
*bank
)
561 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
563 str9xpec_info
= bank
->driver_priv
;
564 chain_pos
= str9xpec_info
->chain_pos
;
566 if (!str9xpec_info
->isc_enable
) {
567 str9xpec_isc_enable( bank
);
570 if (!str9xpec_info
->isc_enable
) {
571 return ISC_STATUS_ERROR
;
574 /* set security address */
575 str9xpec_set_address(bank
, 0x80);
577 /* execute ISC_PROGRAM command */
578 str9xpec_set_instr(chain_pos
, ISC_PROGRAM_SECURITY
, TAP_RTI
);
580 str9xpec_set_instr(chain_pos
, ISC_NOOP
, TAP_PI
);
583 field
.device
= chain_pos
;
585 field
.out_value
= NULL
;
586 field
.out_mask
= NULL
;
587 field
.in_value
= &status
;
588 field
.in_check_value
= NULL
;
589 field
.in_check_mask
= NULL
;
590 field
.in_handler
= NULL
;
591 field
.in_handler_priv
= NULL
;
593 jtag_add_dr_scan(1, &field
, -1, NULL
);
594 jtag_execute_queue();
596 } while(!(status
& ISC_STATUS_BUSY
));
598 str9xpec_isc_disable(bank
);
603 int str9xpec_unlock_device(struct flash_bank_s
*bank
)
607 status
= str9xpec_erase_area(bank
, 0, 255);
612 int str9xpec_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
617 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
619 status
= str9xpec_read_config(bank
);
621 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
622 return ERROR_FLASH_OPERATION_FAILED
;
624 DEBUG("protect: first_bank: %i, last_bank: %i", first
, last
);
626 /* last bank: 0xFF signals a full device protect */
631 status
= str9xpec_lock_device(bank
);
635 /* perform full erase to unlock device */
636 status
= str9xpec_unlock_device(bank
);
641 for (i
= first
; i
<= last
; i
++)
644 buf_set_u32(str9xpec_info
->options
, str9xpec_info
->sector_bits
[i
], 1, 1);
646 buf_set_u32(str9xpec_info
->options
, str9xpec_info
->sector_bits
[i
], 1, 0);
649 status
= str9xpec_write_options(bank
);
652 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
653 return ERROR_FLASH_OPERATION_FAILED
;
658 int str9xpec_set_address(struct flash_bank_s
*bank
, u8 sector
)
662 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
664 chain_pos
= str9xpec_info
->chain_pos
;
666 /* set flash controller address */
667 str9xpec_set_instr(chain_pos
, ISC_ADDRESS_SHIFT
, TAP_PI
);
669 field
.device
= chain_pos
;
671 field
.out_value
= §or
;
672 field
.out_mask
= NULL
;
673 field
.in_value
= NULL
;
674 field
.in_check_value
= NULL
;
675 field
.in_check_mask
= NULL
;
676 field
.in_handler
= NULL
;
677 field
.in_handler_priv
= NULL
;
679 jtag_add_dr_scan(1, &field
, -1, NULL
);
684 int str9xpec_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
686 str9xpec_flash_controller_t
*str9xpec_info
= bank
->driver_priv
;
687 u32 dwords_remaining
= (count
/ 8);
688 u32 bytes_remaining
= (count
& 0x00000007);
689 u32 bytes_written
= 0;
691 u32 check_address
= offset
;
696 u32 first_sector
= 0;
699 chain_pos
= str9xpec_info
->chain_pos
;
701 if (!str9xpec_info
->isc_enable
) {
702 str9xpec_isc_enable(bank
);
705 if (!str9xpec_info
->isc_enable
) {
706 return ERROR_FLASH_OPERATION_FAILED
;
711 WARNING("offset 0x%x breaks required 8-byte alignment", offset
);
712 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
715 for (i
= 0; i
< bank
->num_sectors
; i
++)
717 u32 sec_start
= bank
->sectors
[i
].offset
;
718 u32 sec_end
= sec_start
+ bank
->sectors
[i
].size
;
720 /* check if destination falls within the current sector */
721 if ((check_address
>= sec_start
) && (check_address
< sec_end
))
723 /* check if destination ends in the current sector */
724 if (offset
+ count
< sec_end
)
725 check_address
= offset
+ count
;
727 check_address
= sec_end
;
730 if ((offset
>= sec_start
) && (offset
< sec_end
)){
734 if ((offset
+ count
>= sec_start
) && (offset
+ count
< sec_end
)){
739 if (check_address
!= offset
+ count
)
740 return ERROR_FLASH_DST_OUT_OF_BANK
;
742 DEBUG("first_sector: %i, last_sector: %i", first_sector
, last_sector
);
744 scanbuf
= calloc(CEIL(64, 8), 1);
746 DEBUG("ISC_PROGRAM");
748 for (i
= first_sector
; i
<= last_sector
; i
++)
750 str9xpec_set_address(bank
, str9xpec_info
->sector_bits
[i
]);
752 dwords_remaining
= dwords_remaining
< (bank
->sectors
[i
].size
/8) ? dwords_remaining
: (bank
->sectors
[i
].size
/8);
754 while (dwords_remaining
> 0)
756 str9xpec_set_instr(chain_pos
, ISC_PROGRAM
, TAP_PI
);
758 field
.device
= chain_pos
;
760 field
.out_value
= (buffer
+ bytes_written
);
761 field
.out_mask
= NULL
;
762 field
.in_value
= NULL
;
763 field
.in_check_value
= NULL
;
764 field
.in_check_mask
= NULL
;
765 field
.in_handler
= NULL
;
766 field
.in_handler_priv
= NULL
;
768 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
770 /* small delay before polling */
773 str9xpec_set_instr(chain_pos
, ISC_NOOP
, TAP_PI
);
776 field
.device
= chain_pos
;
778 field
.out_value
= NULL
;
779 field
.out_mask
= NULL
;
780 field
.in_value
= scanbuf
;
781 field
.in_check_value
= NULL
;
782 field
.in_check_mask
= NULL
;
783 field
.in_handler
= NULL
;
784 field
.in_handler_priv
= NULL
;
786 jtag_add_dr_scan(1, &field
, -1, NULL
);
787 jtag_execute_queue();
789 status
= buf_get_u32(scanbuf
, 0, 8);
791 } while(!(status
& ISC_STATUS_BUSY
));
793 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
794 return ERROR_FLASH_OPERATION_FAILED
;
796 //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
797 // return ERROR_FLASH_OPERATION_FAILED;
806 u8 last_dword
[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
809 while(bytes_remaining
> 0)
811 last_dword
[i
++] = *(buffer
+ bytes_written
);
816 str9xpec_set_instr(chain_pos
, ISC_PROGRAM
, TAP_PI
);
818 field
.device
= chain_pos
;
820 field
.out_value
= last_dword
;
821 field
.out_mask
= NULL
;
822 field
.in_value
= NULL
;
823 field
.in_check_value
= NULL
;
824 field
.in_check_mask
= NULL
;
825 field
.in_handler
= NULL
;
826 field
.in_handler_priv
= NULL
;
828 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
830 /* small delay before polling */
833 str9xpec_set_instr(chain_pos
, ISC_NOOP
, TAP_PI
);
836 field
.device
= chain_pos
;
838 field
.out_value
= NULL
;
839 field
.out_mask
= NULL
;
840 field
.in_value
= scanbuf
;
841 field
.in_check_value
= NULL
;
842 field
.in_check_mask
= NULL
;
843 field
.in_handler
= NULL
;
844 field
.in_handler_priv
= NULL
;
846 jtag_add_dr_scan(1, &field
, -1, NULL
);
847 jtag_execute_queue();
849 status
= buf_get_u32(scanbuf
, 0, 8);
851 } while(!(status
& ISC_STATUS_BUSY
));
853 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
854 return ERROR_FLASH_OPERATION_FAILED
;
856 //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
857 // return ERROR_FLASH_OPERATION_FAILED;
862 str9xpec_isc_disable(bank
);
867 int str9xpec_probe(struct flash_bank_s
*bank
)
872 int str9xpec_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
879 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
883 command_print(cmd_ctx
, "usage: str9xpec part_id <num>");
887 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
890 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
894 str9xpec_info
= bank
->driver_priv
;
895 chain_pos
= str9xpec_info
->chain_pos
;
897 buffer
= calloc(CEIL(32, 8), 1);
899 str9xpec_set_instr(chain_pos
, ISC_IDCODE
, TAP_PI
);
901 field
.device
= chain_pos
;
903 field
.out_value
= NULL
;
904 field
.out_mask
= NULL
;
905 field
.in_value
= buffer
;
906 field
.in_check_value
= NULL
;
907 field
.in_check_mask
= NULL
;
908 field
.in_handler
= NULL
;
909 field
.in_handler_priv
= NULL
;
911 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
912 jtag_execute_queue();
914 idcode
= buf_get_u32(buffer
, 0, 32);
916 command_print(cmd_ctx
, "str9xpec part id: 0x%8.8x", idcode
);
923 int str9xpec_erase_check(struct flash_bank_s
*bank
)
925 return str9xpec_blank_check(bank
, 0, bank
->num_sectors
- 1);
928 int str9xpec_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
930 snprintf(buf
, buf_size
, "str9xpec flash driver info" );
934 int str9xpec_handle_flash_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
938 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
942 command_print(cmd_ctx
, "str9xpec options_read <bank>");
946 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
949 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
953 str9xpec_info
= bank
->driver_priv
;
955 status
= str9xpec_read_config(bank
);
957 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
958 return ERROR_FLASH_OPERATION_FAILED
;
961 if (buf_get_u32(str9xpec_info
->options
, STR9XPEC_OPT_CSMAPBIT
, 1))
962 command_print(cmd_ctx
, "CS Map: bank1");
964 command_print(cmd_ctx
, "CS Map: bank0");
967 if (buf_get_u32(str9xpec_info
->options
, STR9XPEC_OPT_OTPBIT
, 1))
968 command_print(cmd_ctx
, "OTP Lock: OTP Locked");
970 command_print(cmd_ctx
, "OTP Lock: OTP Unlocked");
973 if (buf_get_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDTHRESBIT
, 1))
974 command_print(cmd_ctx
, "LVD Threshold: 2.7v");
976 command_print(cmd_ctx
, "LVD Threshold: 2.4v");
978 /* LVD reset warning */
979 if (buf_get_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDWARNBIT
, 1))
980 command_print(cmd_ctx
, "LVD Reset Warning: VDD or VDDQ Inputs");
982 command_print(cmd_ctx
, "LVD Reset Warning: VDD Input Only");
984 /* LVD reset select */
985 if (buf_get_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDSELBIT
, 1))
986 command_print(cmd_ctx
, "LVD Reset Selection: VDD or VDDQ Inputs");
988 command_print(cmd_ctx
, "LVD Reset Selection: VDD Input Only");
993 int str9xpec_write_options(struct flash_bank_s
*bank
)
998 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
1000 str9xpec_info
= bank
->driver_priv
;
1001 chain_pos
= str9xpec_info
->chain_pos
;
1003 /* erase config options first */
1004 status
= str9xpec_erase_area( bank
, 0xFE, 0xFE );
1006 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
1009 if (!str9xpec_info
->isc_enable
) {
1010 str9xpec_isc_enable( bank
);
1013 if (!str9xpec_info
->isc_enable
) {
1014 return ISC_STATUS_ERROR
;
1017 /* according to data 64th bit has to be set */
1018 buf_set_u32(str9xpec_info
->options
, 63, 1, 1);
1020 /* set option byte address */
1021 str9xpec_set_address(bank
, 0x50);
1023 /* execute ISC_PROGRAM command */
1024 str9xpec_set_instr(chain_pos
, ISC_PROGRAM
, TAP_PI
);
1026 field
.device
= chain_pos
;
1027 field
.num_bits
= 64;
1028 field
.out_value
= str9xpec_info
->options
;
1029 field
.out_mask
= NULL
;
1030 field
.in_value
= NULL
;
1031 field
.in_check_value
= NULL
;
1032 field
.in_check_mask
= NULL
;
1033 field
.in_handler
= NULL
;
1034 field
.in_handler_priv
= NULL
;
1036 jtag_add_dr_scan(1, &field
, TAP_RTI
, NULL
);
1038 /* small delay before polling */
1041 str9xpec_set_instr(chain_pos
, ISC_NOOP
, TAP_PI
);
1044 field
.device
= chain_pos
;
1046 field
.out_value
= NULL
;
1047 field
.out_mask
= NULL
;
1048 field
.in_value
= &status
;
1049 field
.in_check_value
= NULL
;
1050 field
.in_check_mask
= NULL
;
1051 field
.in_handler
= NULL
;
1052 field
.in_handler_priv
= NULL
;
1054 jtag_add_dr_scan(1, &field
, -1, NULL
);
1055 jtag_execute_queue();
1057 } while(!(status
& ISC_STATUS_BUSY
));
1059 str9xpec_isc_disable(bank
);
1064 int str9xpec_handle_flash_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1071 command_print(cmd_ctx
, "str9xpec options_write <bank>");
1075 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1078 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1082 status
= str9xpec_write_options(bank
);
1084 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
1085 return ERROR_FLASH_OPERATION_FAILED
;
1090 int str9xpec_handle_flash_options_cmap_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1093 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
1097 command_print(cmd_ctx
, "str9xpec options_cmap <bank> <bank0|bank1>");
1101 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1104 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1108 str9xpec_info
= bank
->driver_priv
;
1110 if (strcmp(args
[1], "bank1") == 0)
1112 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_CSMAPBIT
, 1, 1);
1116 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_CSMAPBIT
, 1, 0);
1122 int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1125 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
1129 command_print(cmd_ctx
, "str9xpec options_lvdthd <bank> <2.4v|2.7v>");
1133 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1136 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1140 str9xpec_info
= bank
->driver_priv
;
1142 if (strcmp(args
[1], "2.7v") == 0)
1144 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDTHRESBIT
, 1, 1);
1148 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDTHRESBIT
, 1, 0);
1154 int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1157 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
1161 command_print(cmd_ctx
, "str9xpec options_lvdsel <bank> <vdd|vdd_vddq>");
1165 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1168 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1172 str9xpec_info
= bank
->driver_priv
;
1174 if (strcmp(args
[1], "vdd_vddq") == 0)
1176 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDSELBIT
, 1, 1);
1180 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDSELBIT
, 1, 0);
1186 int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1189 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
1193 command_print(cmd_ctx
, "str9xpec options_lvdwarn <bank> <vdd|vdd_vddq>");
1197 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1200 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1204 str9xpec_info
= bank
->driver_priv
;
1206 if (strcmp(args
[1], "vdd_vddq") == 0)
1208 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDWARNBIT
, 1, 1);
1212 buf_set_u32(str9xpec_info
->options
, STR9XPEC_OPT_LVDWARNBIT
, 1, 0);
1218 int str9xpec_handle_flash_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1225 command_print(cmd_ctx
, "str9xpec lock <bank>");
1229 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1232 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1236 status
= str9xpec_lock_device(bank
);
1238 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
1239 return ERROR_FLASH_OPERATION_FAILED
;
1244 int str9xpec_handle_flash_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1251 command_print(cmd_ctx
, "str9xpec unlock <bank>");
1255 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1258 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1262 status
= str9xpec_unlock_device(bank
);
1264 if ((status
& ISC_STATUS_ERROR
) != STR9XPEC_ISC_SUCCESS
)
1265 return ERROR_FLASH_OPERATION_FAILED
;
1270 int str9xpec_handle_flash_enable_turbo_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1274 jtag_device_t
* dev0
;
1275 jtag_device_t
* dev2
;
1276 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
1280 command_print(cmd_ctx
, "str9xpec enable_turbo <bank>");
1284 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1287 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1291 str9xpec_info
= bank
->driver_priv
;
1293 chain_pos
= str9xpec_info
->chain_pos
;
1295 /* remove arm core from chain - enter turbo mode */
1297 str9xpec_set_instr(chain_pos
+2, 0xD, TAP_RTI
);
1298 jtag_execute_queue();
1300 /* modify scan chain - str9 core has been removed */
1301 dev0
= jtag_get_device(chain_pos
);
1302 str9xpec_info
->devarm
= jtag_get_device(chain_pos
+1);
1303 dev2
= jtag_get_device(chain_pos
+2);
1310 int str9xpec_handle_flash_disable_turbo_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1314 jtag_device_t
* dev0
;
1315 str9xpec_flash_controller_t
*str9xpec_info
= NULL
;
1319 command_print(cmd_ctx
, "str9xpec disable_turbo <bank>");
1323 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
1326 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
1330 str9xpec_info
= bank
->driver_priv
;
1332 chain_pos
= str9xpec_info
->chain_pos
;
1334 dev0
= jtag_get_device(chain_pos
);
1336 /* exit turbo mode via TLR */
1337 str9xpec_set_instr(chain_pos
, ISC_NOOP
, TAP_TLR
);
1338 jtag_execute_queue();
1340 /* restore previous scan chain */
1341 if( str9xpec_info
->devarm
) {
1342 dev0
->next
= str9xpec_info
->devarm
;
1344 str9xpec_info
->devarm
= NULL
;
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