1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2013 by Andes Technology *
5 * Hsiangkai Wang <hkwang@andestech.com> *
6 ***************************************************************************/
8 #ifndef OPENOCD_JTAG_AICE_AICE_PORT_H
9 #define OPENOCD_JTAG_AICE_AICE_PORT_H
11 #include <target/nds32_edm.h>
13 #define AICE_MAX_NUM_CORE (0x10)
15 #define ERROR_AICE_DISCONNECT (-200)
16 #define ERROR_AICE_TIMEOUT (-201)
18 enum aice_target_state_s
{
25 AICE_TARGET_DEBUG_RUNNING
,
28 enum aice_srst_type_s
{
30 AICE_RESET_HOLD
= 0x8,
33 enum aice_target_endian
{
34 AICE_LITTLE_ENDIAN
= 0,
65 AICE_SET_COMMAND_MODE
,
67 AICE_SET_CUSTOM_SRST_SCRIPT
,
68 AICE_SET_CUSTOM_TRST_SCRIPT
,
69 AICE_SET_CUSTOM_RESTART_SCRIPT
,
70 AICE_SET_COUNT_TO_CHECK_DBGER
,
80 enum aice_cache_ctl_type
{
81 AICE_CACHE_CTL_L1D_INVALALL
= 0,
82 AICE_CACHE_CTL_L1D_VA_INVAL
,
83 AICE_CACHE_CTL_L1D_WBALL
,
84 AICE_CACHE_CTL_L1D_VA_WB
,
85 AICE_CACHE_CTL_L1I_INVALALL
,
86 AICE_CACHE_CTL_L1I_VA_INVAL
,
89 enum aice_command_mode
{
90 AICE_COMMAND_MODE_NORMAL
,
91 AICE_COMMAND_MODE_PACK
,
92 AICE_COMMAND_MODE_BATCH
,
95 struct aice_port_param_s
{
97 const char *device_desc
;
110 const struct aice_port
*port
;
114 extern struct aice_port_api_s aice_usb_layout_api
;
117 struct aice_port_api_s
{
119 int (*open
)(struct aice_port_param_s
*param
);
125 int (*idcode
)(uint32_t *idcode
, uint8_t *num_of_idcode
);
127 int (*set_jtag_clock
)(uint32_t a_clock
);
129 int (*assert_srst
)(uint32_t coreid
, enum aice_srst_type_s srst
);
131 int (*run
)(uint32_t coreid
);
133 int (*halt
)(uint32_t coreid
);
135 int (*step
)(uint32_t coreid
);
137 int (*read_reg
)(uint32_t coreid
, uint32_t num
, uint32_t *val
);
139 int (*write_reg
)(uint32_t coreid
, uint32_t num
, uint32_t val
);
141 int (*read_reg_64
)(uint32_t coreid
, uint32_t num
, uint64_t *val
);
143 int (*write_reg_64
)(uint32_t coreid
, uint32_t num
, uint64_t val
);
145 int (*read_mem_unit
)(uint32_t coreid
, uint32_t addr
, uint32_t size
,
146 uint32_t count
, uint8_t *buffer
);
148 int (*write_mem_unit
)(uint32_t coreid
, uint32_t addr
, uint32_t size
,
149 uint32_t count
, const uint8_t *buffer
);
151 int (*read_mem_bulk
)(uint32_t coreid
, uint32_t addr
, uint32_t length
,
154 int (*write_mem_bulk
)(uint32_t coreid
, uint32_t addr
, uint32_t length
,
155 const uint8_t *buffer
);
157 int (*read_debug_reg
)(uint32_t coreid
, uint32_t addr
, uint32_t *val
);
159 int (*write_debug_reg
)(uint32_t coreid
, uint32_t addr
, const uint32_t val
);
162 int (*state
)(uint32_t coreid
, enum aice_target_state_s
*state
);
165 int (*memory_access
)(uint32_t coreid
, enum nds_memory_access a_access
);
167 int (*memory_mode
)(uint32_t coreid
, enum nds_memory_select mem_select
);
170 int (*read_tlb
)(uint32_t coreid
, target_addr_t virtual_address
, target_addr_t
*physical_address
);
173 int (*cache_ctl
)(uint32_t coreid
, uint32_t subtype
, uint32_t address
);
176 int (*set_retry_times
)(uint32_t a_retry_times
);
179 int (*program_edm
)(uint32_t coreid
, char *command_sequence
);
182 int (*set_command_mode
)(enum aice_command_mode command_mode
);
185 int (*execute
)(uint32_t coreid
, uint32_t *instructions
, uint32_t instruction_num
);
188 int (*set_custom_srst_script
)(const char *script
);
191 int (*set_custom_trst_script
)(const char *script
);
194 int (*set_custom_restart_script
)(const char *script
);
197 int (*set_count_to_check_dbger
)(uint32_t count_to_check
);
200 int (*set_data_endian
)(uint32_t coreid
, enum aice_target_endian target_data_endian
);
203 int (*profiling
)(uint32_t coreid
, uint32_t interval
, uint32_t iteration
,
204 uint32_t reg_no
, uint32_t *samples
, uint32_t *num_samples
);
207 #define AICE_PORT_UNKNOWN 0
208 #define AICE_PORT_AICE_USB 1
209 #define AICE_PORT_AICE_PIPE 2
218 struct aice_port_api_s
*const api
;
222 const struct aice_port
*aice_port_get_list(void);
224 #endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */
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