1 /***************************************************************************
2 * Copyright (C) 2013 by Paul Fertser, fercerpav@gmail.com *
4 * Copyright (C) 2012 by Creative Product Design, marc @ cpdesign.com.au *
5 * Based on at91rm9200.c (c) Anders Larsen *
6 * and RPi GPIO examples by Gert van Loo & Dom *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
28 #include <jtag/interface.h>
33 #define BCM2835_PERI_BASE 0x20000000
34 #define BCM2835_GPIO_BASE (BCM2835_PERI_BASE + 0x200000) /* GPIO controller */
36 #define BCM2835_PADS_GPIO_0_27 (BCM2835_PERI_BASE + 0x100000)
37 #define BCM2835_PADS_GPIO_0_27_OFFSET (0x2c / 4)
39 /* GPIO setup macros */
40 #define MODE_GPIO(g) (*(pio_base+((g)/10))>>(((g)%10)*3) & 7)
41 #define INP_GPIO(g) do { *(pio_base+((g)/10)) &= ~(7<<(((g)%10)*3)); } while (0)
42 #define SET_MODE_GPIO(g, m) do { /* clear the mode bits first, then set as necessary */ \
44 *(pio_base+((g)/10)) |= ((m)<<(((g)%10)*3)); } while (0)
45 #define OUT_GPIO(g) SET_MODE_GPIO(g, 1)
47 #define GPIO_SET (*(pio_base+7)) /* sets bits which are 1, ignores bits which are 0 */
48 #define GPIO_CLR (*(pio_base+10)) /* clears bits which are 1, ignores bits which are 0 */
49 #define GPIO_LEV (*(pio_base+13)) /* current level of the pin */
51 static int dev_mem_fd
;
52 static volatile uint32_t *pio_base
;
54 static int bcm2835gpio_read(void);
55 static void bcm2835gpio_write(int tck
, int tms
, int tdi
);
56 static void bcm2835gpio_reset(int trst
, int srst
);
58 static int bcm2835gpio_init(void);
59 static int bcm2835gpio_quit(void);
61 static struct bitbang_interface bcm2835gpio_bitbang
= {
62 .read
= bcm2835gpio_read
,
63 .write
= bcm2835gpio_write
,
64 .reset
= bcm2835gpio_reset
,
68 /* GPIO numbers for each signal. Negative values are invalid */
69 static int tck_gpio
= -1;
70 static int tck_gpio_mode
;
71 static int tms_gpio
= -1;
72 static int tms_gpio_mode
;
73 static int tdi_gpio
= -1;
74 static int tdi_gpio_mode
;
75 static int tdo_gpio
= -1;
76 static int tdo_gpio_mode
;
77 static int trst_gpio
= -1;
78 static int trst_gpio_mode
;
79 static int srst_gpio
= -1;
80 static int srst_gpio_mode
;
82 /* Transition delay coefficients */
83 static int speed_coeff
= 113714;
84 static int speed_offset
= 28;
85 static unsigned int jtag_delay
;
87 static int bcm2835gpio_read(void)
89 return !!(GPIO_LEV
& 1<<tdo_gpio
);
92 static void bcm2835gpio_write(int tck
, int tms
, int tdi
)
94 uint32_t set
= tck
<<tck_gpio
| tms
<<tms_gpio
| tdi
<<tdi_gpio
;
95 uint32_t clear
= !tck
<<tck_gpio
| !tms
<<tms_gpio
| !tdi
<<tdi_gpio
;
100 for (unsigned int i
= 0; i
< jtag_delay
; i
++)
104 /* (1) assert or (0) deassert reset lines */
105 static void bcm2835gpio_reset(int trst
, int srst
)
111 set
|= !trst
<<trst_gpio
;
112 clear
|= trst
<<trst_gpio
;
116 set
|= !srst
<<srst_gpio
;
117 clear
|= srst
<<srst_gpio
;
124 static int bcm2835gpio_khz(int khz
, int *jtag_speed
)
127 LOG_DEBUG("RCLK not supported");
130 *jtag_speed
= speed_coeff
/khz
- speed_offset
;
136 static int bcm2835gpio_speed_div(int speed
, int *khz
)
138 *khz
= speed_coeff
/(speed
+ speed_offset
);
142 static int bcm2835gpio_speed(int speed
)
148 static int is_gpio_valid(int gpio
)
150 return gpio
>= 0 && gpio
<= 53;
153 COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionums
)
156 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], tck_gpio
);
157 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], tms_gpio
);
158 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[2], tdi_gpio
);
159 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[3], tdo_gpio
);
160 } else if (CMD_ARGC
!= 0) {
161 return ERROR_COMMAND_SYNTAX_ERROR
;
164 command_print(CMD_CTX
,
165 "BCM2835 GPIO config: tck = %d, tms = %d, tdi = %d, tdi = %d",
166 tck_gpio
, tms_gpio
, tdi_gpio
, tdo_gpio
);
171 COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tck
)
174 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], tck_gpio
);
176 command_print(CMD_CTX
, "BCM2835 GPIO config: tck = %d", tck_gpio
);
180 COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tms
)
183 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], tms_gpio
);
185 command_print(CMD_CTX
, "BCM2835 GPIO config: tms = %d", tms_gpio
);
189 COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tdo
)
192 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], tdo_gpio
);
194 command_print(CMD_CTX
, "BCM2835 GPIO config: tdo = %d", tdo_gpio
);
198 COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tdi
)
201 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], tdi_gpio
);
203 command_print(CMD_CTX
, "BCM2835 GPIO config: tdi = %d", tdi_gpio
);
207 COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_srst
)
210 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], srst_gpio
);
212 command_print(CMD_CTX
, "BCM2835 GPIO config: srst = %d", srst_gpio
);
216 COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_trst
)
219 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], trst_gpio
);
221 command_print(CMD_CTX
, "BCM2835 GPIO config: trst = %d", trst_gpio
);
225 COMMAND_HANDLER(bcm2835gpio_handle_speed_coeffs
)
228 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], speed_coeff
);
229 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], speed_offset
);
234 static const struct command_registration bcm2835gpio_command_handlers
[] = {
236 .name
= "bcm2835gpio_jtag_nums",
237 .handler
= &bcm2835gpio_handle_jtag_gpionums
,
238 .mode
= COMMAND_CONFIG
,
239 .help
= "gpio numbers for tck, tms, tdi, tdo. (in that order)",
240 .usage
= "(tck tms tdi tdo)* ",
243 .name
= "bcm2835gpio_tck_num",
244 .handler
= &bcm2835gpio_handle_jtag_gpionum_tck
,
245 .mode
= COMMAND_CONFIG
,
246 .help
= "gpio number for tck.",
249 .name
= "bcm2835gpio_tms_num",
250 .handler
= &bcm2835gpio_handle_jtag_gpionum_tms
,
251 .mode
= COMMAND_CONFIG
,
252 .help
= "gpio number for tms.",
255 .name
= "bcm2835gpio_tdo_num",
256 .handler
= &bcm2835gpio_handle_jtag_gpionum_tdo
,
257 .mode
= COMMAND_CONFIG
,
258 .help
= "gpio number for tdo.",
261 .name
= "bcm2835gpio_tdi_num",
262 .handler
= &bcm2835gpio_handle_jtag_gpionum_tdi
,
263 .mode
= COMMAND_CONFIG
,
264 .help
= "gpio number for tdi.",
267 .name
= "bcm2835gpio_srst_num",
268 .handler
= &bcm2835gpio_handle_jtag_gpionum_srst
,
269 .mode
= COMMAND_CONFIG
,
270 .help
= "gpio number for srst.",
273 .name
= "bcm2835gpio_trst_num",
274 .handler
= &bcm2835gpio_handle_jtag_gpionum_trst
,
275 .mode
= COMMAND_CONFIG
,
276 .help
= "gpio number for trst.",
279 .name
= "bcm2835gpio_speed_coeffs",
280 .handler
= &bcm2835gpio_handle_speed_coeffs
,
281 .mode
= COMMAND_CONFIG
,
282 .help
= "SPEED_COEFF and SPEED_OFFSET for delay calculations.",
284 COMMAND_REGISTRATION_DONE
287 struct jtag_interface bcm2835gpio_interface
= {
288 .name
= "bcm2835gpio",
289 .supported
= DEBUG_CAP_TMS_SEQ
,
290 .execute_queue
= bitbang_execute_queue
,
291 .transports
= jtag_only
,
292 .speed
= bcm2835gpio_speed
,
293 .khz
= bcm2835gpio_khz
,
294 .speed_div
= bcm2835gpio_speed_div
,
295 .commands
= bcm2835gpio_command_handlers
,
296 .init
= bcm2835gpio_init
,
297 .quit
= bcm2835gpio_quit
,
300 static int bcm2835gpio_init(void)
302 bitbang_interface
= &bcm2835gpio_bitbang
;
304 if (!is_gpio_valid(tdo_gpio
) || !is_gpio_valid(tdi_gpio
) ||
305 !is_gpio_valid(tck_gpio
) || !is_gpio_valid(tms_gpio
) ||
306 (trst_gpio
!= -1 && !is_gpio_valid(trst_gpio
)) ||
307 (srst_gpio
!= -1 && !is_gpio_valid(srst_gpio
)))
308 return ERROR_JTAG_INIT_FAILED
;
310 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
311 if (dev_mem_fd
< 0) {
313 return ERROR_JTAG_INIT_FAILED
;
316 pio_base
= mmap(NULL
, sysconf(_SC_PAGE_SIZE
), PROT_READ
| PROT_WRITE
,
317 MAP_SHARED
, dev_mem_fd
, BCM2835_GPIO_BASE
);
319 if (pio_base
== MAP_FAILED
) {
322 return ERROR_JTAG_INIT_FAILED
;
325 static volatile uint32_t *pads_base
;
326 pads_base
= mmap(NULL
, sysconf(_SC_PAGE_SIZE
), PROT_READ
| PROT_WRITE
,
327 MAP_SHARED
, dev_mem_fd
, BCM2835_PADS_GPIO_0_27
);
329 if (pads_base
== MAP_FAILED
) {
332 return ERROR_JTAG_INIT_FAILED
;
335 /* set 16mA drive strength */
336 pads_base
[BCM2835_PADS_GPIO_0_27_OFFSET
] = 0x5a000018 + 7;
338 tdo_gpio_mode
= MODE_GPIO(tdo_gpio
);
339 tdi_gpio_mode
= MODE_GPIO(tdi_gpio
);
340 tck_gpio_mode
= MODE_GPIO(tck_gpio
);
341 tms_gpio_mode
= MODE_GPIO(tms_gpio
);
343 * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
344 * as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
348 GPIO_CLR
= 1<<tdi_gpio
| 1<<tck_gpio
;
349 GPIO_SET
= 1<<tms_gpio
;
354 if (trst_gpio
!= -1) {
355 trst_gpio_mode
= MODE_GPIO(trst_gpio
);
356 GPIO_SET
= 1 << trst_gpio
;
359 if (srst_gpio
!= -1) {
360 srst_gpio_mode
= MODE_GPIO(srst_gpio
);
361 GPIO_SET
= 1 << srst_gpio
;
365 LOG_DEBUG("saved pinmux settings: tck %d tms %d tdi %d "
366 "tdo %d trst %d srst %d", tck_gpio_mode
, tms_gpio_mode
,
367 tdi_gpio_mode
, tdo_gpio_mode
, trst_gpio_mode
, srst_gpio_mode
);
372 static int bcm2835gpio_quit(void)
374 SET_MODE_GPIO(tdo_gpio
, tdo_gpio_mode
);
375 SET_MODE_GPIO(tdi_gpio
, tdi_gpio_mode
);
376 SET_MODE_GPIO(tck_gpio
, tck_gpio_mode
);
377 SET_MODE_GPIO(tms_gpio
, tms_gpio_mode
);
379 SET_MODE_GPIO(trst_gpio
, trst_gpio_mode
);
381 SET_MODE_GPIO(srst_gpio
, srst_gpio_mode
);
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