jtag/drivers: bcm2835gpio: implement memory barriers when bitbashing
[openocd.git] / src / jtag / drivers / bcm2835gpio.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013 by Paul Fertser, fercerpav@gmail.com *
5 * *
6 * Copyright (C) 2012 by Creative Product Design, marc @ cpdesign.com.au *
7 * Based on at91rm9200.c (c) Anders Larsen *
8 * and RPi GPIO examples by Gert van Loo & Dom *
9 ***************************************************************************/
10
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14
15 #include <jtag/adapter.h>
16 #include <jtag/interface.h>
17 #include <transport/transport.h>
18 #include "bitbang.h"
19
20 #include <sys/mman.h>
21
22 uint32_t bcm2835_peri_base = 0x20000000;
23 #define BCM2835_GPIO_BASE (bcm2835_peri_base + 0x200000) /* GPIO controller */
24
25 #define BCM2835_PADS_GPIO_0_27 (bcm2835_peri_base + 0x100000)
26 #define BCM2835_PADS_GPIO_0_27_OFFSET (0x2c / 4)
27
28 /* See "GPIO Function Select Registers (GPFSELn)" in "Broadcom BCM2835 ARM Peripherals" datasheet. */
29 #define BCM2835_GPIO_MODE_INPUT 0
30 #define BCM2835_GPIO_MODE_OUTPUT 1
31
32 /* GPIO setup macros */
33 #define MODE_GPIO(g) (*(pio_base+((g)/10))>>(((g)%10)*3) & 7)
34 #define INP_GPIO(g) do { *(pio_base+((g)/10)) &= ~(7<<(((g)%10)*3)); } while (0)
35 #define SET_MODE_GPIO(g, m) do { /* clear the mode bits first, then set as necessary */ \
36 INP_GPIO(g); \
37 *(pio_base+((g)/10)) |= ((m)<<(((g)%10)*3)); } while (0)
38 #define OUT_GPIO(g) SET_MODE_GPIO(g, BCM2835_GPIO_MODE_OUTPUT)
39
40 #define GPIO_SET (*(pio_base+7)) /* sets bits which are 1, ignores bits which are 0 */
41 #define GPIO_CLR (*(pio_base+10)) /* clears bits which are 1, ignores bits which are 0 */
42 #define GPIO_LEV (*(pio_base+13)) /* current level of the pin */
43
44 static int dev_mem_fd;
45 static volatile uint32_t *pio_base = MAP_FAILED;
46 static volatile uint32_t *pads_base = MAP_FAILED;
47
48 /* Transition delay coefficients */
49 static int speed_coeff = 113714;
50 static int speed_offset = 28;
51 static unsigned int jtag_delay;
52
53 static const struct adapter_gpio_config *adapter_gpio_config;
54 static struct initial_gpio_state {
55 unsigned int mode;
56 unsigned int output_level;
57 } initial_gpio_state[ADAPTER_GPIO_IDX_NUM];
58 static uint32_t initial_drive_strength_etc;
59
60 static inline void bcm2835_gpio_synchronize(void)
61 {
62 /* Ensure that previous writes to GPIO registers are flushed out of
63 * the inner shareable domain to prevent pipelined writes to the
64 * same address being merged.
65 */
66 __sync_synchronize();
67 }
68
69 static bool is_gpio_config_valid(enum adapter_gpio_config_index idx)
70 {
71 /* Only chip 0 is supported, accept unset value (-1) too */
72 return adapter_gpio_config[idx].chip_num >= -1
73 && adapter_gpio_config[idx].chip_num <= 0
74 && adapter_gpio_config[idx].gpio_num >= 0
75 && adapter_gpio_config[idx].gpio_num <= 31;
76 }
77
78 static void set_gpio_value(const struct adapter_gpio_config *gpio_config, int value)
79 {
80 value = value ^ (gpio_config->active_low ? 1 : 0);
81 switch (gpio_config->drive) {
82 case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL:
83 if (value)
84 GPIO_SET = 1 << gpio_config->gpio_num;
85 else
86 GPIO_CLR = 1 << gpio_config->gpio_num;
87 /* For performance reasons assume the GPIO is already set as an output
88 * and therefore the call can be omitted here.
89 */
90 break;
91 case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN:
92 if (value) {
93 INP_GPIO(gpio_config->gpio_num);
94 } else {
95 GPIO_CLR = 1 << gpio_config->gpio_num;
96 OUT_GPIO(gpio_config->gpio_num);
97 }
98 break;
99 case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE:
100 if (value) {
101 GPIO_SET = 1 << gpio_config->gpio_num;
102 OUT_GPIO(gpio_config->gpio_num);
103 } else {
104 INP_GPIO(gpio_config->gpio_num);
105 }
106 break;
107 }
108 bcm2835_gpio_synchronize();
109 }
110
111 static void restore_gpio(enum adapter_gpio_config_index idx)
112 {
113 if (is_gpio_config_valid(idx)) {
114 SET_MODE_GPIO(adapter_gpio_config[idx].gpio_num, initial_gpio_state[idx].mode);
115 if (initial_gpio_state[idx].mode == BCM2835_GPIO_MODE_OUTPUT) {
116 if (initial_gpio_state[idx].output_level)
117 GPIO_SET = 1 << adapter_gpio_config[idx].gpio_num;
118 else
119 GPIO_CLR = 1 << adapter_gpio_config[idx].gpio_num;
120 }
121 }
122 bcm2835_gpio_synchronize();
123 }
124
125 static void initialize_gpio(enum adapter_gpio_config_index idx)
126 {
127 if (!is_gpio_config_valid(idx))
128 return;
129
130 initial_gpio_state[idx].mode = MODE_GPIO(adapter_gpio_config[idx].gpio_num);
131 unsigned int shift = adapter_gpio_config[idx].gpio_num;
132 initial_gpio_state[idx].output_level = (GPIO_LEV >> shift) & 1;
133 LOG_DEBUG("saved GPIO mode for %s (GPIO %d %d): %d",
134 adapter_gpio_get_name(idx), adapter_gpio_config[idx].chip_num, adapter_gpio_config[idx].gpio_num,
135 initial_gpio_state[idx].mode);
136
137 if (adapter_gpio_config[idx].pull != ADAPTER_GPIO_PULL_NONE) {
138 LOG_WARNING("BCM2835 GPIO does not support pull-up or pull-down settings (signal %s)",
139 adapter_gpio_get_name(idx));
140 }
141
142 switch (adapter_gpio_config[idx].init_state) {
143 case ADAPTER_GPIO_INIT_STATE_INACTIVE:
144 set_gpio_value(&adapter_gpio_config[idx], 0);
145 break;
146 case ADAPTER_GPIO_INIT_STATE_ACTIVE:
147 set_gpio_value(&adapter_gpio_config[idx], 1);
148 break;
149 case ADAPTER_GPIO_INIT_STATE_INPUT:
150 INP_GPIO(adapter_gpio_config[idx].gpio_num);
151 break;
152 }
153
154 /* Direction for non push-pull is already set by set_gpio_value() */
155 if (adapter_gpio_config[idx].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL)
156 OUT_GPIO(adapter_gpio_config[idx].gpio_num);
157 bcm2835_gpio_synchronize();
158 }
159
160 static bb_value_t bcm2835gpio_read(void)
161 {
162 unsigned int shift = adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].gpio_num;
163 uint32_t value = (GPIO_LEV >> shift) & 1;
164 return value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].active_low ? BB_HIGH : BB_LOW);
165
166 }
167
168 static int bcm2835gpio_write(int tck, int tms, int tdi)
169 {
170 uint32_t set = tck << adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num |
171 tms << adapter_gpio_config[ADAPTER_GPIO_IDX_TMS].gpio_num |
172 tdi << adapter_gpio_config[ADAPTER_GPIO_IDX_TDI].gpio_num;
173 uint32_t clear = !tck << adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num |
174 !tms << adapter_gpio_config[ADAPTER_GPIO_IDX_TMS].gpio_num |
175 !tdi << adapter_gpio_config[ADAPTER_GPIO_IDX_TDI].gpio_num;
176
177 GPIO_SET = set;
178 GPIO_CLR = clear;
179 bcm2835_gpio_synchronize();
180
181 for (unsigned int i = 0; i < jtag_delay; i++)
182 asm volatile ("");
183
184 return ERROR_OK;
185 }
186
187 /* Requires push-pull drive mode for swclk and swdio */
188 static int bcm2835gpio_swd_write_fast(int swclk, int swdio)
189 {
190 swclk = swclk ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].active_low ? 1 : 0);
191 swdio = swdio ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low ? 1 : 0);
192
193 uint32_t set = swclk << adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].gpio_num |
194 swdio << adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num;
195 uint32_t clear = !swclk << adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].gpio_num |
196 !swdio << adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num;
197
198 GPIO_SET = set;
199 GPIO_CLR = clear;
200 bcm2835_gpio_synchronize();
201
202 for (unsigned int i = 0; i < jtag_delay; i++)
203 asm volatile ("");
204
205 return ERROR_OK;
206 }
207
208 /* Generic mode that works for open-drain/open-source drive modes, but slower */
209 static int bcm2835gpio_swd_write_generic(int swclk, int swdio)
210 {
211 set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO], swdio);
212 set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK], swclk); /* Write clock last */
213
214 for (unsigned int i = 0; i < jtag_delay; ++i)
215 asm volatile ("");
216
217 return ERROR_OK;
218 }
219
220 /* (1) assert or (0) deassert reset lines */
221 static int bcm2835gpio_reset(int trst, int srst)
222 {
223 /* As the "adapter reset_config" command keeps the srst and trst gpio drive
224 * mode settings in sync we can use our standard set_gpio_value() function
225 * that honours drive mode and active low.
226 */
227 if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SRST))
228 set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SRST], srst);
229
230 if (is_gpio_config_valid(ADAPTER_GPIO_IDX_TRST))
231 set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TRST], trst);
232
233 LOG_DEBUG("BCM2835 GPIO: bcm2835gpio_reset(%d, %d), trst_gpio: %d %d, srst_gpio: %d %d",
234 trst, srst,
235 adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].chip_num, adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].gpio_num,
236 adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].chip_num, adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].gpio_num);
237 return ERROR_OK;
238 }
239
240 static void bcm2835_swdio_drive(bool is_output)
241 {
242 if (is_output) {
243 if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO_DIR))
244 set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 1);
245 OUT_GPIO(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);
246 } else {
247 INP_GPIO(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);
248 if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO_DIR))
249 set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 0);
250 }
251 bcm2835_gpio_synchronize();
252 }
253
254 static int bcm2835_swdio_read(void)
255 {
256 unsigned int shift = adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num;
257 uint32_t value = (GPIO_LEV >> shift) & 1;
258 return value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low ? 1 : 0);
259 }
260
261 static int bcm2835gpio_khz(int khz, int *jtag_speed)
262 {
263 if (!khz) {
264 LOG_DEBUG("BCM2835 GPIO: RCLK not supported");
265 return ERROR_FAIL;
266 }
267 *jtag_speed = speed_coeff/khz - speed_offset;
268 if (*jtag_speed < 0)
269 *jtag_speed = 0;
270 return ERROR_OK;
271 }
272
273 static int bcm2835gpio_speed_div(int speed, int *khz)
274 {
275 *khz = speed_coeff/(speed + speed_offset);
276 return ERROR_OK;
277 }
278
279 static int bcm2835gpio_speed(int speed)
280 {
281 jtag_delay = speed;
282 return ERROR_OK;
283 }
284
285 COMMAND_HANDLER(bcm2835gpio_handle_speed_coeffs)
286 {
287 if (CMD_ARGC == 2) {
288 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], speed_coeff);
289 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], speed_offset);
290 }
291
292 command_print(CMD, "BCM2835 GPIO: speed_coeffs = %d, speed_offset = %d",
293 speed_coeff, speed_offset);
294 return ERROR_OK;
295 }
296
297 COMMAND_HANDLER(bcm2835gpio_handle_peripheral_base)
298 {
299 if (CMD_ARGC == 1)
300 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bcm2835_peri_base);
301
302 command_print(CMD, "BCM2835 GPIO: peripheral_base = 0x%08x",
303 bcm2835_peri_base);
304 return ERROR_OK;
305 }
306
307 static const struct command_registration bcm2835gpio_subcommand_handlers[] = {
308 {
309 .name = "speed_coeffs",
310 .handler = &bcm2835gpio_handle_speed_coeffs,
311 .mode = COMMAND_CONFIG,
312 .help = "SPEED_COEFF and SPEED_OFFSET for delay calculations.",
313 .usage = "[SPEED_COEFF SPEED_OFFSET]",
314 },
315 {
316 .name = "peripheral_base",
317 .handler = &bcm2835gpio_handle_peripheral_base,
318 .mode = COMMAND_CONFIG,
319 .help = "peripheral base to access GPIOs (RPi1 0x20000000, RPi2 0x3F000000).",
320 .usage = "[base]",
321 },
322
323 COMMAND_REGISTRATION_DONE
324 };
325
326 static const struct command_registration bcm2835gpio_command_handlers[] = {
327 {
328 .name = "bcm2835gpio",
329 .mode = COMMAND_ANY,
330 .help = "perform bcm2835gpio management",
331 .chain = bcm2835gpio_subcommand_handlers,
332 .usage = "",
333 },
334 COMMAND_REGISTRATION_DONE
335 };
336
337 static bool bcm2835gpio_jtag_mode_possible(void)
338 {
339 if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TCK))
340 return false;
341 if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TMS))
342 return false;
343 if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDI))
344 return false;
345 if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDO))
346 return false;
347 return true;
348 }
349
350 static bool bcm2835gpio_swd_mode_possible(void)
351 {
352 if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWCLK))
353 return false;
354 if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO))
355 return false;
356 return true;
357 }
358
359 static void bcm2835gpio_munmap(void)
360 {
361 if (pio_base != MAP_FAILED) {
362 munmap((void *)pio_base, sysconf(_SC_PAGE_SIZE));
363 pio_base = MAP_FAILED;
364 }
365
366 if (pads_base != MAP_FAILED) {
367 munmap((void *)pads_base, sysconf(_SC_PAGE_SIZE));
368 pads_base = MAP_FAILED;
369 }
370 }
371
372 static int bcm2835gpio_blink(int on)
373 {
374 if (is_gpio_config_valid(ADAPTER_GPIO_IDX_LED))
375 set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_LED], on);
376
377 return ERROR_OK;
378 }
379
380 static struct bitbang_interface bcm2835gpio_bitbang = {
381 .read = bcm2835gpio_read,
382 .write = bcm2835gpio_write,
383 .swdio_read = bcm2835_swdio_read,
384 .swdio_drive = bcm2835_swdio_drive,
385 .swd_write = bcm2835gpio_swd_write_generic,
386 .blink = bcm2835gpio_blink,
387 };
388
389 static int bcm2835gpio_init(void)
390 {
391 LOG_INFO("BCM2835 GPIO JTAG/SWD bitbang driver");
392
393 bitbang_interface = &bcm2835gpio_bitbang;
394 adapter_gpio_config = adapter_gpio_get_config();
395
396 if (transport_is_jtag() && !bcm2835gpio_jtag_mode_possible()) {
397 LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
398 return ERROR_JTAG_INIT_FAILED;
399 }
400
401 if (transport_is_swd() && !bcm2835gpio_swd_mode_possible()) {
402 LOG_ERROR("Require swclk and swdio gpio for SWD mode");
403 return ERROR_JTAG_INIT_FAILED;
404 }
405
406 dev_mem_fd = open("/dev/gpiomem", O_RDWR | O_SYNC);
407 if (dev_mem_fd < 0) {
408 LOG_DEBUG("Cannot open /dev/gpiomem, fallback to /dev/mem");
409 dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
410 }
411 if (dev_mem_fd < 0) {
412 LOG_ERROR("open: %s", strerror(errno));
413 return ERROR_JTAG_INIT_FAILED;
414 }
415
416 pio_base = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE,
417 MAP_SHARED, dev_mem_fd, BCM2835_GPIO_BASE);
418
419 if (pio_base == MAP_FAILED) {
420 LOG_ERROR("mmap: %s", strerror(errno));
421 close(dev_mem_fd);
422 return ERROR_JTAG_INIT_FAILED;
423 }
424
425 pads_base = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE,
426 MAP_SHARED, dev_mem_fd, BCM2835_PADS_GPIO_0_27);
427
428 if (pads_base == MAP_FAILED) {
429 LOG_ERROR("mmap: %s", strerror(errno));
430 bcm2835gpio_munmap();
431 close(dev_mem_fd);
432 return ERROR_JTAG_INIT_FAILED;
433 }
434
435 close(dev_mem_fd);
436
437 /* set 4mA drive strength, slew rate limited, hysteresis on */
438 initial_drive_strength_etc = pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] & 0x1f;
439 pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] = 0x5a000008 + 1;
440
441 /* Configure JTAG/SWD signals. Default directions and initial states are handled
442 * by adapter.c and "adapter gpio" command.
443 */
444 if (transport_is_jtag()) {
445 initialize_gpio(ADAPTER_GPIO_IDX_TDO);
446 initialize_gpio(ADAPTER_GPIO_IDX_TDI);
447 initialize_gpio(ADAPTER_GPIO_IDX_TMS);
448 initialize_gpio(ADAPTER_GPIO_IDX_TCK);
449 initialize_gpio(ADAPTER_GPIO_IDX_TRST);
450 }
451
452 if (transport_is_swd()) {
453 /* swdio and its buffer should be initialized in the order that prevents
454 * two outputs from being connected together. This will occur if the
455 * swdio GPIO of the AM335x is configured as an output while its
456 * external buffer is configured to send the swdio signal from the
457 * target to the AM335x.
458 */
459 if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].init_state == ADAPTER_GPIO_INIT_STATE_INPUT) {
460 initialize_gpio(ADAPTER_GPIO_IDX_SWDIO);
461 initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR);
462 } else {
463 initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR);
464 initialize_gpio(ADAPTER_GPIO_IDX_SWDIO);
465 }
466
467 initialize_gpio(ADAPTER_GPIO_IDX_SWCLK);
468
469 if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL &&
470 adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL) {
471 LOG_DEBUG("BCM2835 GPIO using fast mode for SWD write");
472 bcm2835gpio_bitbang.swd_write = bcm2835gpio_swd_write_fast;
473 } else {
474 LOG_DEBUG("BCM2835 GPIO using generic mode for SWD write");
475 bcm2835gpio_bitbang.swd_write = bcm2835gpio_swd_write_generic;
476 }
477 }
478
479 initialize_gpio(ADAPTER_GPIO_IDX_SRST);
480 initialize_gpio(ADAPTER_GPIO_IDX_LED);
481
482 return ERROR_OK;
483 }
484
485 static int bcm2835gpio_quit(void)
486 {
487 if (transport_is_jtag()) {
488 restore_gpio(ADAPTER_GPIO_IDX_TDO);
489 restore_gpio(ADAPTER_GPIO_IDX_TDI);
490 restore_gpio(ADAPTER_GPIO_IDX_TCK);
491 restore_gpio(ADAPTER_GPIO_IDX_TMS);
492 restore_gpio(ADAPTER_GPIO_IDX_TRST);
493 }
494
495 if (transport_is_swd()) {
496 /* Restore swdio/swdio_dir to their initial modes, even if that means
497 * connecting two outputs. Begin by making swdio an input so that the
498 * current and final states of swdio and swdio_dir do not have to be
499 * considered to calculate the safe restoration order.
500 */
501 INP_GPIO(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);
502 restore_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR);
503 restore_gpio(ADAPTER_GPIO_IDX_SWDIO);
504 restore_gpio(ADAPTER_GPIO_IDX_SWCLK);
505 }
506
507 restore_gpio(ADAPTER_GPIO_IDX_SRST);
508 restore_gpio(ADAPTER_GPIO_IDX_LED);
509
510 /* Restore drive strength. MSB is password ("5A") */
511 pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] = 0x5A000000 | initial_drive_strength_etc;
512 bcm2835gpio_munmap();
513
514 return ERROR_OK;
515 }
516
517
518 static const char * const bcm2835_transports[] = { "jtag", "swd", NULL };
519
520 static struct jtag_interface bcm2835gpio_interface = {
521 .supported = DEBUG_CAP_TMS_SEQ,
522 .execute_queue = bitbang_execute_queue,
523 };
524 struct adapter_driver bcm2835gpio_adapter_driver = {
525 .name = "bcm2835gpio",
526 .transports = bcm2835_transports,
527 .commands = bcm2835gpio_command_handlers,
528
529 .init = bcm2835gpio_init,
530 .quit = bcm2835gpio_quit,
531 .reset = bcm2835gpio_reset,
532 .speed = bcm2835gpio_speed,
533 .khz = bcm2835gpio_khz,
534 .speed_div = bcm2835gpio_speed_div,
535
536 .jtag_ops = &bcm2835gpio_interface,
537 .swd_ops = &bitbang_swd,
538 };

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