1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include <jtag/interface.h>
37 static uint8_t output_value
= 0x0;
38 static int dev_mem_fd
;
39 static void *gpio_controller
;
40 static volatile uint8_t *gpio_data_register
;
41 static volatile uint8_t *gpio_data_direction_register
;
43 /* low level command set
45 static int ep93xx_read(void);
46 static void ep93xx_write(int tck
, int tms
, int tdi
);
47 static void ep93xx_reset(int trst
, int srst
);
49 static int ep93xx_speed(int speed
);
50 static int ep93xx_register_commands(struct command_context
*cmd_ctx
);
51 static int ep93xx_init(void);
52 static int ep93xx_quit(void);
54 struct timespec ep93xx_zzzz
;
56 struct jtag_interface ep93xx_interface
=
60 .execute_queue
= bitbang_execute_queue
,
62 .speed
= ep93xx_speed
,
63 .register_commands
= ep93xx_register_commands
,
68 static struct bitbang_interface ep93xx_bitbang
=
71 .write
= ep93xx_write
,
72 .reset
= ep93xx_reset
,
76 static int ep93xx_read(void)
78 return !!(*gpio_data_register
& TDO_BIT
);
81 static void ep93xx_write(int tck
, int tms
, int tdi
)
84 output_value
|= TCK_BIT
;
86 output_value
&= ~TCK_BIT
;
89 output_value
|= TMS_BIT
;
91 output_value
&= ~TMS_BIT
;
94 output_value
|= TDI_BIT
;
96 output_value
&= ~TDI_BIT
;
98 *gpio_data_register
= output_value
;
99 nanosleep(&ep93xx_zzzz
, NULL
);
102 /* (1) assert or (0) deassert reset lines */
103 static void ep93xx_reset(int trst
, int srst
)
106 output_value
|= TRST_BIT
;
108 output_value
&= ~TRST_BIT
;
111 output_value
|= SRST_BIT
;
113 output_value
&= ~SRST_BIT
;
115 *gpio_data_register
= output_value
;
116 nanosleep(&ep93xx_zzzz
, NULL
);
119 static int ep93xx_speed(int speed
)
125 static int ep93xx_register_commands(struct command_context
*cmd_ctx
)
131 static int set_gonk_mode(void)
136 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
137 MAP_SHARED
, dev_mem_fd
, 0x80930000);
138 if (syscon
== MAP_FAILED
) {
140 return ERROR_JTAG_INIT_FAILED
;
143 devicecfg
= *((volatile int *)(syscon
+ 0x80));
144 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
145 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
147 munmap(syscon
, 4096);
152 static int ep93xx_init(void)
156 bitbang_interface
= &ep93xx_bitbang
;
158 ep93xx_zzzz
.tv_sec
= 0;
159 ep93xx_zzzz
.tv_nsec
= 10000000;
161 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
162 if (dev_mem_fd
< 0) {
164 return ERROR_JTAG_INIT_FAILED
;
167 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
168 MAP_SHARED
, dev_mem_fd
, 0x80840000);
169 if (gpio_controller
== MAP_FAILED
) {
172 return ERROR_JTAG_INIT_FAILED
;
175 ret
= set_gonk_mode();
176 if (ret
!= ERROR_OK
) {
177 munmap(gpio_controller
, 4096);
183 /* Use GPIO port A. */
184 gpio_data_register
= gpio_controller
+ 0x00;
185 gpio_data_direction_register
= gpio_controller
+ 0x10;
188 /* Use GPIO port B. */
189 gpio_data_register
= gpio_controller
+ 0x04;
190 gpio_data_direction_register
= gpio_controller
+ 0x14;
192 /* Use GPIO port C. */
193 gpio_data_register
= gpio_controller
+ 0x08;
194 gpio_data_direction_register
= gpio_controller
+ 0x18;
196 /* Use GPIO port D. */
197 gpio_data_register
= gpio_controller
+ 0x0c;
198 gpio_data_direction_register
= gpio_controller
+ 0x1c;
201 /* Use GPIO port C. */
202 gpio_data_register
= gpio_controller
+ 0x08;
203 gpio_data_direction_register
= gpio_controller
+ 0x18;
205 LOG_INFO("gpio_data_register = %p\n", gpio_data_register
);
206 LOG_INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register
);
208 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
209 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
210 * TMS/TRST/SRST high.
212 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
213 *gpio_data_register
= output_value
;
214 nanosleep(&ep93xx_zzzz
, NULL
);
217 * Configure the direction register. 1 = output, 0 = input.
219 *gpio_data_direction_register
=
220 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
222 nanosleep(&ep93xx_zzzz
, NULL
);
226 static int ep93xx_quit(void)
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