src/rtos/rtos_riot_stackings.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2015 by Daniel Krebs                                    *
   5  *   Daniel Krebs - github@daniel-krebs.net                                *
   6  ***************************************************************************/
   7
   8 #ifdef HAVE_CONFIG_H
   9 #include "config.h"
  10 #endif
  11
  12 #include "rtos.h"
  13 #include "target/armv7m.h"
  14 #include "rtos_standard_stackings.h"
  15 #include "rtos_riot_stackings.h"
  16
  17 /* This works for the M0 and M34 stackings as xPSR is in a fixed
  18  * location
  19  */
  20 static target_addr_t rtos_riot_cortex_m_stack_align(struct target *target,
  21         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
  22         target_addr_t stack_ptr)
  23 {
  24         const int XPSR_OFFSET = 0x40;
  25         return rtos_cortex_m_stack_align(target, stack_data, stacking,
  26                 stack_ptr, XPSR_OFFSET);
  27 }
  28
  29 /* see thread_arch.c */
  30 static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
  31         { ARMV7M_R0,    0x24, 32 },             /* r0   */
  32         { ARMV7M_R1,    0x28, 32 },             /* r1   */
  33         { ARMV7M_R2,    0x2c, 32 },             /* r2   */
  34         { ARMV7M_R3,    0x30, 32 },             /* r3   */
  35         { ARMV7M_R4,    0x14, 32 },             /* r4   */
  36         { ARMV7M_R5,    0x18, 32 },             /* r5   */
  37         { ARMV7M_R6,    0x1c, 32 },             /* r6   */
  38         { ARMV7M_R7,    0x20, 32 },             /* r7   */
  39         { ARMV7M_R8,    0x04, 32 },             /* r8   */
  40         { ARMV7M_R9,    0x08, 32 },             /* r9   */
  41         { ARMV7M_R10,   0x0c, 32 },             /* r10  */
  42         { ARMV7M_R11,   0x10, 32 },             /* r11  */
  43         { ARMV7M_R12,   0x34, 32 },             /* r12  */
  44         { ARMV7M_R13,   -2,   32 },             /* sp   */
  45         { ARMV7M_R14,   0x38, 32 },             /* lr   */
  46         { ARMV7M_PC,    0x3c, 32 },             /* pc   */
  47         { ARMV7M_XPSR,  0x40, 32 },             /* xPSR */
  48 };
  49
  50 const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
  51         .stack_registers_size = 0x44,
  52         .stack_growth_direction = -1,
  53         .num_output_registers = ARMV7M_NUM_CORE_REGS,
  54         .calculate_process_stack = rtos_riot_cortex_m_stack_align,
  55         .register_offsets = rtos_riot_cortex_m0_stack_offsets
  56 };
  57
  58 /* see thread_arch.c */
  59 static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
  60         { ARMV7M_R0,    0x24, 32 },     /* r0   */
  61         { ARMV7M_R1,    0x28, 32 },     /* r1   */
  62         { ARMV7M_R2,    0x2c, 32 },     /* r2   */
  63         { ARMV7M_R3,    0x30, 32 },     /* r3   */
  64         { ARMV7M_R4,    0x04, 32 },     /* r4   */
  65         { ARMV7M_R5,    0x08, 32 },     /* r5   */
  66         { ARMV7M_R6,    0x0c, 32 },     /* r6   */
  67         { ARMV7M_R7,    0x10, 32 },     /* r7   */
  68         { ARMV7M_R8,    0x14, 32 },     /* r8   */
  69         { ARMV7M_R9,    0x18, 32 },     /* r9   */
  70         { ARMV7M_R10,   0x1c, 32 },     /* r10  */
  71         { ARMV7M_R11,   0x20, 32 },     /* r11  */
  72         { ARMV7M_R12,   0x34, 32 },     /* r12  */
  73         { ARMV7M_R13,   -2,   32 },     /* sp   */
  74         { ARMV7M_R14,   0x38, 32 },     /* lr   */
  75         { ARMV7M_PC,    0x3c, 32 },     /* pc   */
  76         { ARMV7M_XPSR,  0x40, 32 },     /* xPSR */
  77 };
  78
  79 const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
  80         .stack_registers_size = 0x44,
  81         .stack_growth_direction = -1,
  82         .num_output_registers = ARMV7M_NUM_CORE_REGS,
  83         .calculate_process_stack = rtos_riot_cortex_m_stack_align,
  84         .register_offsets = rtos_riot_cortex_m34_stack_offsets
  85 };