src/rtos/rtos_standard_stackings.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Broadcom Corporation                            *
   3  *   Evan Hunter - ehunter@broadcom.com                                    *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "rtos.h"
  26 #include "target/armv7m.h"
  27
  28 static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
  29         { 0x20, 32 },           /* r0   */
  30         { 0x24, 32 },           /* r1   */
  31         { 0x28, 32 },           /* r2   */
  32         { 0x2c, 32 },           /* r3   */
  33         { 0x00, 32 },           /* r4   */
  34         { 0x04, 32 },           /* r5   */
  35         { 0x08, 32 },           /* r6   */
  36         { 0x0c, 32 },           /* r7   */
  37         { 0x10, 32 },           /* r8   */
  38         { 0x14, 32 },           /* r9   */
  39         { 0x18, 32 },           /* r10  */
  40         { 0x1c, 32 },           /* r11  */
  41         { 0x30, 32 },           /* r12  */
  42         { -2,   32 },           /* sp   */
  43         { 0x34, 32 },           /* lr   */
  44         { 0x38, 32 },           /* pc   */
  45         { 0x3c, 32 },           /* xPSR */
  46 };
  47
  48 static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
  49         { 0x08, 32 },           /* r0  (a1)   */
  50         { 0x0c, 32 },           /* r1  (a2)  */
  51         { 0x10, 32 },           /* r2  (a3)  */
  52         { 0x14, 32 },           /* r3  (a4)  */
  53         { 0x18, 32 },           /* r4  (v1)  */
  54         { 0x1c, 32 },           /* r5  (v2)  */
  55         { 0x20, 32 },           /* r6  (v3)  */
  56         { 0x24, 32 },           /* r7  (v4)  */
  57         { 0x28, 32 },           /* r8  (a1)  */
  58         { 0x2c, 32 },           /* r9  (sb)  */
  59         { 0x30, 32 },           /* r10 (sl) */
  60         { 0x34, 32 },           /* r11 (fp) */
  61         { 0x38, 32 },           /* r12 (ip) */
  62         { -2,   32 },           /* sp   */
  63         { 0x3c, 32 },           /* lr   */
  64         { 0x40, 32 },           /* pc   */
  65         { -1,   96 },           /* FPA1 */
  66         { -1,   96 },           /* FPA2 */
  67         { -1,   96 },           /* FPA3 */
  68         { -1,   96 },           /* FPA4 */
  69         { -1,   96 },           /* FPA5 */
  70         { -1,   96 },           /* FPA6 */
  71         { -1,   96 },           /* FPA7 */
  72         { -1,   96 },           /* FPA8 */
  73         { -1,   32 },           /* FPS  */
  74         { 0x04, 32 },           /* CSPR */
  75 };
  76
  77 static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = {
  78         { 0x88, 32 },           /* R0  */
  79         { 0x8C, 32 },           /* R1 */
  80         { 0x14, 32 },           /* R2 */
  81         { 0x18, 32 },           /* R3 */
  82         { 0x1C, 32 },           /* R4 */
  83         { 0x20, 32 },           /* R5 */
  84         { 0x24, 32 },           /* R6 */
  85         { 0x28, 32 },           /* R7 */
  86         { 0x2C, 32 },           /* R8 */
  87         { 0x30, 32 },           /* R9 */
  88         { 0x34, 32 },           /* R10 */
  89         { 0x38, 32 },           /* R11 */
  90         { 0x3C, 32 },           /* R12 */
  91         { 0x40, 32 },           /* R13 */
  92         { 0x44, 32 },           /* R14 */
  93         { 0x48, 32 },           /* R15 */
  94         { 0x4C, 32 },           /* R16 */
  95         { 0x50, 32 },           /* R17 */
  96         { 0x54, 32 },           /* R18 */
  97         { 0x58, 32 },           /* R19 */
  98         { 0x5C, 32 },           /* R20 */
  99         { 0x60, 32 },           /* R21 */
 100         { 0x64, 32 },           /* R22 */
 101         { 0x68, 32 },           /* R23 */
 102         { 0x6C, 32 },           /* R24 */
 103         { 0x70, 32 },           /* R25 */
 104         { 0x74, 32 },           /* R26 */
 105         { 0x78, 32 },           /* R27 */
 106         { 0x7C, 32 },           /* R28 */
 107         { 0x80, 32 },           /* R29 */
 108         { 0x84, 32 },           /* R30 (LP) */
 109         { 0x00, 32 },           /* R31 (SP) */
 110         { 0x04, 32 },           /* PSW */
 111         { 0x08, 32 },           /* IPC */
 112         { 0x0C, 32 },           /* IPSW */
 113         { 0x10, 32 },           /* IFC_LP */
 114 };
 115
 116 static int64_t rtos_generic_stack_align(struct target *target,
 117         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 118         int64_t stack_ptr, int align)
 119 {
 120         int64_t new_stack_ptr;
 121         int64_t aligned_stack_ptr;
 122         new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
 123                 stacking->stack_registers_size;
 124         aligned_stack_ptr = new_stack_ptr & ~((int64_t)align - 1);
 125         if (aligned_stack_ptr != new_stack_ptr &&
 126                 stacking->stack_growth_direction == -1) {
 127                 /* If we have a downward growing stack, the simple alignment code
 128                  * above results in a wrong result (since it rounds down to nearest
 129                  * alignment).  We want to round up so add an extra align.
 130                  */
 131                 aligned_stack_ptr += (int64_t)align;
 132         }
 133         return aligned_stack_ptr;
 134 }
 135
 136 int64_t rtos_generic_stack_align8(struct target *target,
 137         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 138         int64_t stack_ptr)
 139 {
 140         return rtos_generic_stack_align(target, stack_data,
 141                         stacking, stack_ptr, 8);
 142 }
 143
 144 /* The Cortex M3 will indicate that an alignment adjustment
 145  * has been done on the stack by setting bit 9 of the stacked xPSR
 146  * register.  In this case, we can just add an extra 4 bytes to get
 147  * to the program stack.  Note that some places in the ARM documentation
 148  * make this a little unclear but the padding takes place before the
 149  * normal exception stacking - so xPSR is always available at a fixed
 150  * location.
 151  *
 152  * Relevant documentation:
 153  *    Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
 154  *        Cortex-M3 Devices Generic User Guide -> The Cortex-M3 Processor ->
 155  *        Exception Model -> Exception entry and return -> Exception entry
 156  *    Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
 157  *        Cortex-M3 Devices Generic User Guide -> Cortex-M3 Peripherals ->
 158  *        System control block -> Configuration and Control Register (STKALIGN)
 159  *
 160  * This is just a helper function for use in the calculate_process_stack
 161  * function for a given architecture/rtos.
 162  */
 163 int64_t rtos_Cortex_M_stack_align(struct target *target,
 164         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 165         int64_t stack_ptr, size_t xpsr_offset)
 166 {
 167         const uint32_t ALIGN_NEEDED = (1 << 9);
 168         uint32_t xpsr;
 169         int64_t new_stack_ptr;
 170
 171         new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
 172                 stacking->stack_registers_size;
 173         xpsr = (target->endianness == TARGET_LITTLE_ENDIAN) ?
 174                         le_to_h_u32(&stack_data[xpsr_offset]) :
 175                         be_to_h_u32(&stack_data[xpsr_offset]);
 176         if ((xpsr & ALIGN_NEEDED) != 0) {
 177                 LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n",
 178                         xpsr);
 179                 new_stack_ptr -= (stacking->stack_growth_direction * 4);
 180         }
 181         return new_stack_ptr;
 182 }
 183
 184 static int64_t rtos_standard_Cortex_M3_stack_align(struct target *target,
 185         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 186         int64_t stack_ptr)
 187 {
 188         const int XPSR_OFFSET = 0x3c;
 189         return rtos_Cortex_M_stack_align(target, stack_data, stacking,
 190                 stack_ptr, XPSR_OFFSET);
 191 }
 192
 193 const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
 194         0x40,                                   /* stack_registers_size */
 195         -1,                                             /* stack_growth_direction */
 196         ARMV7M_NUM_CORE_REGS,   /* num_output_registers */
 197         rtos_standard_Cortex_M3_stack_align,    /* stack_alignment */
 198         rtos_standard_Cortex_M3_stack_offsets   /* register_offsets */
 199 };
 200
 201 const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
 202         0x48,                           /* stack_registers_size */
 203         -1,                                     /* stack_growth_direction */
 204         26,                                     /* num_output_registers */
 205         rtos_generic_stack_align8,      /* stack_alignment */
 206         rtos_standard_Cortex_R4_stack_offsets   /* register_offsets */
 207 };
 208
 209 const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking = {
 210         0x90,                           /* stack_registers_size */
 211         -1,                                     /* stack_growth_direction */
 212         32,                                     /* num_output_registers */
 213         rtos_generic_stack_align8,      /* stack_alignment */
 214         rtos_standard_NDS32_N1068_stack_offsets /* register_offsets */
 215 };