1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
18 ***************************************************************************/
24 #include "breakpoints.h"
27 #include "target_request.h"
28 #include "target_type.h"
29 #include "armv8_opcodes.h"
30 #include "armv8_cache.h"
31 #include <helper/time_support.h>
33 static int aarch64_poll(struct target
*target
);
34 static int aarch64_debug_entry(struct target
*target
);
35 static int aarch64_restore_context(struct target
*target
, bool bpwp
);
36 static int aarch64_set_breakpoint(struct target
*target
,
37 struct breakpoint
*breakpoint
, uint8_t matchmode
);
38 static int aarch64_set_context_breakpoint(struct target
*target
,
39 struct breakpoint
*breakpoint
, uint8_t matchmode
);
40 static int aarch64_set_hybrid_breakpoint(struct target
*target
,
41 struct breakpoint
*breakpoint
);
42 static int aarch64_unset_breakpoint(struct target
*target
,
43 struct breakpoint
*breakpoint
);
44 static int aarch64_mmu(struct target
*target
, int *enabled
);
45 static int aarch64_virt2phys(struct target
*target
,
46 target_addr_t virt
, target_addr_t
*phys
);
47 static int aarch64_read_apb_ap_memory(struct target
*target
,
48 uint64_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
50 static int aarch64_restore_system_control_reg(struct target
*target
)
52 int retval
= ERROR_OK
;
54 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
55 struct armv8_common
*armv8
= target_to_armv8(target
);
57 if (aarch64
->system_control_reg
!= aarch64
->system_control_reg_curr
) {
58 aarch64
->system_control_reg_curr
= aarch64
->system_control_reg
;
59 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
61 switch (armv8
->arm
.core_mode
) {
65 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
68 aarch64
->system_control_reg
);
69 if (retval
!= ERROR_OK
)
74 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
77 aarch64
->system_control_reg
);
78 if (retval
!= ERROR_OK
)
83 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
86 aarch64
->system_control_reg
);
87 if (retval
!= ERROR_OK
)
91 retval
= armv8
->arm
.mcr(target
, 15, 0, 0, 1, 0, aarch64
->system_control_reg
);
92 if (retval
!= ERROR_OK
)
100 /* check address before aarch64_apb read write access with mmu on
101 * remove apb predictible data abort */
102 static int aarch64_check_address(struct target
*target
, uint32_t address
)
107 /* modify system_control_reg in order to enable or disable mmu for :
108 * - virt2phys address conversion
109 * - read or write memory in phys or virt address */
110 static int aarch64_mmu_modify(struct target
*target
, int enable
)
112 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
113 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
114 int retval
= ERROR_OK
;
117 /* if mmu enabled at target stop and mmu not enable */
118 if (!(aarch64
->system_control_reg
& 0x1U
)) {
119 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
122 if (!(aarch64
->system_control_reg_curr
& 0x1U
)) {
123 aarch64
->system_control_reg_curr
|= 0x1U
;
124 switch (armv8
->arm
.core_mode
) {
128 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
131 aarch64
->system_control_reg_curr
);
132 if (retval
!= ERROR_OK
)
137 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
140 aarch64
->system_control_reg_curr
);
141 if (retval
!= ERROR_OK
)
146 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
149 aarch64
->system_control_reg_curr
);
150 if (retval
!= ERROR_OK
)
154 LOG_DEBUG("unknow cpu state 0x%x" PRIx32
, armv8
->arm
.core_state
);
158 if (aarch64
->system_control_reg_curr
& 0x4U
) {
159 /* data cache is active */
160 aarch64
->system_control_reg_curr
&= ~0x4U
;
161 /* flush data cache armv7 function to be called */
162 if (armv8
->armv8_mmu
.armv8_cache
.flush_all_data_cache
)
163 armv8
->armv8_mmu
.armv8_cache
.flush_all_data_cache(target
);
165 if ((aarch64
->system_control_reg_curr
& 0x1U
)) {
166 aarch64
->system_control_reg_curr
&= ~0x1U
;
167 switch (armv8
->arm
.core_mode
) {
171 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
174 aarch64
->system_control_reg_curr
);
175 if (retval
!= ERROR_OK
)
180 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
183 aarch64
->system_control_reg_curr
);
184 if (retval
!= ERROR_OK
)
189 retval
= armv8
->arm
.msr(target
, 3, /*op 0*/
192 aarch64
->system_control_reg_curr
);
193 if (retval
!= ERROR_OK
)
197 LOG_DEBUG("unknow cpu state 0x%x" PRIx32
, armv8
->arm
.core_state
);
206 * Basic debug access, very low level assumes state is saved
208 static int aarch64_init_debug_access(struct target
*target
)
210 struct armv8_common
*armv8
= target_to_armv8(target
);
216 /* Clear Sticky Power Down status Bit in PRSR to enable access to
217 the registers in the Core Power Domain */
218 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
219 armv8
->debug_base
+ CPUV8_DBG_PRSR
, &dummy
);
220 if (retval
!= ERROR_OK
)
224 * Static CTI configuration:
225 * Channel 0 -> trigger outputs HALT request to PE
226 * Channel 1 -> trigger outputs Resume request to PE
227 * Gate all channel trigger events from entering the CTM
231 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
232 armv8
->cti_base
+ CTI_CTR
, 1);
233 /* By default, gate all channel triggers to and from the CTM */
234 if (retval
== ERROR_OK
)
235 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
236 armv8
->cti_base
+ CTI_GATE
, 0);
237 /* output halt requests to PE on channel 0 trigger */
238 if (retval
== ERROR_OK
)
239 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
240 armv8
->cti_base
+ CTI_OUTEN0
, CTI_CHNL(0));
241 /* output restart requests to PE on channel 1 trigger */
242 if (retval
== ERROR_OK
)
243 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
244 armv8
->cti_base
+ CTI_OUTEN1
, CTI_CHNL(1));
245 if (retval
!= ERROR_OK
)
248 /* Resync breakpoint registers */
250 /* Since this is likely called from init or reset, update target state information*/
251 return aarch64_poll(target
);
254 /* Write to memory mapped registers directly with no cache or mmu handling */
255 static int aarch64_dap_write_memap_register_u32(struct target
*target
,
260 struct armv8_common
*armv8
= target_to_armv8(target
);
262 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
, address
, value
);
267 static int aarch64_dpm_setup(struct aarch64_common
*a8
, uint64_t debug
)
269 struct arm_dpm
*dpm
= &a8
->armv8_common
.dpm
;
272 dpm
->arm
= &a8
->armv8_common
.arm
;
275 retval
= armv8_dpm_setup(dpm
);
276 if (retval
== ERROR_OK
)
277 retval
= armv8_dpm_initialize(dpm
);
282 static struct target
*get_aarch64(struct target
*target
, int32_t coreid
)
284 struct target_list
*head
;
288 while (head
!= (struct target_list
*)NULL
) {
290 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
296 static int aarch64_halt(struct target
*target
);
298 static int aarch64_halt_smp(struct target
*target
)
300 int retval
= ERROR_OK
;
301 struct target_list
*head
= target
->head
;
303 while (head
!= (struct target_list
*)NULL
) {
304 struct target
*curr
= head
->target
;
305 struct armv8_common
*armv8
= target_to_armv8(curr
);
307 /* open the gate for channel 0 to let HALT requests pass to the CTM */
309 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
310 armv8
->cti_base
+ CTI_GATE
, CTI_CHNL(0));
311 if (retval
!= ERROR_OK
)
317 /* halt the target PE */
318 if (retval
== ERROR_OK
)
319 retval
= aarch64_halt(target
);
324 static int update_halt_gdb(struct target
*target
)
327 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
328 target
->gdb_service
->target
= target
;
329 target
->gdb_service
->core
[0] = target
->coreid
;
330 retval
+= aarch64_halt_smp(target
);
336 * Cortex-A8 Run control
339 static int aarch64_poll(struct target
*target
)
341 int retval
= ERROR_OK
;
343 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
344 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
345 enum target_state prev_target_state
= target
->state
;
346 /* toggle to another core is done by gdb as follow */
347 /* maint packet J core_id */
349 /* the next polling trigger an halt event sent to gdb */
350 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
351 (target
->gdb_service
) &&
352 (target
->gdb_service
->target
== NULL
)) {
353 target
->gdb_service
->target
=
354 get_aarch64(target
, target
->gdb_service
->core
[1]);
355 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
358 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
359 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
360 if (retval
!= ERROR_OK
)
362 aarch64
->cpudbg_dscr
= dscr
;
364 if (DSCR_RUN_MODE(dscr
) == 0x3) {
365 if (prev_target_state
!= TARGET_HALTED
) {
366 /* We have a halting debug event */
367 LOG_DEBUG("Target halted");
368 target
->state
= TARGET_HALTED
;
369 if ((prev_target_state
== TARGET_RUNNING
)
370 || (prev_target_state
== TARGET_UNKNOWN
)
371 || (prev_target_state
== TARGET_RESET
)) {
372 retval
= aarch64_debug_entry(target
);
373 if (retval
!= ERROR_OK
)
376 retval
= update_halt_gdb(target
);
377 if (retval
!= ERROR_OK
)
380 target_call_event_callbacks(target
,
381 TARGET_EVENT_HALTED
);
383 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
386 retval
= aarch64_debug_entry(target
);
387 if (retval
!= ERROR_OK
)
390 retval
= update_halt_gdb(target
);
391 if (retval
!= ERROR_OK
)
395 target_call_event_callbacks(target
,
396 TARGET_EVENT_DEBUG_HALTED
);
400 target
->state
= TARGET_RUNNING
;
405 static int aarch64_halt(struct target
*target
)
407 int retval
= ERROR_OK
;
409 struct armv8_common
*armv8
= target_to_armv8(target
);
412 * add HDE in halting debug mode
414 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
415 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
416 if (retval
== ERROR_OK
)
417 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
418 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
| DSCR_HDE
);
419 if (retval
!= ERROR_OK
)
422 /* trigger an event on channel 0, this outputs a halt request to the PE */
423 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
424 armv8
->cti_base
+ CTI_APPPULSE
, CTI_CHNL(0));
425 if (retval
!= ERROR_OK
)
428 long long then
= timeval_ms();
430 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
431 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
432 if (retval
!= ERROR_OK
)
434 if ((dscr
& DSCRV8_HALT_MASK
) != 0)
436 if (timeval_ms() > then
+ 1000) {
437 LOG_ERROR("Timeout waiting for halt");
442 target
->debug_reason
= DBG_REASON_DBGRQ
;
447 static int aarch64_internal_restore(struct target
*target
, int current
,
448 uint64_t *address
, int handle_breakpoints
, int debug_execution
)
450 struct armv8_common
*armv8
= target_to_armv8(target
);
451 struct arm
*arm
= &armv8
->arm
;
455 if (!debug_execution
)
456 target_free_all_working_areas(target
);
458 /* current = 1: continue on current pc, otherwise continue at <address> */
459 resume_pc
= buf_get_u64(arm
->pc
->value
, 0, 64);
461 resume_pc
= *address
;
463 *address
= resume_pc
;
465 /* Make sure that the Armv7 gdb thumb fixups does not
466 * kill the return address
468 switch (arm
->core_state
) {
470 resume_pc
&= 0xFFFFFFFC;
472 case ARM_STATE_AARCH64
:
473 resume_pc
&= 0xFFFFFFFFFFFFFFFC;
475 case ARM_STATE_THUMB
:
476 case ARM_STATE_THUMB_EE
:
477 /* When the return address is loaded into PC
478 * bit 0 must be 1 to stay in Thumb state
482 case ARM_STATE_JAZELLE
:
483 LOG_ERROR("How do I resume into Jazelle state??");
486 LOG_DEBUG("resume pc = 0x%16" PRIx64
, resume_pc
);
487 buf_set_u64(arm
->pc
->value
, 0, 64, resume_pc
);
490 dpmv8_modeswitch(&armv8
->dpm
, ARM_MODE_ANY
);
492 /* called it now before restoring context because it uses cpu
493 * register r0 for restoring system control register */
494 retval
= aarch64_restore_system_control_reg(target
);
495 if (retval
!= ERROR_OK
)
497 retval
= aarch64_restore_context(target
, handle_breakpoints
);
498 if (retval
!= ERROR_OK
)
500 target
->debug_reason
= DBG_REASON_NOTHALTED
;
501 target
->state
= TARGET_RUNNING
;
503 /* registers are now invalid */
504 register_cache_invalidate(arm
->core_cache
);
509 static int aarch64_internal_restart(struct target
*target
, bool slave_pe
)
511 struct armv8_common
*armv8
= target_to_armv8(target
);
512 struct arm
*arm
= &armv8
->arm
;
516 * * Restart core and wait for it to be started. Clear ITRen and sticky
517 * * exception flags: see ARMv7 ARM, C5.9.
519 * REVISIT: for single stepping, we probably want to
520 * disable IRQs by default, with optional override...
523 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
524 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
525 if (retval
!= ERROR_OK
)
528 if ((dscr
& DSCR_ITE
) == 0)
529 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
531 /* make sure to acknowledge the halt event before resuming */
532 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
533 armv8
->cti_base
+ CTI_INACK
, CTI_TRIG(HALT
));
536 * open the CTI gate for channel 1 so that the restart events
537 * get passed along to all PEs
539 if (retval
== ERROR_OK
)
540 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
541 armv8
->cti_base
+ CTI_GATE
, CTI_CHNL(1));
542 if (retval
!= ERROR_OK
)
546 /* trigger an event on channel 1, generates a restart request to the PE */
547 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
548 armv8
->cti_base
+ CTI_APPPULSE
, CTI_CHNL(1));
549 if (retval
!= ERROR_OK
)
552 long long then
= timeval_ms();
554 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
555 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
556 if (retval
!= ERROR_OK
)
558 if ((dscr
& DSCR_HDE
) != 0)
560 if (timeval_ms() > then
+ 1000) {
561 LOG_ERROR("Timeout waiting for resume");
567 target
->debug_reason
= DBG_REASON_NOTHALTED
;
568 target
->state
= TARGET_RUNNING
;
570 /* registers are now invalid */
571 register_cache_invalidate(arm
->core_cache
);
576 static int aarch64_restore_smp(struct target
*target
, int handle_breakpoints
)
579 struct target_list
*head
;
583 while (head
!= (struct target_list
*)NULL
) {
585 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
586 /* resume current address , not in step mode */
587 retval
+= aarch64_internal_restore(curr
, 1, &address
,
588 handle_breakpoints
, 0);
589 retval
+= aarch64_internal_restart(curr
, true);
597 static int aarch64_resume(struct target
*target
, int current
,
598 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
601 uint64_t addr
= address
;
603 /* dummy resume for smp toggle in order to reduce gdb impact */
604 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
605 /* simulate a start and halt of target */
606 target
->gdb_service
->target
= NULL
;
607 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
608 /* fake resume at next poll we play the target core[1], see poll*/
609 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
612 aarch64_internal_restore(target
, current
, &addr
, handle_breakpoints
,
615 target
->gdb_service
->core
[0] = -1;
616 retval
= aarch64_restore_smp(target
, handle_breakpoints
);
617 if (retval
!= ERROR_OK
)
620 aarch64_internal_restart(target
, false);
622 if (!debug_execution
) {
623 target
->state
= TARGET_RUNNING
;
624 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
625 LOG_DEBUG("target resumed at 0x%" PRIx64
, addr
);
627 target
->state
= TARGET_DEBUG_RUNNING
;
628 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
629 LOG_DEBUG("target debug resumed at 0x%" PRIx64
, addr
);
635 static int aarch64_debug_entry(struct target
*target
)
637 int retval
= ERROR_OK
;
638 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
639 struct armv8_common
*armv8
= target_to_armv8(target
);
641 LOG_DEBUG("dscr = 0x%08" PRIx32
, aarch64
->cpudbg_dscr
);
643 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
644 * imprecise data aborts get discarded by issuing a Data
645 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
648 /* make sure to clear all sticky errors */
649 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
650 armv8
->debug_base
+ CPUV8_DBG_DRCR
, DRCR_CSE
);
651 if (retval
!= ERROR_OK
)
654 /* Examine debug reason */
655 armv8_dpm_report_dscr(&armv8
->dpm
, aarch64
->cpudbg_dscr
);
657 /* save address of instruction that triggered the watchpoint? */
658 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
662 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
663 armv8
->debug_base
+ CPUV8_DBG_WFAR1
,
665 if (retval
!= ERROR_OK
)
669 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
670 armv8
->debug_base
+ CPUV8_DBG_WFAR0
,
672 if (retval
!= ERROR_OK
)
675 armv8_dpm_report_wfar(&armv8
->dpm
, wfar
);
678 retval
= armv8_dpm_read_current_registers(&armv8
->dpm
);
680 if (armv8
->post_debug_entry
) {
681 retval
= armv8
->post_debug_entry(target
);
682 if (retval
!= ERROR_OK
)
689 static int aarch64_post_debug_entry(struct target
*target
)
691 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
692 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
695 /* clear sticky errors */
696 mem_ap_write_atomic_u32(armv8
->debug_ap
,
697 armv8
->debug_base
+ CPUV8_DBG_DRCR
, DRCR_CSE
);
699 switch (armv8
->arm
.core_mode
) {
703 retval
= armv8
->arm
.mrs(target
, 3, /*op 0*/
706 &aarch64
->system_control_reg
);
707 if (retval
!= ERROR_OK
)
712 retval
= armv8
->arm
.mrs(target
, 3, /*op 0*/
715 &aarch64
->system_control_reg
);
716 if (retval
!= ERROR_OK
)
721 retval
= armv8
->arm
.mrs(target
, 3, /*op 0*/
724 &aarch64
->system_control_reg
);
725 if (retval
!= ERROR_OK
)
729 retval
= armv8
->arm
.mrc(target
, 15, 0, 0, 1, 0, &aarch64
->system_control_reg
);
730 if (retval
!= ERROR_OK
)
735 LOG_DEBUG("System_register: %8.8" PRIx32
, aarch64
->system_control_reg
);
736 aarch64
->system_control_reg_curr
= aarch64
->system_control_reg
;
738 if (armv8
->armv8_mmu
.armv8_cache
.info
== -1) {
739 armv8_identify_cache(armv8
);
740 armv8_read_mpidr(armv8
);
743 armv8
->armv8_mmu
.mmu_enabled
=
744 (aarch64
->system_control_reg
& 0x1U
) ? 1 : 0;
745 armv8
->armv8_mmu
.armv8_cache
.d_u_cache_enabled
=
746 (aarch64
->system_control_reg
& 0x4U
) ? 1 : 0;
747 armv8
->armv8_mmu
.armv8_cache
.i_cache_enabled
=
748 (aarch64
->system_control_reg
& 0x1000U
) ? 1 : 0;
749 aarch64
->curr_mode
= armv8
->arm
.core_mode
;
753 static int aarch64_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
755 struct armv8_common
*armv8
= target_to_armv8(target
);
759 int retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
760 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
761 if (ERROR_OK
!= retval
)
767 dscr
|= value
& bit_mask
;
770 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
771 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
775 static int aarch64_step(struct target
*target
, int current
, target_addr_t address
,
776 int handle_breakpoints
)
778 struct armv8_common
*armv8
= target_to_armv8(target
);
782 if (target
->state
!= TARGET_HALTED
) {
783 LOG_WARNING("target not halted");
784 return ERROR_TARGET_NOT_HALTED
;
787 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
788 armv8
->debug_base
+ CPUV8_DBG_EDECR
, &edecr
);
789 if (retval
!= ERROR_OK
)
792 /* make sure EDECR.SS is not set when restoring the register */
795 /* set EDECR.SS to enter hardware step mode */
796 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
797 armv8
->debug_base
+ CPUV8_DBG_EDECR
, (edecr
|0x4));
798 if (retval
!= ERROR_OK
)
801 /* disable interrupts while stepping */
802 retval
= aarch64_set_dscr_bits(target
, 0x3 << 22, 0x3 << 22);
803 if (retval
!= ERROR_OK
)
806 /* resume the target */
807 retval
= aarch64_resume(target
, current
, address
, 0, 0);
808 if (retval
!= ERROR_OK
)
811 long long then
= timeval_ms();
812 while (target
->state
!= TARGET_HALTED
) {
813 retval
= aarch64_poll(target
);
814 if (retval
!= ERROR_OK
)
816 if (timeval_ms() > then
+ 1000) {
817 LOG_ERROR("timeout waiting for target halt");
823 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
824 armv8
->debug_base
+ CPUV8_DBG_EDECR
, edecr
);
825 if (retval
!= ERROR_OK
)
828 /* restore interrupts */
829 retval
= aarch64_set_dscr_bits(target
, 0x3 << 22, 0);
830 if (retval
!= ERROR_OK
)
836 static int aarch64_restore_context(struct target
*target
, bool bpwp
)
838 struct armv8_common
*armv8
= target_to_armv8(target
);
842 if (armv8
->pre_restore_context
)
843 armv8
->pre_restore_context(target
);
845 return armv8_dpm_write_dirty_registers(&armv8
->dpm
, bpwp
);
850 * Cortex-A8 Breakpoint and watchpoint functions
853 /* Setup hardware Breakpoint Register Pair */
854 static int aarch64_set_breakpoint(struct target
*target
,
855 struct breakpoint
*breakpoint
, uint8_t matchmode
)
860 uint8_t byte_addr_select
= 0x0F;
861 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
862 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
863 struct aarch64_brp
*brp_list
= aarch64
->brp_list
;
865 if (breakpoint
->set
) {
866 LOG_WARNING("breakpoint already set");
870 if (breakpoint
->type
== BKPT_HARD
) {
872 while (brp_list
[brp_i
].used
&& (brp_i
< aarch64
->brp_num
))
874 if (brp_i
>= aarch64
->brp_num
) {
875 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
876 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
878 breakpoint
->set
= brp_i
+ 1;
879 if (breakpoint
->length
== 2)
880 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
881 control
= ((matchmode
& 0x7) << 20)
883 | (byte_addr_select
<< 5)
885 brp_list
[brp_i
].used
= 1;
886 brp_list
[brp_i
].value
= breakpoint
->address
& 0xFFFFFFFFFFFFFFFC;
887 brp_list
[brp_i
].control
= control
;
888 bpt_value
= brp_list
[brp_i
].value
;
890 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
891 + CPUV8_DBG_BVR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
892 (uint32_t)(bpt_value
& 0xFFFFFFFF));
893 if (retval
!= ERROR_OK
)
895 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
896 + CPUV8_DBG_BVR_BASE
+ 4 + 16 * brp_list
[brp_i
].BRPn
,
897 (uint32_t)(bpt_value
>> 32));
898 if (retval
!= ERROR_OK
)
901 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
902 + CPUV8_DBG_BCR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
903 brp_list
[brp_i
].control
);
904 if (retval
!= ERROR_OK
)
906 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%" TARGET_PRIxADDR
, brp_i
,
907 brp_list
[brp_i
].control
,
908 brp_list
[brp_i
].value
);
910 } else if (breakpoint
->type
== BKPT_SOFT
) {
913 buf_set_u32(code
, 0, 32, ARMV8_HLT(0x11));
914 retval
= target_read_memory(target
,
915 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
916 breakpoint
->length
, 1,
917 breakpoint
->orig_instr
);
918 if (retval
!= ERROR_OK
)
921 armv8_cache_d_inner_flush_virt(armv8
,
922 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
925 retval
= target_write_memory(target
,
926 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
927 breakpoint
->length
, 1, code
);
928 if (retval
!= ERROR_OK
)
931 armv8_cache_d_inner_flush_virt(armv8
,
932 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
935 armv8_cache_i_inner_inval_virt(armv8
,
936 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
939 breakpoint
->set
= 0x11; /* Any nice value but 0 */
942 /* Ensure that halting debug mode is enable */
943 retval
= aarch64_set_dscr_bits(target
, DSCR_HDE
, DSCR_HDE
);
944 if (retval
!= ERROR_OK
) {
945 LOG_DEBUG("Failed to set DSCR.HDE");
952 static int aarch64_set_context_breakpoint(struct target
*target
,
953 struct breakpoint
*breakpoint
, uint8_t matchmode
)
955 int retval
= ERROR_FAIL
;
958 uint8_t byte_addr_select
= 0x0F;
959 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
960 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
961 struct aarch64_brp
*brp_list
= aarch64
->brp_list
;
963 if (breakpoint
->set
) {
964 LOG_WARNING("breakpoint already set");
967 /*check available context BRPs*/
968 while ((brp_list
[brp_i
].used
||
969 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< aarch64
->brp_num
))
972 if (brp_i
>= aarch64
->brp_num
) {
973 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
977 breakpoint
->set
= brp_i
+ 1;
978 control
= ((matchmode
& 0x7) << 20)
980 | (byte_addr_select
<< 5)
982 brp_list
[brp_i
].used
= 1;
983 brp_list
[brp_i
].value
= (breakpoint
->asid
);
984 brp_list
[brp_i
].control
= control
;
985 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
986 + CPUV8_DBG_BVR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
987 brp_list
[brp_i
].value
);
988 if (retval
!= ERROR_OK
)
990 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
991 + CPUV8_DBG_BCR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
992 brp_list
[brp_i
].control
);
993 if (retval
!= ERROR_OK
)
995 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%" TARGET_PRIxADDR
, brp_i
,
996 brp_list
[brp_i
].control
,
997 brp_list
[brp_i
].value
);
1002 static int aarch64_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1004 int retval
= ERROR_FAIL
;
1005 int brp_1
= 0; /* holds the contextID pair */
1006 int brp_2
= 0; /* holds the IVA pair */
1007 uint32_t control_CTX
, control_IVA
;
1008 uint8_t CTX_byte_addr_select
= 0x0F;
1009 uint8_t IVA_byte_addr_select
= 0x0F;
1010 uint8_t CTX_machmode
= 0x03;
1011 uint8_t IVA_machmode
= 0x01;
1012 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
1013 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
1014 struct aarch64_brp
*brp_list
= aarch64
->brp_list
;
1016 if (breakpoint
->set
) {
1017 LOG_WARNING("breakpoint already set");
1020 /*check available context BRPs*/
1021 while ((brp_list
[brp_1
].used
||
1022 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< aarch64
->brp_num
))
1025 printf("brp(CTX) found num: %d\n", brp_1
);
1026 if (brp_1
>= aarch64
->brp_num
) {
1027 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1031 while ((brp_list
[brp_2
].used
||
1032 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< aarch64
->brp_num
))
1035 printf("brp(IVA) found num: %d\n", brp_2
);
1036 if (brp_2
>= aarch64
->brp_num
) {
1037 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1041 breakpoint
->set
= brp_1
+ 1;
1042 breakpoint
->linked_BRP
= brp_2
;
1043 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1046 | (CTX_byte_addr_select
<< 5)
1048 brp_list
[brp_1
].used
= 1;
1049 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1050 brp_list
[brp_1
].control
= control_CTX
;
1051 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1052 + CPUV8_DBG_BVR_BASE
+ 16 * brp_list
[brp_1
].BRPn
,
1053 brp_list
[brp_1
].value
);
1054 if (retval
!= ERROR_OK
)
1056 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1057 + CPUV8_DBG_BCR_BASE
+ 16 * brp_list
[brp_1
].BRPn
,
1058 brp_list
[brp_1
].control
);
1059 if (retval
!= ERROR_OK
)
1062 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1065 | (IVA_byte_addr_select
<< 5)
1067 brp_list
[brp_2
].used
= 1;
1068 brp_list
[brp_2
].value
= breakpoint
->address
& 0xFFFFFFFFFFFFFFFC;
1069 brp_list
[brp_2
].control
= control_IVA
;
1070 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1071 + CPUV8_DBG_BVR_BASE
+ 16 * brp_list
[brp_2
].BRPn
,
1072 brp_list
[brp_2
].value
& 0xFFFFFFFF);
1073 if (retval
!= ERROR_OK
)
1075 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1076 + CPUV8_DBG_BVR_BASE
+ 4 + 16 * brp_list
[brp_2
].BRPn
,
1077 brp_list
[brp_2
].value
>> 32);
1078 if (retval
!= ERROR_OK
)
1080 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1081 + CPUV8_DBG_BCR_BASE
+ 16 * brp_list
[brp_2
].BRPn
,
1082 brp_list
[brp_2
].control
);
1083 if (retval
!= ERROR_OK
)
1089 static int aarch64_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1092 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
1093 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
1094 struct aarch64_brp
*brp_list
= aarch64
->brp_list
;
1096 if (!breakpoint
->set
) {
1097 LOG_WARNING("breakpoint not set");
1101 if (breakpoint
->type
== BKPT_HARD
) {
1102 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1103 int brp_i
= breakpoint
->set
- 1;
1104 int brp_j
= breakpoint
->linked_BRP
;
1105 if ((brp_i
< 0) || (brp_i
>= aarch64
->brp_num
)) {
1106 LOG_DEBUG("Invalid BRP number in breakpoint");
1109 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%" TARGET_PRIxADDR
, brp_i
,
1110 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1111 brp_list
[brp_i
].used
= 0;
1112 brp_list
[brp_i
].value
= 0;
1113 brp_list
[brp_i
].control
= 0;
1114 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1115 + CPUV8_DBG_BCR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
1116 brp_list
[brp_i
].control
);
1117 if (retval
!= ERROR_OK
)
1119 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1120 + CPUV8_DBG_BVR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
1121 (uint32_t)brp_list
[brp_i
].value
);
1122 if (retval
!= ERROR_OK
)
1124 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1125 + CPUV8_DBG_BVR_BASE
+ 4 + 16 * brp_list
[brp_i
].BRPn
,
1126 (uint32_t)brp_list
[brp_i
].value
);
1127 if (retval
!= ERROR_OK
)
1129 if ((brp_j
< 0) || (brp_j
>= aarch64
->brp_num
)) {
1130 LOG_DEBUG("Invalid BRP number in breakpoint");
1133 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx64
, brp_j
,
1134 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1135 brp_list
[brp_j
].used
= 0;
1136 brp_list
[brp_j
].value
= 0;
1137 brp_list
[brp_j
].control
= 0;
1138 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1139 + CPUV8_DBG_BCR_BASE
+ 16 * brp_list
[brp_j
].BRPn
,
1140 brp_list
[brp_j
].control
);
1141 if (retval
!= ERROR_OK
)
1143 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1144 + CPUV8_DBG_BVR_BASE
+ 16 * brp_list
[brp_j
].BRPn
,
1145 (uint32_t)brp_list
[brp_j
].value
);
1146 if (retval
!= ERROR_OK
)
1148 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1149 + CPUV8_DBG_BVR_BASE
+ 4 + 16 * brp_list
[brp_j
].BRPn
,
1150 (uint32_t)brp_list
[brp_j
].value
);
1151 if (retval
!= ERROR_OK
)
1154 breakpoint
->linked_BRP
= 0;
1155 breakpoint
->set
= 0;
1159 int brp_i
= breakpoint
->set
- 1;
1160 if ((brp_i
< 0) || (brp_i
>= aarch64
->brp_num
)) {
1161 LOG_DEBUG("Invalid BRP number in breakpoint");
1164 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx64
, brp_i
,
1165 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1166 brp_list
[brp_i
].used
= 0;
1167 brp_list
[brp_i
].value
= 0;
1168 brp_list
[brp_i
].control
= 0;
1169 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1170 + CPUV8_DBG_BCR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
1171 brp_list
[brp_i
].control
);
1172 if (retval
!= ERROR_OK
)
1174 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1175 + CPUV8_DBG_BVR_BASE
+ 16 * brp_list
[brp_i
].BRPn
,
1176 brp_list
[brp_i
].value
);
1177 if (retval
!= ERROR_OK
)
1180 retval
= aarch64_dap_write_memap_register_u32(target
, armv8
->debug_base
1181 + CPUV8_DBG_BVR_BASE
+ 4 + 16 * brp_list
[brp_i
].BRPn
,
1182 (uint32_t)brp_list
[brp_i
].value
);
1183 if (retval
!= ERROR_OK
)
1185 breakpoint
->set
= 0;
1189 /* restore original instruction (kept in target endianness) */
1191 armv8_cache_d_inner_flush_virt(armv8
,
1192 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
1193 breakpoint
->length
);
1195 if (breakpoint
->length
== 4) {
1196 retval
= target_write_memory(target
,
1197 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
1198 4, 1, breakpoint
->orig_instr
);
1199 if (retval
!= ERROR_OK
)
1202 retval
= target_write_memory(target
,
1203 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
1204 2, 1, breakpoint
->orig_instr
);
1205 if (retval
!= ERROR_OK
)
1209 armv8_cache_d_inner_flush_virt(armv8
,
1210 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
1211 breakpoint
->length
);
1213 armv8_cache_i_inner_inval_virt(armv8
,
1214 breakpoint
->address
& 0xFFFFFFFFFFFFFFFE,
1215 breakpoint
->length
);
1217 breakpoint
->set
= 0;
1222 static int aarch64_add_breakpoint(struct target
*target
,
1223 struct breakpoint
*breakpoint
)
1225 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
1227 if ((breakpoint
->type
== BKPT_HARD
) && (aarch64
->brp_num_available
< 1)) {
1228 LOG_INFO("no hardware breakpoint available");
1229 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1232 if (breakpoint
->type
== BKPT_HARD
)
1233 aarch64
->brp_num_available
--;
1235 return aarch64_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1238 static int aarch64_add_context_breakpoint(struct target
*target
,
1239 struct breakpoint
*breakpoint
)
1241 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
1243 if ((breakpoint
->type
== BKPT_HARD
) && (aarch64
->brp_num_available
< 1)) {
1244 LOG_INFO("no hardware breakpoint available");
1245 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1248 if (breakpoint
->type
== BKPT_HARD
)
1249 aarch64
->brp_num_available
--;
1251 return aarch64_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1254 static int aarch64_add_hybrid_breakpoint(struct target
*target
,
1255 struct breakpoint
*breakpoint
)
1257 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
1259 if ((breakpoint
->type
== BKPT_HARD
) && (aarch64
->brp_num_available
< 1)) {
1260 LOG_INFO("no hardware breakpoint available");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1264 if (breakpoint
->type
== BKPT_HARD
)
1265 aarch64
->brp_num_available
--;
1267 return aarch64_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1271 static int aarch64_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1273 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
1276 /* It is perfectly possible to remove breakpoints while the target is running */
1277 if (target
->state
!= TARGET_HALTED
) {
1278 LOG_WARNING("target not halted");
1279 return ERROR_TARGET_NOT_HALTED
;
1283 if (breakpoint
->set
) {
1284 aarch64_unset_breakpoint(target
, breakpoint
);
1285 if (breakpoint
->type
== BKPT_HARD
)
1286 aarch64
->brp_num_available
++;
1293 * Cortex-A8 Reset functions
1296 static int aarch64_assert_reset(struct target
*target
)
1298 struct armv8_common
*armv8
= target_to_armv8(target
);
1302 /* FIXME when halt is requested, make it work somehow... */
1304 /* Issue some kind of warm reset. */
1305 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1306 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1307 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1308 /* REVISIT handle "pulls" cases, if there's
1309 * hardware that needs them to work.
1311 jtag_add_reset(0, 1);
1313 LOG_ERROR("%s: how to reset?", target_name(target
));
1317 /* registers are now invalid */
1318 register_cache_invalidate(armv8
->arm
.core_cache
);
1320 target
->state
= TARGET_RESET
;
1325 static int aarch64_deassert_reset(struct target
*target
)
1331 /* be certain SRST is off */
1332 jtag_add_reset(0, 0);
1334 retval
= aarch64_poll(target
);
1335 if (retval
!= ERROR_OK
)
1338 if (target
->reset_halt
) {
1339 if (target
->state
!= TARGET_HALTED
) {
1340 LOG_WARNING("%s: ran after reset and before halt ...",
1341 target_name(target
));
1342 retval
= target_halt(target
);
1343 if (retval
!= ERROR_OK
)
1351 static int aarch64_write_apb_ap_memory(struct target
*target
,
1352 uint64_t address
, uint32_t size
,
1353 uint32_t count
, const uint8_t *buffer
)
1355 /* write memory through APB-AP */
1356 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1357 struct armv8_common
*armv8
= target_to_armv8(target
);
1358 struct arm_dpm
*dpm
= &armv8
->dpm
;
1359 struct arm
*arm
= &armv8
->arm
;
1360 int total_bytes
= count
* size
;
1362 int start_byte
= address
& 0x3;
1363 int end_byte
= (address
+ total_bytes
) & 0x3;
1366 uint8_t *tmp_buff
= NULL
;
1368 LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx64
" size %" PRIu32
" count%" PRIu32
,
1369 address
, size
, count
);
1370 if (target
->state
!= TARGET_HALTED
) {
1371 LOG_WARNING("target not halted");
1372 return ERROR_TARGET_NOT_HALTED
;
1375 total_u32
= DIV_ROUND_UP((address
& 3) + total_bytes
, 4);
1377 /* Mark register R0 as dirty, as it will be used
1378 * for transferring the data.
1379 * It will be restored automatically when exiting
1382 reg
= armv8_reg_current(arm
, 1);
1385 reg
= armv8_reg_current(arm
, 0);
1388 /* clear any abort */
1389 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1390 armv8
->debug_base
+ CPUV8_DBG_DRCR
, DRCR_CSE
);
1391 if (retval
!= ERROR_OK
)
1395 /* This algorithm comes from DDI0487A.g, chapter J9.1 */
1397 /* The algorithm only copies 32 bit words, so the buffer
1398 * should be expanded to include the words at either end.
1399 * The first and last words will be read first to avoid
1400 * corruption if needed.
1402 tmp_buff
= malloc(total_u32
* 4);
1404 if ((start_byte
!= 0) && (total_u32
> 1)) {
1405 /* First bytes not aligned - read the 32 bit word to avoid corrupting
1406 * the other bytes in the word.
1408 retval
= aarch64_read_apb_ap_memory(target
, (address
& ~0x3), 4, 1, tmp_buff
);
1409 if (retval
!= ERROR_OK
)
1410 goto error_free_buff_w
;
1413 /* If end of write is not aligned, or the write is less than 4 bytes */
1414 if ((end_byte
!= 0) ||
1415 ((total_u32
== 1) && (total_bytes
!= 4))) {
1417 /* Read the last word to avoid corruption during 32 bit write */
1418 int mem_offset
= (total_u32
-1) * 4;
1419 retval
= aarch64_read_apb_ap_memory(target
, (address
& ~0x3) + mem_offset
, 4, 1, &tmp_buff
[mem_offset
]);
1420 if (retval
!= ERROR_OK
)
1421 goto error_free_buff_w
;
1424 /* Copy the write buffer over the top of the temporary buffer */
1425 memcpy(&tmp_buff
[start_byte
], buffer
, total_bytes
);
1427 /* We now have a 32 bit aligned buffer that can be written */
1430 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1431 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1432 if (retval
!= ERROR_OK
)
1433 goto error_free_buff_w
;
1435 /* Set Normal access mode */
1436 dscr
= (dscr
& ~DSCR_MA
);
1437 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1438 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1440 if (arm
->core_state
== ARM_STATE_AARCH64
) {
1441 /* Write X0 with value 'address' using write procedure */
1442 /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
1443 /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
1444 retval
= dpm
->instr_write_data_dcc_64(dpm
,
1445 ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0
, 0), address
& ~0x3ULL
);
1447 /* Write R0 with value 'address' using write procedure */
1448 /* Step 1.a+b - Write the address for read access into DBGDTRRX */
1449 /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
1450 dpm
->instr_write_data_dcc(dpm
,
1451 T32_FMTITR(ARMV4_5_MRC(14, 0, 0, 0, 5, 0)), address
& ~0x3ULL
);
1454 /* Step 1.d - Change DCC to memory mode */
1455 dscr
= dscr
| DSCR_MA
;
1456 retval
+= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1457 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1458 if (retval
!= ERROR_OK
)
1459 goto error_unset_dtr_w
;
1462 /* Step 2.a - Do the write */
1463 retval
= mem_ap_write_buf_noincr(armv8
->debug_ap
,
1464 tmp_buff
, 4, total_u32
, armv8
->debug_base
+ CPUV8_DBG_DTRRX
);
1465 if (retval
!= ERROR_OK
)
1466 goto error_unset_dtr_w
;
1468 /* Step 3.a - Switch DTR mode back to Normal mode */
1469 dscr
= (dscr
& ~DSCR_MA
);
1470 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1471 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1472 if (retval
!= ERROR_OK
)
1473 goto error_unset_dtr_w
;
1475 /* Check for sticky abort flags in the DSCR */
1476 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1477 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1478 if (retval
!= ERROR_OK
)
1479 goto error_free_buff_w
;
1480 if (dscr
& (DSCR_ERR
| DSCR_SYS_ERROR_PEND
)) {
1481 /* Abort occurred - clear it and exit */
1482 LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32
, dscr
);
1483 mem_ap_write_atomic_u32(armv8
->debug_ap
,
1484 armv8
->debug_base
+ CPUV8_DBG_DRCR
, 1<<2);
1485 goto error_free_buff_w
;
1493 /* Unset DTR mode */
1494 mem_ap_read_atomic_u32(armv8
->debug_ap
,
1495 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1496 dscr
= (dscr
& ~DSCR_MA
);
1497 mem_ap_write_atomic_u32(armv8
->debug_ap
,
1498 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1505 static int aarch64_read_apb_ap_memory(struct target
*target
,
1506 target_addr_t address
, uint32_t size
,
1507 uint32_t count
, uint8_t *buffer
)
1509 /* read memory through APB-AP */
1510 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1511 struct armv8_common
*armv8
= target_to_armv8(target
);
1512 struct arm_dpm
*dpm
= &armv8
->dpm
;
1513 struct arm
*arm
= &armv8
->arm
;
1514 int total_bytes
= count
* size
;
1516 int start_byte
= address
& 0x3;
1517 int end_byte
= (address
+ total_bytes
) & 0x3;
1520 uint8_t *tmp_buff
= NULL
;
1524 LOG_DEBUG("Reading APB-AP memory address 0x%" TARGET_PRIxADDR
" size %" PRIu32
" count%" PRIu32
,
1525 address
, size
, count
);
1526 if (target
->state
!= TARGET_HALTED
) {
1527 LOG_WARNING("target not halted");
1528 return ERROR_TARGET_NOT_HALTED
;
1531 total_u32
= DIV_ROUND_UP((address
& 3) + total_bytes
, 4);
1532 /* Mark register X0, X1 as dirty, as it will be used
1533 * for transferring the data.
1534 * It will be restored automatically when exiting
1537 reg
= armv8_reg_current(arm
, 1);
1540 reg
= armv8_reg_current(arm
, 0);
1543 /* clear any abort */
1544 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1545 armv8
->debug_base
+ CPUV8_DBG_DRCR
, DRCR_CSE
);
1546 if (retval
!= ERROR_OK
)
1547 goto error_free_buff_r
;
1550 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1551 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1553 /* This algorithm comes from DDI0487A.g, chapter J9.1 */
1555 /* Set Normal access mode */
1556 dscr
= (dscr
& ~DSCR_MA
);
1557 retval
+= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1558 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1560 if (arm
->core_state
== ARM_STATE_AARCH64
) {
1561 /* Write X0 with value 'address' using write procedure */
1562 /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
1563 /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
1564 retval
+= dpm
->instr_write_data_dcc_64(dpm
,
1565 ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0
, 0), address
& ~0x3ULL
);
1566 /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
1567 retval
+= dpm
->instr_execute(dpm
, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0
, 0));
1568 /* Step 1.e - Change DCC to memory mode */
1569 dscr
= dscr
| DSCR_MA
;
1570 retval
+= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1571 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1572 /* Step 1.f - read DBGDTRTX and discard the value */
1573 retval
+= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1574 armv8
->debug_base
+ CPUV8_DBG_DTRTX
, &value
);
1576 /* Write R0 with value 'address' using write procedure */
1577 /* Step 1.a+b - Write the address for read access into DBGDTRRXint */
1578 /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
1579 retval
+= dpm
->instr_write_data_dcc(dpm
,
1580 T32_FMTITR(ARMV4_5_MRC(14, 0, 0, 0, 5, 0)), address
& ~0x3ULL
);
1581 /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
1582 retval
+= dpm
->instr_execute(dpm
, T32_FMTITR(ARMV4_5_MCR(14, 0, 0, 0, 5, 0)));
1583 /* Step 1.e - Change DCC to memory mode */
1584 dscr
= dscr
| DSCR_MA
;
1585 retval
+= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1586 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1587 /* Step 1.f - read DBGDTRTX and discard the value */
1588 retval
+= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1589 armv8
->debug_base
+ CPUV8_DBG_DTRTX
, &value
);
1592 if (retval
!= ERROR_OK
)
1593 goto error_unset_dtr_r
;
1595 /* Optimize the read as much as we can, either way we read in a single pass */
1596 if ((start_byte
) || (end_byte
)) {
1597 /* The algorithm only copies 32 bit words, so the buffer
1598 * should be expanded to include the words at either end.
1599 * The first and last words will be read into a temp buffer
1600 * to avoid corruption
1602 tmp_buff
= malloc(total_u32
* 4);
1604 goto error_unset_dtr_r
;
1606 /* use the tmp buffer to read the entire data */
1607 u8buf_ptr
= tmp_buff
;
1609 /* address and read length are aligned so read directly into the passed buffer */
1612 /* Read the data - Each read of the DTRTX register causes the instruction to be reissued
1613 * Abort flags are sticky, so can be read at end of transactions
1615 * This data is read in aligned to 32 bit boundary.
1618 /* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
1619 * increments X0 by 4. */
1620 retval
= mem_ap_read_buf_noincr(armv8
->debug_ap
, u8buf_ptr
, 4, total_u32
-1,
1621 armv8
->debug_base
+ CPUV8_DBG_DTRTX
);
1622 if (retval
!= ERROR_OK
)
1623 goto error_unset_dtr_r
;
1625 /* Step 3.a - set DTR access mode back to Normal mode */
1626 dscr
= (dscr
& ~DSCR_MA
);
1627 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1628 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1629 if (retval
!= ERROR_OK
)
1630 goto error_free_buff_r
;
1632 /* Step 3.b - read DBGDTRTX for the final value */
1633 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1634 armv8
->debug_base
+ CPUV8_DBG_DTRTX
, &value
);
1635 memcpy(u8buf_ptr
+ (total_u32
-1) * 4, &value
, 4);
1637 /* Check for sticky abort flags in the DSCR */
1638 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1639 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1640 if (retval
!= ERROR_OK
)
1641 goto error_free_buff_r
;
1642 if (dscr
& (DSCR_ERR
| DSCR_SYS_ERROR_PEND
)) {
1643 /* Abort occurred - clear it and exit */
1644 LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32
, dscr
);
1645 mem_ap_write_atomic_u32(armv8
->debug_ap
,
1646 armv8
->debug_base
+ CPUV8_DBG_DRCR
, DRCR_CSE
);
1647 goto error_free_buff_r
;
1650 /* check if we need to copy aligned data by applying any shift necessary */
1652 memcpy(buffer
, tmp_buff
+ start_byte
, total_bytes
);
1660 /* Unset DTR mode */
1661 mem_ap_read_atomic_u32(armv8
->debug_ap
,
1662 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1663 dscr
= (dscr
& ~DSCR_MA
);
1664 mem_ap_write_atomic_u32(armv8
->debug_ap
,
1665 armv8
->debug_base
+ CPUV8_DBG_DSCR
, dscr
);
1672 static int aarch64_read_phys_memory(struct target
*target
,
1673 target_addr_t address
, uint32_t size
,
1674 uint32_t count
, uint8_t *buffer
)
1676 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1677 LOG_DEBUG("Reading memory at real address 0x%" TARGET_PRIxADDR
"; size %" PRId32
"; count %" PRId32
,
1678 address
, size
, count
);
1680 if (count
&& buffer
) {
1681 /* read memory through APB-AP */
1682 retval
= aarch64_mmu_modify(target
, 0);
1683 if (retval
!= ERROR_OK
)
1685 retval
= aarch64_read_apb_ap_memory(target
, address
, size
, count
, buffer
);
1690 static int aarch64_read_memory(struct target
*target
, target_addr_t address
,
1691 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1693 int mmu_enabled
= 0;
1696 /* aarch64 handles unaligned memory access */
1697 LOG_DEBUG("Reading memory at address 0x%" TARGET_PRIxADDR
"; size %" PRId32
"; count %" PRId32
, address
,
1700 /* determine if MMU was enabled on target stop */
1701 retval
= aarch64_mmu(target
, &mmu_enabled
);
1702 if (retval
!= ERROR_OK
)
1706 retval
= aarch64_check_address(target
, address
);
1707 if (retval
!= ERROR_OK
)
1709 /* enable MMU as we could have disabled it for phys access */
1710 retval
= aarch64_mmu_modify(target
, 1);
1711 if (retval
!= ERROR_OK
)
1714 return aarch64_read_apb_ap_memory(target
, address
, size
, count
, buffer
);
1717 static int aarch64_write_phys_memory(struct target
*target
,
1718 target_addr_t address
, uint32_t size
,
1719 uint32_t count
, const uint8_t *buffer
)
1721 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1723 LOG_DEBUG("Writing memory to real address 0x%" TARGET_PRIxADDR
"; size %" PRId32
"; count %" PRId32
, address
,
1726 if (count
&& buffer
) {
1727 /* write memory through APB-AP */
1728 retval
= aarch64_mmu_modify(target
, 0);
1729 if (retval
!= ERROR_OK
)
1731 return aarch64_write_apb_ap_memory(target
, address
, size
, count
, buffer
);
1737 static int aarch64_write_memory(struct target
*target
, target_addr_t address
,
1738 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1740 int mmu_enabled
= 0;
1743 /* aarch64 handles unaligned memory access */
1744 LOG_DEBUG("Writing memory at address 0x%" TARGET_PRIxADDR
"; size %" PRId32
1745 "; count %" PRId32
, address
, size
, count
);
1747 /* determine if MMU was enabled on target stop */
1748 retval
= aarch64_mmu(target
, &mmu_enabled
);
1749 if (retval
!= ERROR_OK
)
1753 retval
= aarch64_check_address(target
, address
);
1754 if (retval
!= ERROR_OK
)
1756 /* enable MMU as we could have disabled it for phys access */
1757 retval
= aarch64_mmu_modify(target
, 1);
1758 if (retval
!= ERROR_OK
)
1761 return aarch64_write_apb_ap_memory(target
, address
, size
, count
, buffer
);
1764 static int aarch64_handle_target_request(void *priv
)
1766 struct target
*target
= priv
;
1767 struct armv8_common
*armv8
= target_to_armv8(target
);
1770 if (!target_was_examined(target
))
1772 if (!target
->dbg_msg_enabled
)
1775 if (target
->state
== TARGET_RUNNING
) {
1778 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1779 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1781 /* check if we have data */
1782 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
1783 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1784 armv8
->debug_base
+ CPUV8_DBG_DTRTX
, &request
);
1785 if (retval
== ERROR_OK
) {
1786 target_request(target
, request
);
1787 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1788 armv8
->debug_base
+ CPUV8_DBG_DSCR
, &dscr
);
1796 static int aarch64_examine_first(struct target
*target
)
1798 struct aarch64_common
*aarch64
= target_to_aarch64(target
);
1799 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
1800 struct adiv5_dap
*swjdp
= armv8
->arm
.dap
;
1802 int retval
= ERROR_OK
;
1803 uint64_t debug
, ttypr
;
1805 uint32_t tmp0
, tmp1
;
1806 debug
= ttypr
= cpuid
= 0;
1808 /* We do one extra read to ensure DAP is configured,
1809 * we call ahbap_debugport_init(swjdp) instead
1811 retval
= dap_dp_init(swjdp
);
1812 if (retval
!= ERROR_OK
)
1815 /* Search for the APB-AB - it is needed for access to debug registers */
1816 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv8
->debug_ap
);
1817 if (retval
!= ERROR_OK
) {
1818 LOG_ERROR("Could not find APB-AP for debug access");
1822 retval
= mem_ap_init(armv8
->debug_ap
);
1823 if (retval
!= ERROR_OK
) {
1824 LOG_ERROR("Could not initialize the APB-AP");
1828 armv8
->debug_ap
->memaccess_tck
= 80;
1830 if (!target
->dbgbase_set
) {
1832 /* Get ROM Table base */
1834 int32_t coreidx
= target
->coreid
;
1835 retval
= dap_get_debugbase(armv8
->debug_ap
, &dbgbase
, &apid
);
1836 if (retval
!= ERROR_OK
)
1838 /* Lookup 0x15 -- Processor DAP */
1839 retval
= dap_lookup_cs_component(armv8
->debug_ap
, dbgbase
, 0x15,
1840 &armv8
->debug_base
, &coreidx
);
1841 if (retval
!= ERROR_OK
)
1843 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
1844 " apid: %08" PRIx32
, coreidx
, armv8
->debug_base
, apid
);
1846 armv8
->debug_base
= target
->dbgbase
;
1848 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1849 armv8
->debug_base
+ CPUV8_DBG_LOCKACCESS
, 0xC5ACCE55);
1850 if (retval
!= ERROR_OK
) {
1851 LOG_DEBUG("LOCK debug access fail");
1855 retval
= mem_ap_write_atomic_u32(armv8
->debug_ap
,
1856 armv8
->debug_base
+ CPUV8_DBG_OSLAR
, 0);
1857 if (retval
!= ERROR_OK
) {
1858 LOG_DEBUG("Examine %s failed", "oslock");
1862 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1863 armv8
->debug_base
+ CPUV8_DBG_MAINID0
, &cpuid
);
1864 if (retval
!= ERROR_OK
) {
1865 LOG_DEBUG("Examine %s failed", "CPUID");
1869 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1870 armv8
->debug_base
+ CPUV8_DBG_MEMFEATURE0
, &tmp0
);
1871 retval
+= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1872 armv8
->debug_base
+ CPUV8_DBG_MEMFEATURE0
+ 4, &tmp1
);
1873 if (retval
!= ERROR_OK
) {
1874 LOG_DEBUG("Examine %s failed", "Memory Model Type");
1878 ttypr
= (ttypr
<< 32) | tmp0
;
1880 retval
= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1881 armv8
->debug_base
+ CPUV8_DBG_DBGFEATURE0
, &tmp0
);
1882 retval
+= mem_ap_read_atomic_u32(armv8
->debug_ap
,
1883 armv8
->debug_base
+ CPUV8_DBG_DBGFEATURE0
+ 4, &tmp1
);
1884 if (retval
!= ERROR_OK
) {
1885 LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
1889 debug
= (debug
<< 32) | tmp0
;
1891 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
1892 LOG_DEBUG("ttypr = 0x%08" PRIx64
, ttypr
);
1893 LOG_DEBUG("debug = 0x%08" PRIx64
, debug
);
1895 if (target
->ctibase
== 0) {
1896 /* assume a v8 rom table layout */
1897 armv8
->cti_base
= target
->ctibase
= armv8
->debug_base
+ 0x10000;
1898 LOG_INFO("Target ctibase is not set, assuming 0x%0" PRIx32
, target
->ctibase
);
1900 armv8
->cti_base
= target
->ctibase
;
1902 armv8
->arm
.core_type
= ARM_MODE_MON
;
1903 retval
= aarch64_dpm_setup(aarch64
, debug
);
1904 if (retval
!= ERROR_OK
)
1907 /* Setup Breakpoint Register Pairs */
1908 aarch64
->brp_num
= (uint32_t)((debug
>> 12) & 0x0F) + 1;
1909 aarch64
->brp_num_context
= (uint32_t)((debug
>> 28) & 0x0F) + 1;
1910 aarch64
->brp_num_available
= aarch64
->brp_num
;
1911 aarch64
->brp_list
= calloc(aarch64
->brp_num
, sizeof(struct aarch64_brp
));
1912 for (i
= 0; i
< aarch64
->brp_num
; i
++) {
1913 aarch64
->brp_list
[i
].used
= 0;
1914 if (i
< (aarch64
->brp_num
-aarch64
->brp_num_context
))
1915 aarch64
->brp_list
[i
].type
= BRP_NORMAL
;
1917 aarch64
->brp_list
[i
].type
= BRP_CONTEXT
;
1918 aarch64
->brp_list
[i
].value
= 0;
1919 aarch64
->brp_list
[i
].control
= 0;
1920 aarch64
->brp_list
[i
].BRPn
= i
;
1923 LOG_DEBUG("Configured %i hw breakpoints", aarch64
->brp_num
);
1925 target_set_examined(target
);
1929 static int aarch64_examine(struct target
*target
)
1931 int retval
= ERROR_OK
;
1933 /* don't re-probe hardware after each reset */
1934 if (!target_was_examined(target
))
1935 retval
= aarch64_examine_first(target
);
1937 /* Configure core debug access */
1938 if (retval
== ERROR_OK
)
1939 retval
= aarch64_init_debug_access(target
);
1945 * Cortex-A8 target creation and initialization
1948 static int aarch64_init_target(struct command_context
*cmd_ctx
,
1949 struct target
*target
)
1951 /* examine_first() does a bunch of this */
1955 static int aarch64_init_arch_info(struct target
*target
,
1956 struct aarch64_common
*aarch64
, struct jtag_tap
*tap
)
1958 struct armv8_common
*armv8
= &aarch64
->armv8_common
;
1959 struct adiv5_dap
*dap
= armv8
->arm
.dap
;
1961 armv8
->arm
.dap
= dap
;
1963 /* Setup struct aarch64_common */
1964 aarch64
->common_magic
= AARCH64_COMMON_MAGIC
;
1965 /* tap has no dap initialized */
1967 tap
->dap
= dap_init();
1969 /* Leave (only) generic DAP stuff for debugport_init() */
1970 tap
->dap
->tap
= tap
;
1973 armv8
->arm
.dap
= tap
->dap
;
1975 aarch64
->fast_reg_read
= 0;
1977 /* register arch-specific functions */
1978 armv8
->examine_debug_reason
= NULL
;
1980 armv8
->post_debug_entry
= aarch64_post_debug_entry
;
1982 armv8
->pre_restore_context
= NULL
;
1984 armv8
->armv8_mmu
.read_physical_memory
= aarch64_read_phys_memory
;
1986 /* REVISIT v7a setup should be in a v7a-specific routine */
1987 armv8_init_arch_info(target
, armv8
);
1988 target_register_timer_callback(aarch64_handle_target_request
, 1, 1, target
);
1993 static int aarch64_target_create(struct target
*target
, Jim_Interp
*interp
)
1995 struct aarch64_common
*aarch64
= calloc(1, sizeof(struct aarch64_common
));
1997 return aarch64_init_arch_info(target
, aarch64
, target
->tap
);
2000 static int aarch64_mmu(struct target
*target
, int *enabled
)
2002 if (target
->state
!= TARGET_HALTED
) {
2003 LOG_ERROR("%s: target not halted", __func__
);
2004 return ERROR_TARGET_INVALID
;
2007 *enabled
= target_to_aarch64(target
)->armv8_common
.armv8_mmu
.mmu_enabled
;
2011 static int aarch64_virt2phys(struct target
*target
, target_addr_t virt
,
2012 target_addr_t
*phys
)
2014 return armv8_mmu_translate_va(target
, virt
, phys
);
2017 COMMAND_HANDLER(aarch64_handle_cache_info_command
)
2019 struct target
*target
= get_current_target(CMD_CTX
);
2020 struct armv8_common
*armv8
= target_to_armv8(target
);
2022 return armv8_handle_cache_info_command(CMD_CTX
,
2023 &armv8
->armv8_mmu
.armv8_cache
);
2027 COMMAND_HANDLER(aarch64_handle_dbginit_command
)
2029 struct target
*target
= get_current_target(CMD_CTX
);
2030 if (!target_was_examined(target
)) {
2031 LOG_ERROR("target not examined yet");
2035 return aarch64_init_debug_access(target
);
2037 COMMAND_HANDLER(aarch64_handle_smp_off_command
)
2039 struct target
*target
= get_current_target(CMD_CTX
);
2040 /* check target is an smp target */
2041 struct target_list
*head
;
2042 struct target
*curr
;
2043 head
= target
->head
;
2045 if (head
!= (struct target_list
*)NULL
) {
2046 while (head
!= (struct target_list
*)NULL
) {
2047 curr
= head
->target
;
2051 /* fixes the target display to the debugger */
2052 target
->gdb_service
->target
= target
;
2057 COMMAND_HANDLER(aarch64_handle_smp_on_command
)
2059 struct target
*target
= get_current_target(CMD_CTX
);
2060 struct target_list
*head
;
2061 struct target
*curr
;
2062 head
= target
->head
;
2063 if (head
!= (struct target_list
*)NULL
) {
2065 while (head
!= (struct target_list
*)NULL
) {
2066 curr
= head
->target
;
2074 COMMAND_HANDLER(aarch64_handle_smp_gdb_command
)
2076 struct target
*target
= get_current_target(CMD_CTX
);
2077 int retval
= ERROR_OK
;
2078 struct target_list
*head
;
2079 head
= target
->head
;
2080 if (head
!= (struct target_list
*)NULL
) {
2081 if (CMD_ARGC
== 1) {
2083 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
2084 if (ERROR_OK
!= retval
)
2086 target
->gdb_service
->core
[1] = coreid
;
2089 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
2090 , target
->gdb_service
->core
[1]);
2095 static const struct command_registration aarch64_exec_command_handlers
[] = {
2097 .name
= "cache_info",
2098 .handler
= aarch64_handle_cache_info_command
,
2099 .mode
= COMMAND_EXEC
,
2100 .help
= "display information about target caches",
2105 .handler
= aarch64_handle_dbginit_command
,
2106 .mode
= COMMAND_EXEC
,
2107 .help
= "Initialize core debug",
2110 { .name
= "smp_off",
2111 .handler
= aarch64_handle_smp_off_command
,
2112 .mode
= COMMAND_EXEC
,
2113 .help
= "Stop smp handling",
2118 .handler
= aarch64_handle_smp_on_command
,
2119 .mode
= COMMAND_EXEC
,
2120 .help
= "Restart smp handling",
2125 .handler
= aarch64_handle_smp_gdb_command
,
2126 .mode
= COMMAND_EXEC
,
2127 .help
= "display/fix current core played to gdb",
2132 COMMAND_REGISTRATION_DONE
2134 static const struct command_registration aarch64_command_handlers
[] = {
2136 .chain
= arm_command_handlers
,
2139 .chain
= armv8_command_handlers
,
2143 .mode
= COMMAND_ANY
,
2144 .help
= "Cortex-A command group",
2146 .chain
= aarch64_exec_command_handlers
,
2148 COMMAND_REGISTRATION_DONE
2151 struct target_type aarch64_target
= {
2154 .poll
= aarch64_poll
,
2155 .arch_state
= armv8_arch_state
,
2157 .halt
= aarch64_halt
,
2158 .resume
= aarch64_resume
,
2159 .step
= aarch64_step
,
2161 .assert_reset
= aarch64_assert_reset
,
2162 .deassert_reset
= aarch64_deassert_reset
,
2164 /* REVISIT allow exporting VFP3 registers ... */
2165 .get_gdb_reg_list
= armv8_get_gdb_reg_list
,
2167 .read_memory
= aarch64_read_memory
,
2168 .write_memory
= aarch64_write_memory
,
2170 .checksum_memory
= arm_checksum_memory
,
2171 .blank_check_memory
= arm_blank_check_memory
,
2173 .run_algorithm
= armv4_5_run_algorithm
,
2175 .add_breakpoint
= aarch64_add_breakpoint
,
2176 .add_context_breakpoint
= aarch64_add_context_breakpoint
,
2177 .add_hybrid_breakpoint
= aarch64_add_hybrid_breakpoint
,
2178 .remove_breakpoint
= aarch64_remove_breakpoint
,
2179 .add_watchpoint
= NULL
,
2180 .remove_watchpoint
= NULL
,
2182 .commands
= aarch64_command_handlers
,
2183 .target_create
= aarch64_target_create
,
2184 .init_target
= aarch64_init_target
,
2185 .examine
= aarch64_examine
,
2187 .read_phys_memory
= aarch64_read_phys_memory
,
2188 .write_phys_memory
= aarch64_write_phys_memory
,
2190 .virt2phys
= aarch64_virt2phys
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)