1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
27 * Single-DAP support only.
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
56 /* for debug, set do_sync to true to force synchronous transfers */
59 static struct adiv5_dap
*swd_multidrop_selected_dap
;
62 static int swd_queue_dp_write_inner(struct adiv5_dap
*dap
, unsigned int reg
,
66 static int swd_send_sequence(struct adiv5_dap
*dap
, enum swd_special_seq seq
)
68 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
71 return swd
->switch_seq(seq
);
74 static void swd_finish_read(struct adiv5_dap
*dap
)
76 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
78 swd
->read_reg(swd_cmd(true, false, DP_RDBUFF
), dap
->last_read
, 0);
79 dap
->last_read
= NULL
;
83 static void swd_clear_sticky_errors(struct adiv5_dap
*dap
)
85 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
88 swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
89 STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
92 static int swd_run_inner(struct adiv5_dap
*dap
)
94 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
99 if (retval
!= ERROR_OK
) {
101 dap
->do_reconnect
= true;
107 static inline int check_sync(struct adiv5_dap
*dap
)
109 return do_sync
? swd_run_inner(dap
) : ERROR_OK
;
112 /** Select the DP register bank matching bits 7:4 of reg. */
113 static int swd_queue_dp_bankselect(struct adiv5_dap
*dap
, unsigned int reg
)
115 /* Only register address 4 is banked. */
116 if ((reg
& 0xf) != 4)
119 uint32_t select_dp_bank
= (reg
& 0x000000F0) >> 4;
120 uint32_t sel
= select_dp_bank
121 | (dap
->select
& (DP_SELECT_APSEL
| DP_SELECT_APBANK
));
123 if (sel
== dap
->select
)
128 int retval
= swd_queue_dp_write_inner(dap
, DP_SELECT
, sel
);
129 if (retval
!= ERROR_OK
)
130 dap
->select
= DP_SELECT_INVALID
;
135 static int swd_queue_dp_read_inner(struct adiv5_dap
*dap
, unsigned int reg
,
138 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
141 int retval
= swd_queue_dp_bankselect(dap
, reg
);
142 if (retval
!= ERROR_OK
)
145 swd
->read_reg(swd_cmd(true, false, reg
), data
, 0);
147 return check_sync(dap
);
150 static int swd_queue_dp_write_inner(struct adiv5_dap
*dap
, unsigned int reg
,
154 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
157 swd_finish_read(dap
);
159 if (reg
== DP_SELECT
) {
160 dap
->select
= data
& (DP_SELECT_APSEL
| DP_SELECT_APBANK
| DP_SELECT_DPBANK
);
162 swd
->write_reg(swd_cmd(false, false, reg
), data
, 0);
164 retval
= check_sync(dap
);
165 if (retval
!= ERROR_OK
)
166 dap
->select
= DP_SELECT_INVALID
;
171 retval
= swd_queue_dp_bankselect(dap
, reg
);
172 if (retval
!= ERROR_OK
)
175 swd
->write_reg(swd_cmd(false, false, reg
), data
, 0);
177 return check_sync(dap
);
181 static int swd_multidrop_select_inner(struct adiv5_dap
*dap
, uint32_t *dpidr_ptr
,
182 uint32_t *dlpidr_ptr
, bool clear_sticky
)
185 uint32_t dpidr
, dlpidr
;
187 assert(dap_is_multidrop(dap
));
189 swd_send_sequence(dap
, LINE_RESET
);
191 retval
= swd_queue_dp_write_inner(dap
, DP_TARGETSEL
, dap
->multidrop_targetsel
);
192 if (retval
!= ERROR_OK
)
195 retval
= swd_queue_dp_read_inner(dap
, DP_DPIDR
, &dpidr
);
196 if (retval
!= ERROR_OK
)
200 /* Clear all sticky errors (including ORUN) */
201 swd_clear_sticky_errors(dap
);
203 /* Ideally just clear ORUN flag which is set by reset */
204 retval
= swd_queue_dp_write_inner(dap
, DP_ABORT
, ORUNERRCLR
);
205 if (retval
!= ERROR_OK
)
209 retval
= swd_queue_dp_read_inner(dap
, DP_DLPIDR
, &dlpidr
);
210 if (retval
!= ERROR_OK
)
213 retval
= swd_run_inner(dap
);
214 if (retval
!= ERROR_OK
)
217 if ((dpidr
& DP_DPIDR_VERSION_MASK
) < (2UL << DP_DPIDR_VERSION_SHIFT
)) {
218 LOG_INFO("Read DPIDR 0x%08" PRIx32
219 " has version < 2. A non multidrop capable device connected?",
224 /* TODO: check TARGETID if DLIPDR is same for more than one DP */
225 uint32_t expected_dlpidr
= DP_DLPIDR_PROTVSN
|
226 (dap
->multidrop_targetsel
& DP_TARGETSEL_INSTANCEID_MASK
);
227 if (dlpidr
!= expected_dlpidr
) {
228 LOG_INFO("Read incorrect DLPIDR 0x%08" PRIx32
229 " (possibly CTRL/STAT value)",
234 LOG_DEBUG_IO("Selected DP_TARGETSEL 0x%08" PRIx32
, dap
->multidrop_targetsel
);
235 swd_multidrop_selected_dap
= dap
;
241 *dlpidr_ptr
= dlpidr
;
246 static int swd_multidrop_select(struct adiv5_dap
*dap
)
248 if (!dap_is_multidrop(dap
))
251 if (swd_multidrop_selected_dap
== dap
)
254 int retval
= ERROR_OK
;
255 for (unsigned int retry
= 0; ; retry
++) {
256 bool clear_sticky
= retry
> 0;
258 retval
= swd_multidrop_select_inner(dap
, NULL
, NULL
, clear_sticky
);
259 if (retval
== ERROR_OK
)
262 swd_multidrop_selected_dap
= NULL
;
264 LOG_ERROR("Failed to select multidrop %s", adiv5_dap_name(dap
));
268 LOG_DEBUG("Failed to select multidrop %s, retrying...",
269 adiv5_dap_name(dap
));
275 static int swd_connect_multidrop(struct adiv5_dap
*dap
)
278 uint32_t dpidr
= 0xdeadbeef;
279 uint32_t dlpidr
= 0xdeadbeef;
280 int64_t timeout
= timeval_ms() + 500;
283 swd_send_sequence(dap
, JTAG_TO_DORMANT
);
284 swd_send_sequence(dap
, DORMANT_TO_SWD
);
286 /* Clear link state, including the SELECT cache. */
287 dap
->do_reconnect
= false;
288 dap_invalidate_cache(dap
);
289 swd_multidrop_selected_dap
= NULL
;
291 retval
= swd_multidrop_select_inner(dap
, &dpidr
, &dlpidr
, true);
292 if (retval
== ERROR_OK
)
297 } while (timeval_ms() < timeout
);
299 if (retval
!= ERROR_OK
) {
300 swd_multidrop_selected_dap
= NULL
;
301 LOG_ERROR("Failed to connect multidrop %s", adiv5_dap_name(dap
));
305 LOG_INFO("SWD DPIDR 0x%08" PRIx32
", DLPIDR 0x%08" PRIx32
,
311 static int swd_connect_single(struct adiv5_dap
*dap
)
314 uint32_t dpidr
= 0xdeadbeef;
315 int64_t timeout
= timeval_ms() + 500;
318 if (dap
->switch_through_dormant
) {
319 swd_send_sequence(dap
, JTAG_TO_DORMANT
);
320 swd_send_sequence(dap
, DORMANT_TO_SWD
);
322 swd_send_sequence(dap
, JTAG_TO_SWD
);
325 /* Clear link state, including the SELECT cache. */
326 dap
->do_reconnect
= false;
327 dap_invalidate_cache(dap
);
329 retval
= swd_queue_dp_read_inner(dap
, DP_DPIDR
, &dpidr
);
330 if (retval
== ERROR_OK
) {
331 retval
= swd_run_inner(dap
);
332 if (retval
== ERROR_OK
)
338 dap
->switch_through_dormant
= !dap
->switch_through_dormant
;
339 } while (timeval_ms() < timeout
);
341 if (retval
!= ERROR_OK
) {
342 LOG_ERROR("Error connecting DP: cannot read IDR");
346 LOG_INFO("SWD DPIDR 0x%08" PRIx32
, dpidr
);
349 dap
->do_reconnect
= false;
351 /* force clear all sticky faults */
352 swd_clear_sticky_errors(dap
);
354 retval
= swd_run_inner(dap
);
355 if (retval
!= ERROR_WAIT
)
360 } while (timeval_ms() < timeout
);
365 static int swd_connect(struct adiv5_dap
*dap
)
369 /* FIXME validate transport config ... is the
370 * configured DAP present (check IDCODE)?
373 /* Check if we should reset srst already when connecting, but not if reconnecting. */
374 if (!dap
->do_reconnect
) {
375 enum reset_types jtag_reset_config
= jtag_get_reset_config();
377 if (jtag_reset_config
& RESET_CNCT_UNDER_SRST
) {
378 if (jtag_reset_config
& RESET_SRST_NO_GATING
)
379 adapter_assert_reset();
381 LOG_WARNING("\'srst_nogate\' reset_config option is required");
385 if (dap_is_multidrop(dap
))
386 status
= swd_connect_multidrop(dap
);
388 status
= swd_connect_single(dap
);
391 * "A WAIT response must not be issued to the ...
392 * ... writes to the ABORT register"
393 * swd_clear_sticky_errors() writes to the ABORT register only.
395 * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
396 * in a corner case. Just try if ABORT resolves the problem.
398 if (status
== ERROR_WAIT
) {
399 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
401 dap
->do_reconnect
= false;
403 status
= swd_queue_dp_write_inner(dap
, DP_ABORT
,
404 DAPABORT
| STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
);
406 if (status
== ERROR_OK
)
407 status
= swd_run_inner(dap
);
410 if (status
== ERROR_OK
)
411 status
= dap_dp_init(dap
);
416 static int swd_check_reconnect(struct adiv5_dap
*dap
)
418 if (dap
->do_reconnect
)
419 return swd_connect(dap
);
424 static int swd_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
426 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
429 /* TODO: Send DAPABORT in swd_multidrop_select_inner()
430 * in the case the multidrop dap is not selected?
431 * swd_queue_ap_abort() is not currently used anyway...
433 int retval
= swd_multidrop_select(dap
);
434 if (retval
!= ERROR_OK
)
437 swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
438 DAPABORT
| STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
439 return check_sync(dap
);
442 static int swd_queue_dp_read(struct adiv5_dap
*dap
, unsigned reg
,
445 int retval
= swd_check_reconnect(dap
);
446 if (retval
!= ERROR_OK
)
449 retval
= swd_multidrop_select(dap
);
450 if (retval
!= ERROR_OK
)
453 return swd_queue_dp_read_inner(dap
, reg
, data
);
456 static int swd_queue_dp_write(struct adiv5_dap
*dap
, unsigned reg
,
459 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
462 int retval
= swd_check_reconnect(dap
);
463 if (retval
!= ERROR_OK
)
466 retval
= swd_multidrop_select(dap
);
467 if (retval
!= ERROR_OK
)
470 return swd_queue_dp_write_inner(dap
, reg
, data
);
473 /** Select the AP register bank matching bits 7:4 of reg. */
474 static int swd_queue_ap_bankselect(struct adiv5_ap
*ap
, unsigned reg
)
476 struct adiv5_dap
*dap
= ap
->dap
;
477 uint32_t sel
= ((uint32_t)ap
->ap_num
<< 24)
479 | (dap
->select
& DP_SELECT_DPBANK
);
481 if (sel
== dap
->select
)
486 int retval
= swd_queue_dp_write_inner(dap
, DP_SELECT
, sel
);
487 if (retval
!= ERROR_OK
)
488 dap
->select
= DP_SELECT_INVALID
;
493 static int swd_queue_ap_read(struct adiv5_ap
*ap
, unsigned reg
,
496 struct adiv5_dap
*dap
= ap
->dap
;
497 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
500 int retval
= swd_check_reconnect(dap
);
501 if (retval
!= ERROR_OK
)
504 retval
= swd_multidrop_select(dap
);
505 if (retval
!= ERROR_OK
)
508 retval
= swd_queue_ap_bankselect(ap
, reg
);
509 if (retval
!= ERROR_OK
)
512 swd
->read_reg(swd_cmd(true, true, reg
), dap
->last_read
, ap
->memaccess_tck
);
513 dap
->last_read
= data
;
515 return check_sync(dap
);
518 static int swd_queue_ap_write(struct adiv5_ap
*ap
, unsigned reg
,
521 struct adiv5_dap
*dap
= ap
->dap
;
522 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
525 int retval
= swd_check_reconnect(dap
);
526 if (retval
!= ERROR_OK
)
529 retval
= swd_multidrop_select(dap
);
530 if (retval
!= ERROR_OK
)
533 swd_finish_read(dap
);
535 retval
= swd_queue_ap_bankselect(ap
, reg
);
536 if (retval
!= ERROR_OK
)
539 swd
->write_reg(swd_cmd(false, true, reg
), data
, ap
->memaccess_tck
);
541 return check_sync(dap
);
544 /** Executes all queued DAP operations. */
545 static int swd_run(struct adiv5_dap
*dap
)
547 int retval
= swd_multidrop_select(dap
);
548 if (retval
!= ERROR_OK
)
551 swd_finish_read(dap
);
553 return swd_run_inner(dap
);
556 /** Put the SWJ-DP back to JTAG mode */
557 static void swd_quit(struct adiv5_dap
*dap
)
559 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
562 /* There is no difference if the sequence is sent at the last
563 * or the first swd_quit() call, send it just once */
568 if (dap_is_multidrop(dap
)) {
569 swd
->switch_seq(SWD_TO_DORMANT
);
571 * Leaving DPs in dormant state was tested and offers some safety
572 * against DPs mismatch in case of unintentional use of non-multidrop SWD.
573 * To put SWJ-DPs to power-on state issue
574 * swd->switch_seq(DORMANT_TO_JTAG);
577 if (dap
->switch_through_dormant
) {
578 swd
->switch_seq(SWD_TO_DORMANT
);
579 swd
->switch_seq(DORMANT_TO_JTAG
);
581 swd
->switch_seq(SWD_TO_JTAG
);
585 /* flush the queue to shift out the sequence before exit */
589 const struct dap_ops swd_dap_ops
= {
590 .connect
= swd_connect
,
591 .send_sequence
= swd_send_sequence
,
592 .queue_dp_read
= swd_queue_dp_read
,
593 .queue_dp_write
= swd_queue_dp_write
,
594 .queue_ap_read
= swd_queue_ap_read
,
595 .queue_ap_write
= swd_queue_ap_write
,
596 .queue_ap_abort
= swd_queue_ap_abort
,
601 static const struct command_registration swd_commands
[] = {
604 * Set up SWD and JTAG targets identically, unless/until
605 * infrastructure improves ... meanwhile, ignore all
606 * JTAG-specific stuff like IR length for SWD.
608 * REVISIT can we verify "just one SWD DAP" here/early?
611 .jim_handler
= jim_jtag_newtap
,
612 .mode
= COMMAND_CONFIG
,
613 .help
= "declare a new SWD DAP"
615 COMMAND_REGISTRATION_DONE
618 static const struct command_registration swd_handlers
[] = {
622 .help
= "SWD command group",
623 .chain
= swd_commands
,
626 COMMAND_REGISTRATION_DONE
629 static int swd_select(struct command_context
*ctx
)
631 /* FIXME: only place where global 'adapter_driver' is still needed */
632 extern struct adapter_driver
*adapter_driver
;
633 const struct swd_driver
*swd
= adapter_driver
->swd_ops
;
636 retval
= register_commands(ctx
, NULL
, swd_handlers
);
637 if (retval
!= ERROR_OK
)
640 /* be sure driver is in SWD mode; start
641 * with hardware default TRN (1), it can be changed later
643 if (!swd
|| !swd
->read_reg
|| !swd
->write_reg
|| !swd
->init
) {
644 LOG_DEBUG("no SWD driver?");
648 retval
= swd
->init();
649 if (retval
!= ERROR_OK
) {
650 LOG_DEBUG("can't init SWD driver");
657 static int swd_init(struct command_context
*ctx
)
659 /* nothing done here, SWD is initialized
660 * together with the DAP */
664 static struct transport swd_transport
= {
666 .select
= swd_select
,
670 static void swd_constructor(void) __attribute__((constructor
));
671 static void swd_constructor(void)
673 transport_register(&swd_transport
);
676 /** Returns true if the current debug session
677 * is using SWD as its transport.
679 bool transport_is_swd(void)
681 return get_current_transport() == &swd_transport
;
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)