1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
5 * Frank Dols <frank.dols@synopsys.com> *
6 * Mischa Jonker <mischa.jonker@synopsys.com> *
7 * Anton Kolesov <anton.kolesov@synopsys.com> *
8 * Evgeniy Didin <didin@synopsys.com> *
9 ***************************************************************************/
21 * ARC architecture specific details.
23 * ARC has two types of registers:
24 * 1) core registers(e.g. r0,r1..) [is_core = true]
25 * 2) Auxiliary registers [is_core = false]..
27 * Auxiliary registers at the same time can be divided into
28 * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
29 * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
31 * The way of accessing to Core and AUX registers differs on Jtag level.
32 * BCR/non-BCR describes if the register is immutable and that reading
33 * unexisting register is safe RAZ, rather then an error.
34 * Note, core registers cannot be BCR.
36 * In arc/cpu/ tcl files all registers are defined as core, non-BCR aux
37 * and BCR aux, in "add-reg" command they are passed to three lists
38 * respectively: core_reg_descriptions, aux_reg_descriptions,
39 * bcr_reg_descriptions.
41 * Due to the specifics of accessing to BCR/non-BCR registers there are two
43 * 1) core_and_aux_cache - includes registers described in
44 * core_reg_descriptions and aux_reg_descriptions lists.
45 * Used during save/restore context step.
46 * 2) bcr_cache - includes registers described bcr_reg_descriptions.
47 * Currently used internally during configure step.
51 static int arc_remove_watchpoint(struct target
*target
,
52 struct watchpoint
*watchpoint
);
54 void arc_reg_data_type_add(struct target
*target
,
55 struct arc_reg_data_type
*data_type
)
57 LOG_DEBUG("Adding %s reg_data_type", data_type
->data_type
.id
);
58 struct arc_common
*arc
= target_to_arc(target
);
61 list_add_tail(&data_type
->list
, &arc
->reg_data_types
);
65 * Private implementation of register_get_by_name() for ARC that
66 * doesn't skip not [yet] existing registers. Used in many places
67 * for iteration through registers and even for marking required registers as
70 struct reg
*arc_reg_get_by_name(struct reg_cache
*first
,
71 const char *name
, bool search_all
)
74 struct reg_cache
*cache
= first
;
77 for (i
= 0; i
< cache
->num_regs
; i
++) {
78 if (!strcmp(cache
->reg_list
[i
].name
, name
))
79 return &(cache
->reg_list
[i
]);
92 * Reset internal states of caches. Must be called when entering debugging.
94 * @param target Target for which to reset caches states.
96 static int arc_reset_caches_states(struct target
*target
)
98 struct arc_common
*arc
= target_to_arc(target
);
100 LOG_DEBUG("Resetting internal variables of caches states");
102 /* Reset caches states. */
103 arc
->dcache_flushed
= false;
104 arc
->l2cache_flushed
= false;
105 arc
->icache_invalidated
= false;
106 arc
->dcache_invalidated
= false;
107 arc
->l2cache_invalidated
= false;
112 /* Initialize arc_common structure, which passes to openocd target instance */
113 static int arc_init_arch_info(struct target
*target
, struct arc_common
*arc
,
114 struct jtag_tap
*tap
)
116 arc
->common_magic
= ARC_COMMON_MAGIC
;
117 target
->arch_info
= arc
;
119 arc
->jtag_info
.tap
= tap
;
121 /* The only allowed ir_length is 4 for ARC jtag. */
122 if (tap
->ir_length
!= 4) {
123 LOG_ERROR("ARC jtag instruction length should be equal to 4");
127 /* On most ARC targets there is a dcache, so we enable its flushing
128 * by default. If there no dcache, there will be no error, just a slight
129 * performance penalty from unnecessary JTAG operations. */
130 arc
->has_dcache
= true;
131 arc
->has_icache
= true;
132 /* L2$ is not available in a target by default. */
133 arc
->has_l2cache
= false;
134 arc_reset_caches_states(target
);
136 /* Add standard GDB data types */
137 INIT_LIST_HEAD(&arc
->reg_data_types
);
138 struct arc_reg_data_type
*std_types
= calloc(ARRAY_SIZE(standard_gdb_types
),
142 LOG_ERROR("Unable to allocate memory");
146 for (unsigned int i
= 0; i
< ARRAY_SIZE(standard_gdb_types
); i
++) {
147 std_types
[i
].data_type
.type
= standard_gdb_types
[i
].type
;
148 std_types
[i
].data_type
.id
= standard_gdb_types
[i
].id
;
149 arc_reg_data_type_add(target
, &(std_types
[i
]));
152 /* Fields related to target descriptions */
153 INIT_LIST_HEAD(&arc
->core_reg_descriptions
);
154 INIT_LIST_HEAD(&arc
->aux_reg_descriptions
);
155 INIT_LIST_HEAD(&arc
->bcr_reg_descriptions
);
157 arc
->num_core_regs
= 0;
158 arc
->num_aux_regs
= 0;
159 arc
->num_bcr_regs
= 0;
160 arc
->last_general_reg
= ULONG_MAX
;
161 arc
->pc_index_in_cache
= ULONG_MAX
;
162 arc
->debug_index_in_cache
= ULONG_MAX
;
167 int arc_reg_add(struct target
*target
, struct arc_reg_desc
*arc_reg
,
168 const char * const type_name
, const size_t type_name_len
)
173 struct arc_common
*arc
= target_to_arc(target
);
176 /* Find register type */
178 struct arc_reg_data_type
*type
;
179 list_for_each_entry(type
, &arc
->reg_data_types
, list
)
180 if (!strncmp(type
->data_type
.id
, type_name
, type_name_len
)) {
181 arc_reg
->data_type
= &(type
->data_type
);
185 if (!arc_reg
->data_type
)
186 return ERROR_ARC_REGTYPE_NOT_FOUND
;
189 if (arc_reg
->is_core
) {
190 list_add_tail(&arc_reg
->list
, &arc
->core_reg_descriptions
);
191 arc
->num_core_regs
+= 1;
192 } else if (arc_reg
->is_bcr
) {
193 list_add_tail(&arc_reg
->list
, &arc
->bcr_reg_descriptions
);
194 arc
->num_bcr_regs
+= 1;
196 list_add_tail(&arc_reg
->list
, &arc
->aux_reg_descriptions
);
197 arc
->num_aux_regs
+= 1;
202 "added register {name=%s, num=0x%" PRIx32
", type=%s%s%s%s}",
203 arc_reg
->name
, arc_reg
->arch_num
, arc_reg
->data_type
->id
,
204 arc_reg
->is_core
? ", core" : "", arc_reg
->is_bcr
? ", bcr" : "",
205 arc_reg
->is_general
? ", general" : ""
211 /* Reading core or aux register */
212 static int arc_get_register(struct reg
*reg
)
216 struct arc_reg_desc
*desc
= reg
->arch_info
;
217 struct target
*target
= desc
->target
;
218 struct arc_common
*arc
= target_to_arc(target
);
223 LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32
", name=%s, value=0x%" PRIx32
,
224 reg
->number
, desc
->name
, target_buffer_get_u32(target
, reg
->value
));
229 /* Accessing to R61/R62 registers causes Jtag hang */
230 if (desc
->arch_num
== ARC_R61
|| desc
->arch_num
== ARC_R62
) {
231 LOG_ERROR("It is forbidden to read core registers 61 and 62.");
234 CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc
->jtag_info
, desc
->arch_num
,
237 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, desc
->arch_num
,
241 target_buffer_set_u32(target
, reg
->value
, value
);
243 /* If target is unhalted all register reads should be uncached. */
244 if (target
->state
== TARGET_HALTED
)
251 LOG_DEBUG("Get register gdb_num=%" PRIu32
", name=%s, value=0x%" PRIx32
,
252 reg
->number
, desc
->name
, value
);
258 /* Writing core or aux register */
259 static int arc_set_register(struct reg
*reg
, uint8_t *buf
)
261 struct arc_reg_desc
*desc
= reg
->arch_info
;
262 struct target
*target
= desc
->target
;
263 uint32_t value
= target_buffer_get_u32(target
, buf
);
264 /* Unlike "get" function "set" is supported only if target
265 * is in halt mode. Async writes are not supported yet. */
266 if (target
->state
!= TARGET_HALTED
)
267 return ERROR_TARGET_NOT_HALTED
;
269 /* Accessing to R61/R62 registers causes Jtag hang */
270 if (desc
->is_core
&& (desc
->arch_num
== ARC_R61
||
271 desc
->arch_num
== ARC_R62
)) {
272 LOG_ERROR("It is forbidden to write core registers 61 and 62.");
275 target_buffer_set_u32(target
, reg
->value
, value
);
277 LOG_DEBUG("Set register gdb_num=%" PRIu32
", name=%s, value=0x%08" PRIx32
,
278 reg
->number
, desc
->name
, value
);
286 static const struct reg_arch_type arc_reg_type
= {
287 .get
= arc_get_register
,
288 .set
= arc_set_register
,
291 /* GDB register groups. For now we support only general and "empty" */
292 static const char * const reg_group_general
= "general";
293 static const char * const reg_group_other
= "";
295 /* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
296 static int arc_init_reg(struct target
*target
, struct reg
*reg
,
297 struct arc_reg_desc
*reg_desc
, unsigned long number
)
303 struct arc_common
*arc
= target_to_arc(target
);
305 /* Initialize struct reg */
306 reg
->name
= reg_desc
->name
;
307 reg
->size
= 32; /* All register in ARC are 32-bit */
308 reg
->value
= reg_desc
->reg_value
;
309 reg
->type
= &arc_reg_type
;
310 reg
->arch_info
= reg_desc
;
311 reg
->caller_save
= true; /* @todo should be configurable. */
312 reg
->reg_data_type
= reg_desc
->data_type
;
313 reg
->feature
= ®_desc
->feature
;
315 reg
->feature
->name
= reg_desc
->gdb_xml_feature
;
317 /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
318 * value of a register GDB will use it as a number of register in
319 * P-packet. OpenOCD gdbserver will then use number of register in
320 * P-packet as an array index in the reg_list returned by
321 * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
322 * correctly it would be required to either sort registers in
323 * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
324 * according to how registers will be sorted in
325 * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
326 reg
->number
= number
;
328 if (reg_desc
->is_general
) {
329 arc
->last_general_reg
= reg
->number
;
330 reg
->group
= reg_group_general
;
332 reg
->group
= reg_group_other
;
338 /* Building aux/core reg_cache */
339 static int arc_build_reg_cache(struct target
*target
)
342 struct arc_reg_desc
*reg_desc
;
343 /* get pointers to arch-specific information */
344 struct arc_common
*arc
= target_to_arc(target
);
345 const unsigned long num_regs
= arc
->num_core_regs
+ arc
->num_aux_regs
;
346 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
347 struct reg_cache
*cache
= calloc(1, sizeof(*cache
));
348 struct reg
*reg_list
= calloc(num_regs
, sizeof(*reg_list
));
350 if (!cache
|| !reg_list
) {
351 LOG_ERROR("Not enough memory");
355 /* Build the process context cache */
356 cache
->name
= "arc registers";
358 cache
->reg_list
= reg_list
;
359 cache
->num_regs
= num_regs
;
360 arc
->core_and_aux_cache
= cache
;
363 if (list_empty(&arc
->core_reg_descriptions
)) {
364 LOG_ERROR("No core registers were defined");
368 list_for_each_entry(reg_desc
, &arc
->core_reg_descriptions
, list
) {
369 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, i
));
371 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
372 reg_list
[i
].name
, reg_list
[i
].group
,
373 reg_list
[i
].feature
->name
);
378 if (list_empty(&arc
->aux_reg_descriptions
)) {
379 LOG_ERROR("No aux registers were defined");
383 list_for_each_entry(reg_desc
, &arc
->aux_reg_descriptions
, list
) {
384 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, i
));
386 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
387 reg_list
[i
].name
, reg_list
[i
].group
,
388 reg_list
[i
].feature
->name
);
390 /* PC and DEBUG are essential so we search for them. */
391 if (!strcmp("pc", reg_desc
->name
)) {
392 if (arc
->pc_index_in_cache
!= ULONG_MAX
) {
393 LOG_ERROR("Double definition of PC in configuration");
396 arc
->pc_index_in_cache
= i
;
397 } else if (!strcmp("debug", reg_desc
->name
)) {
398 if (arc
->debug_index_in_cache
!= ULONG_MAX
) {
399 LOG_ERROR("Double definition of DEBUG in configuration");
402 arc
->debug_index_in_cache
= i
;
407 if (arc
->pc_index_in_cache
== ULONG_MAX
408 || arc
->debug_index_in_cache
== ULONG_MAX
) {
409 LOG_ERROR("`pc' and `debug' registers must be present in target description.");
413 assert(i
== (arc
->num_core_regs
+ arc
->num_aux_regs
));
415 arc
->core_aux_cache_built
= true;
426 /* Build bcr reg_cache.
427 * This function must be called only after arc_build_reg_cache */
428 static int arc_build_bcr_reg_cache(struct target
*target
)
430 /* get pointers to arch-specific information */
431 struct arc_common
*arc
= target_to_arc(target
);
432 const unsigned long num_regs
= arc
->num_bcr_regs
;
433 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
434 struct reg_cache
*cache
= malloc(sizeof(*cache
));
435 struct reg
*reg_list
= calloc(num_regs
, sizeof(*reg_list
));
437 struct arc_reg_desc
*reg_desc
;
439 unsigned long gdb_regnum
= arc
->core_and_aux_cache
->num_regs
;
441 if (!cache
|| !reg_list
) {
442 LOG_ERROR("Unable to allocate memory");
446 /* Build the process context cache */
447 cache
->name
= "arc.bcr";
449 cache
->reg_list
= reg_list
;
450 cache
->num_regs
= num_regs
;
451 arc
->bcr_cache
= cache
;
454 if (list_empty(&arc
->bcr_reg_descriptions
)) {
455 LOG_ERROR("No BCR registers are defined");
459 list_for_each_entry(reg_desc
, &arc
->bcr_reg_descriptions
, list
) {
460 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, gdb_regnum
));
461 /* BCRs always semantically, they are just read-as-zero, if there is
462 * not real register. */
463 reg_list
[i
].exist
= true;
465 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
466 reg_list
[i
].name
, reg_list
[i
].group
,
467 reg_list
[i
].feature
->name
);
472 assert(i
== arc
->num_bcr_regs
);
474 arc
->bcr_cache_built
= true;
486 static int arc_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
487 int *reg_list_size
, enum target_register_class reg_class
)
489 assert(target
->reg_cache
);
490 struct arc_common
*arc
= target_to_arc(target
);
492 /* get pointers to arch-specific information storage */
493 *reg_list_size
= arc
->num_regs
;
494 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
497 LOG_ERROR("Unable to allocate memory");
501 /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
502 * XML tdesc it filters out !exist registers, however when creating a
503 * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
504 * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
505 * out !exist register for "general", but not for "all". Attempts to filter out
506 * !exist for "all" as well will cause a failed check in OpenOCD GDB
508 if (reg_class
== REG_CLASS_ALL
) {
510 struct reg_cache
*reg_cache
= target
->reg_cache
;
512 for (unsigned j
= 0; j
< reg_cache
->num_regs
; j
++, i
++)
513 (*reg_list
)[i
] = ®_cache
->reg_list
[j
];
514 reg_cache
= reg_cache
->next
;
516 assert(i
== arc
->num_regs
);
517 LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size
);
520 unsigned long gdb_reg_number
= 0;
521 struct reg_cache
*reg_cache
= target
->reg_cache
;
524 j
< reg_cache
->num_regs
&& gdb_reg_number
<= arc
->last_general_reg
;
526 if (reg_cache
->reg_list
[j
].exist
) {
527 (*reg_list
)[i
] = ®_cache
->reg_list
[j
];
532 reg_cache
= reg_cache
->next
;
535 LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size
);
541 /* Reading field of struct_type register */
542 int arc_reg_get_field(struct target
*target
, const char *reg_name
,
543 const char *field_name
, uint32_t *value_ptr
)
545 struct reg_data_type_struct_field
*field
;
547 LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name
, field_name
);
550 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
553 LOG_ERROR("Requested register `%s' doesn't exist.", reg_name
);
554 return ERROR_ARC_REGISTER_NOT_FOUND
;
557 if (reg
->reg_data_type
->type
!= REG_TYPE_ARCH_DEFINED
558 || reg
->reg_data_type
->type_class
!= REG_TYPE_CLASS_STRUCT
)
559 return ERROR_ARC_REGISTER_IS_NOT_STRUCT
;
561 /* Get field in a register */
562 struct reg_data_type_struct
*reg_struct
=
563 reg
->reg_data_type
->reg_type_struct
;
564 for (field
= reg_struct
->fields
;
566 field
= field
->next
) {
567 if (!strcmp(field
->name
, field_name
))
572 return ERROR_ARC_REGISTER_FIELD_NOT_FOUND
;
574 if (!field
->use_bitfields
)
575 return ERROR_ARC_FIELD_IS_NOT_BITFIELD
;
578 CHECK_RETVAL(reg
->type
->get(reg
));
580 /* First do endianness-safe read of register value
581 * then convert it to binary buffer for further
582 * field extraction */
584 *value_ptr
= buf_get_u32(reg
->value
, field
->bitfield
->start
,
585 field
->bitfield
->end
- field
->bitfield
->start
+ 1);
590 static int arc_get_register_value(struct target
*target
, const char *reg_name
,
593 LOG_DEBUG("reg_name=%s", reg_name
);
595 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
598 return ERROR_ARC_REGISTER_NOT_FOUND
;
601 CHECK_RETVAL(reg
->type
->get(reg
));
603 *value_ptr
= target_buffer_get_u32(target
, reg
->value
);
608 static int arc_set_register_value(struct target
*target
, const char *reg_name
,
611 LOG_DEBUG("reg_name=%s value=0x%08" PRIx32
, reg_name
, value
);
613 if (!(target
&& reg_name
)) {
614 LOG_ERROR("Arguments cannot be NULL.");
618 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
621 return ERROR_ARC_REGISTER_NOT_FOUND
;
623 uint8_t value_buf
[4];
624 buf_set_u32(value_buf
, 0, 32, value
);
625 CHECK_RETVAL(reg
->type
->set(reg
, value_buf
));
630 /* Configure DCCM's */
631 static int arc_configure_dccm(struct target
*target
)
633 struct arc_common
*arc
= target_to_arc(target
);
635 uint32_t dccm_build_version
, dccm_build_size0
, dccm_build_size1
;
636 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "version",
637 &dccm_build_version
));
638 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "size0",
640 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "size1",
642 /* There is no yet support of configurable number of cycles,
643 * So there is no difference between v3 and v4 */
644 if ((dccm_build_version
== 3 || dccm_build_version
== 4) && dccm_build_size0
> 0) {
645 CHECK_RETVAL(arc_get_register_value(target
, "aux_dccm", &(arc
->dccm_start
)));
646 uint32_t dccm_size
= 0x100;
647 dccm_size
<<= dccm_build_size0
;
648 if (dccm_build_size0
== 0xF)
649 dccm_size
<<= dccm_build_size1
;
650 arc
->dccm_end
= arc
->dccm_start
+ dccm_size
;
651 LOG_DEBUG("DCCM detected start=0x%" PRIx32
" end=0x%" PRIx32
,
652 arc
->dccm_start
, arc
->dccm_end
);
659 /* Configure ICCM's */
661 static int arc_configure_iccm(struct target
*target
)
663 struct arc_common
*arc
= target_to_arc(target
);
666 uint32_t iccm_build_version
, iccm_build_size00
, iccm_build_size01
;
667 uint32_t aux_iccm
= 0;
668 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "version",
669 &iccm_build_version
));
670 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm0_size0",
671 &iccm_build_size00
));
672 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm0_size1",
673 &iccm_build_size01
));
674 if (iccm_build_version
== 4 && iccm_build_size00
> 0) {
675 CHECK_RETVAL(arc_get_register_value(target
, "aux_iccm", &aux_iccm
));
676 uint32_t iccm0_size
= 0x100;
677 iccm0_size
<<= iccm_build_size00
;
678 if (iccm_build_size00
== 0xF)
679 iccm0_size
<<= iccm_build_size01
;
680 /* iccm0 start is located in highest 4 bits of aux_iccm */
681 arc
->iccm0_start
= aux_iccm
& 0xF0000000;
682 arc
->iccm0_end
= arc
->iccm0_start
+ iccm0_size
;
683 LOG_DEBUG("ICCM0 detected start=0x%" PRIx32
" end=0x%" PRIx32
,
684 arc
->iccm0_start
, arc
->iccm0_end
);
688 uint32_t iccm_build_size10
, iccm_build_size11
;
689 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm1_size0",
690 &iccm_build_size10
));
691 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm1_size1",
692 &iccm_build_size11
));
693 if (iccm_build_version
== 4 && iccm_build_size10
> 0) {
694 /* Use value read for ICCM0 */
696 CHECK_RETVAL(arc_get_register_value(target
, "aux_iccm", &aux_iccm
));
697 uint32_t iccm1_size
= 0x100;
698 iccm1_size
<<= iccm_build_size10
;
699 if (iccm_build_size10
== 0xF)
700 iccm1_size
<<= iccm_build_size11
;
701 arc
->iccm1_start
= aux_iccm
& 0x0F000000;
702 arc
->iccm1_end
= arc
->iccm1_start
+ iccm1_size
;
703 LOG_DEBUG("ICCM1 detected start=0x%" PRIx32
" end=0x%" PRIx32
,
704 arc
->iccm1_start
, arc
->iccm1_end
);
709 /* Configure some core features, depending on BCRs. */
710 static int arc_configure(struct target
*target
)
712 LOG_DEBUG("Configuring ARC ICCM and DCCM");
714 /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
715 if (arc_reg_get_by_name(target
->reg_cache
, "dccm_build", true) &&
716 arc_reg_get_by_name(target
->reg_cache
, "aux_dccm", true))
717 CHECK_RETVAL(arc_configure_dccm(target
));
719 /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
720 if (arc_reg_get_by_name(target
->reg_cache
, "iccm_build", true) &&
721 arc_reg_get_by_name(target
->reg_cache
, "aux_iccm", true))
722 CHECK_RETVAL(arc_configure_iccm(target
));
727 /* arc_examine is function, which is used for all arc targets*/
728 static int arc_examine(struct target
*target
)
731 struct arc_common
*arc
= target_to_arc(target
);
733 CHECK_RETVAL(arc_jtag_startup(&arc
->jtag_info
));
735 if (!target_was_examined(target
)) {
736 CHECK_RETVAL(arc_jtag_status(&arc
->jtag_info
, &status
));
737 if (status
& ARC_JTAG_STAT_RU
)
738 target
->state
= TARGET_RUNNING
;
740 target
->state
= TARGET_HALTED
;
742 /* Read BCRs and configure optional registers. */
743 CHECK_RETVAL(arc_configure(target
));
745 target_set_examined(target
);
751 static int arc_halt(struct target
*target
)
753 uint32_t value
, irq_state
;
754 struct arc_common
*arc
= target_to_arc(target
);
756 LOG_DEBUG("target->state: %s", target_state_name(target
));
758 if (target
->state
== TARGET_HALTED
) {
759 LOG_DEBUG("target was already halted");
763 if (target
->state
== TARGET_UNKNOWN
)
764 LOG_WARNING("target was in unknown state when halt was requested");
766 if (target
->state
== TARGET_RESET
) {
767 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
768 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
769 return ERROR_TARGET_FAILURE
;
771 target
->debug_reason
= DBG_REASON_DBGRQ
;
775 /* Break (stop) processor.
776 * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
777 * We do not use here arc_get/set_core_reg functions here because they imply
778 * that the processor is already halted. */
779 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
, &value
));
780 value
|= SET_CORE_FORCE_HALT
; /* set the HALT bit */
781 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
, value
));
784 /* Save current IRQ state */
785 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &irq_state
));
787 if (irq_state
& AUX_STATUS32_REG_IE_BIT
)
792 /* update state and notify gdb*/
793 target
->state
= TARGET_HALTED
;
794 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
796 /* some more debug information */
797 if (debug_level
>= LOG_LVL_DEBUG
) {
798 LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32
, value
);
799 CHECK_RETVAL(arc_get_register_value(target
, "status32", &value
));
800 LOG_DEBUG("core STATUS32: 0x%08" PRIx32
, value
);
807 * Read registers that are used in GDB g-packet. We don't read them one-by-one,
808 * but do that in one batch operation to improve speed. Calls to JTAG layer are
809 * expensive so it is better to make one big call that reads all necessary
810 * registers, instead of many calls, one for one register.
812 static int arc_save_context(struct target
*target
)
814 int retval
= ERROR_OK
;
816 struct arc_common
*arc
= target_to_arc(target
);
817 struct reg
*reg_list
= arc
->core_and_aux_cache
->reg_list
;
819 LOG_DEBUG("Saving aux and core registers values");
822 /* It is assumed that there is at least one AUX register in the list, for
824 const uint32_t core_regs_size
= arc
->num_core_regs
* sizeof(uint32_t);
825 /* last_general_reg is inclusive number. To get count of registers it is
826 * required to do +1. */
827 const uint32_t regs_to_scan
=
828 MIN(arc
->last_general_reg
+ 1, arc
->num_regs
);
829 const uint32_t aux_regs_size
= arc
->num_aux_regs
* sizeof(uint32_t);
830 uint32_t *core_values
= malloc(core_regs_size
);
831 uint32_t *aux_values
= malloc(aux_regs_size
);
832 uint32_t *core_addrs
= malloc(core_regs_size
);
833 uint32_t *aux_addrs
= malloc(aux_regs_size
);
834 unsigned int core_cnt
= 0;
835 unsigned int aux_cnt
= 0;
837 if (!core_values
|| !core_addrs
|| !aux_values
|| !aux_addrs
) {
838 LOG_ERROR("Unable to allocate memory");
843 memset(core_values
, 0xff, core_regs_size
);
844 memset(core_addrs
, 0xff, core_regs_size
);
845 memset(aux_values
, 0xff, aux_regs_size
);
846 memset(aux_addrs
, 0xff, aux_regs_size
);
848 for (i
= 0; i
< MIN(arc
->num_core_regs
, regs_to_scan
); i
++) {
849 struct reg
*reg
= reg_list
+ i
;
850 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
851 if (!reg
->valid
&& reg
->exist
)
852 core_addrs
[core_cnt
++] = arc_reg
->arch_num
;
855 for (i
= arc
->num_core_regs
; i
< regs_to_scan
; i
++) {
856 struct reg
*reg
= reg_list
+ i
;
857 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
858 if (!reg
->valid
&& reg
->exist
)
859 aux_addrs
[aux_cnt
++] = arc_reg
->arch_num
;
862 /* Read data from target. */
864 retval
= arc_jtag_read_core_reg(&arc
->jtag_info
, core_addrs
, core_cnt
, core_values
);
865 if (retval
!= ERROR_OK
) {
866 LOG_ERROR("Attempt to read core registers failed.");
872 retval
= arc_jtag_read_aux_reg(&arc
->jtag_info
, aux_addrs
, aux_cnt
, aux_values
);
873 if (retval
!= ERROR_OK
) {
874 LOG_ERROR("Attempt to read aux registers failed.");
880 /* Parse core regs */
882 for (i
= 0; i
< MIN(arc
->num_core_regs
, regs_to_scan
); i
++) {
883 struct reg
*reg
= reg_list
+ i
;
884 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
885 if (!reg
->valid
&& reg
->exist
) {
886 target_buffer_set_u32(target
, reg
->value
, core_values
[core_cnt
]);
889 LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32
,
890 i
, arc_reg
->name
, core_values
[core_cnt
]);
897 for (i
= arc
->num_core_regs
; i
< regs_to_scan
; i
++) {
898 struct reg
*reg
= reg_list
+ i
;
899 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
900 if (!reg
->valid
&& reg
->exist
) {
901 target_buffer_set_u32(target
, reg
->value
, aux_values
[aux_cnt
]);
904 LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32
,
905 i
, arc_reg
->name
, aux_values
[aux_cnt
]);
920 * Finds an actionpoint that triggered last actionpoint event, as specified by
924 * @param actionpoint Pointer to be set to last active actionpoint. Pointer
925 * will be set to NULL if DEBUG.AH is 0.
927 static int get_current_actionpoint(struct target
*target
,
928 struct arc_actionpoint
**actionpoint
)
934 /* Check if actionpoint caused halt */
935 CHECK_RETVAL(arc_reg_get_field(target
, "debug", "ah",
939 struct arc_common
*arc
= target_to_arc(target
);
942 CHECK_RETVAL(arc_reg_get_field(target
, "debug",
945 for (ap
= 0; debug_asr
> 1; debug_asr
>>= 1)
948 assert(ap
< arc
->actionpoints_num
);
950 *actionpoint
= &(arc
->actionpoints_list
[ap
]);
958 static int arc_examine_debug_reason(struct target
*target
)
962 /* Only check for reason if don't know it already. */
963 /* BTW After singlestep at this point core is not marked as halted, so
964 * reading from memory to get current instruction wouldn't work anyway. */
965 if (target
->debug_reason
== DBG_REASON_DBGRQ
||
966 target
->debug_reason
== DBG_REASON_SINGLESTEP
) {
970 CHECK_RETVAL(arc_reg_get_field(target
, "debug", "bh",
974 /* DEBUG.BH is set if core halted due to BRK instruction. */
975 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
977 struct arc_actionpoint
*actionpoint
= NULL
;
978 CHECK_RETVAL(get_current_actionpoint(target
, &actionpoint
));
981 if (!actionpoint
->used
)
982 LOG_WARNING("Target halted by an unused actionpoint.");
984 if (actionpoint
->type
== ARC_AP_BREAKPOINT
)
985 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
986 else if (actionpoint
->type
== ARC_AP_WATCHPOINT
)
987 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
989 LOG_WARNING("Unknown type of actionpoint.");
996 static int arc_debug_entry(struct target
*target
)
998 CHECK_RETVAL(arc_save_context(target
));
1000 /* TODO: reset internal indicators of caches states, otherwise D$/I$
1001 * will not be flushed/invalidated when required. */
1002 CHECK_RETVAL(arc_reset_caches_states(target
));
1003 CHECK_RETVAL(arc_examine_debug_reason(target
));
1008 static int arc_poll(struct target
*target
)
1010 uint32_t status
, value
;
1011 struct arc_common
*arc
= target_to_arc(target
);
1013 /* gdb calls continuously through this arc_poll() function */
1014 CHECK_RETVAL(arc_jtag_status(&arc
->jtag_info
, &status
));
1016 /* check for processor halted */
1017 if (status
& ARC_JTAG_STAT_RU
) {
1018 if (target
->state
!= TARGET_RUNNING
) {
1019 LOG_WARNING("target is still running!");
1020 target
->state
= TARGET_RUNNING
;
1024 /* In some cases JTAG status register indicates that
1025 * processor is in halt mode, but processor is still running.
1026 * We check halt bit of AUX STATUS32 register for setting correct state. */
1027 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
)) {
1028 CHECK_RETVAL(arc_get_register_value(target
, "status32", &value
));
1029 if (value
& AUX_STATUS32_REG_HALT_BIT
) {
1030 LOG_DEBUG("ARC core in halt or reset state.");
1031 /* Save context if target was not in reset state */
1032 if (target
->state
== TARGET_RUNNING
)
1033 CHECK_RETVAL(arc_debug_entry(target
));
1034 target
->state
= TARGET_HALTED
;
1035 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1037 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
1038 "target is still running");
1041 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
1043 target
->state
= TARGET_HALTED
;
1044 LOG_DEBUG("ARC core is in debug running mode");
1046 CHECK_RETVAL(arc_debug_entry(target
));
1048 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
));
1054 static int arc_assert_reset(struct target
*target
)
1056 struct arc_common
*arc
= target_to_arc(target
);
1057 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1058 bool srst_asserted
= false;
1060 LOG_DEBUG("target->state: %s", target_state_name(target
));
1062 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1063 /* allow scripts to override the reset event */
1065 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1066 register_cache_invalidate(arc
->core_and_aux_cache
);
1067 /* An ARC target might be in halt state after reset, so
1068 * if script requested processor to resume, then it must
1069 * be manually started to ensure that this request
1071 if (target
->state
== TARGET_HALTED
&& !target
->reset_halt
) {
1072 /* Resume the target and continue from the current
1073 * PC register value. */
1074 LOG_DEBUG("Starting CPU execution after reset");
1075 CHECK_RETVAL(target_resume(target
, 1, 0, 0, 0));
1077 target
->state
= TARGET_RESET
;
1082 /* some cores support connecting while srst is asserted
1083 * use that mode if it has been configured */
1084 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
1085 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1086 jtag_add_reset(0, 1);
1087 srst_asserted
= true;
1090 if (jtag_reset_config
& RESET_HAS_SRST
) {
1091 /* should issue a srst only, but we may have to assert trst as well */
1092 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1093 jtag_add_reset(1, 1);
1094 else if (!srst_asserted
)
1095 jtag_add_reset(0, 1);
1098 target
->state
= TARGET_RESET
;
1099 jtag_add_sleep(50000);
1101 register_cache_invalidate(arc
->core_and_aux_cache
);
1103 if (target
->reset_halt
)
1104 CHECK_RETVAL(target_halt(target
));
1109 static int arc_deassert_reset(struct target
*target
)
1111 LOG_DEBUG("target->state: %s", target_state_name(target
));
1113 /* deassert reset lines */
1114 jtag_add_reset(0, 0);
1119 static int arc_arch_state(struct target
*target
)
1123 if (debug_level
< LOG_LVL_DEBUG
)
1126 CHECK_RETVAL(arc_get_register_value(target
, "pc", &pc_value
));
1128 LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32
,
1129 target_state_name(target
),
1136 * See arc_save_context() for reason why we want to dump all regs at once.
1137 * This however means that if there are dependencies between registers they
1138 * will not be observable until target will be resumed.
1140 static int arc_restore_context(struct target
*target
)
1142 int retval
= ERROR_OK
;
1144 struct arc_common
*arc
= target_to_arc(target
);
1145 struct reg
*reg_list
= arc
->core_and_aux_cache
->reg_list
;
1147 LOG_DEBUG("Restoring registers values");
1150 const uint32_t core_regs_size
= arc
->num_core_regs
* sizeof(uint32_t);
1151 const uint32_t aux_regs_size
= arc
->num_aux_regs
* sizeof(uint32_t);
1152 uint32_t *core_values
= malloc(core_regs_size
);
1153 uint32_t *aux_values
= malloc(aux_regs_size
);
1154 uint32_t *core_addrs
= malloc(core_regs_size
);
1155 uint32_t *aux_addrs
= malloc(aux_regs_size
);
1156 unsigned int core_cnt
= 0;
1157 unsigned int aux_cnt
= 0;
1159 if (!core_values
|| !core_addrs
|| !aux_values
|| !aux_addrs
) {
1160 LOG_ERROR("Unable to allocate memory");
1161 retval
= ERROR_FAIL
;
1165 memset(core_values
, 0xff, core_regs_size
);
1166 memset(core_addrs
, 0xff, core_regs_size
);
1167 memset(aux_values
, 0xff, aux_regs_size
);
1168 memset(aux_addrs
, 0xff, aux_regs_size
);
1170 for (i
= 0; i
< arc
->num_core_regs
; i
++) {
1171 struct reg
*reg
= &(reg_list
[i
]);
1172 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
1173 if (reg
->valid
&& reg
->exist
&& reg
->dirty
) {
1174 LOG_DEBUG("Will write regnum=%u", i
);
1175 core_addrs
[core_cnt
] = arc_reg
->arch_num
;
1176 core_values
[core_cnt
] = target_buffer_get_u32(target
, reg
->value
);
1181 for (i
= 0; i
< arc
->num_aux_regs
; i
++) {
1182 struct reg
*reg
= &(reg_list
[arc
->num_core_regs
+ i
]);
1183 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
1184 if (reg
->valid
&& reg
->exist
&& reg
->dirty
) {
1185 LOG_DEBUG("Will write regnum=%lu", arc
->num_core_regs
+ i
);
1186 aux_addrs
[aux_cnt
] = arc_reg
->arch_num
;
1187 aux_values
[aux_cnt
] = target_buffer_get_u32(target
, reg
->value
);
1192 /* Write data to target.
1193 * Check before write, if aux and core count is greater than 0. */
1195 retval
= arc_jtag_write_core_reg(&arc
->jtag_info
, core_addrs
, core_cnt
, core_values
);
1196 if (retval
!= ERROR_OK
) {
1197 LOG_ERROR("Attempt to write to core registers failed.");
1198 retval
= ERROR_FAIL
;
1204 retval
= arc_jtag_write_aux_reg(&arc
->jtag_info
, aux_addrs
, aux_cnt
, aux_values
);
1205 if (retval
!= ERROR_OK
) {
1206 LOG_ERROR("Attempt to write to aux registers failed.");
1207 retval
= ERROR_FAIL
;
1221 static int arc_enable_interrupts(struct target
*target
, int enable
)
1225 struct arc_common
*arc
= target_to_arc(target
);
1227 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &value
));
1230 /* enable interrupts */
1231 value
|= SET_CORE_ENABLE_INTERRUPTS
;
1232 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1233 LOG_DEBUG("interrupts enabled");
1235 /* disable interrupts */
1236 value
&= ~SET_CORE_ENABLE_INTERRUPTS
;
1237 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1238 LOG_DEBUG("interrupts disabled");
1244 static int arc_resume(struct target
*target
, int current
, target_addr_t address
,
1245 int handle_breakpoints
, int debug_execution
)
1247 struct arc_common
*arc
= target_to_arc(target
);
1248 uint32_t resume_pc
= 0;
1250 struct reg
*pc
= &arc
->core_and_aux_cache
->reg_list
[arc
->pc_index_in_cache
];
1252 LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR
", handle_breakpoints(not supported yet):%i,"
1253 " debug_execution:%i", current
, address
, handle_breakpoints
, debug_execution
);
1255 /* We need to reset ARC cache variables so caches
1256 * would be invalidated and actual data
1257 * would be fetched from memory. */
1258 CHECK_RETVAL(arc_reset_caches_states(target
));
1260 if (target
->state
!= TARGET_HALTED
) {
1261 LOG_TARGET_ERROR(target
, "not halted");
1262 return ERROR_TARGET_NOT_HALTED
;
1265 /* current = 1: continue on current PC, otherwise continue at <address> */
1267 target_buffer_set_u32(target
, pc
->value
, address
);
1270 LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR
, address
);
1274 resume_pc
= address
;
1276 resume_pc
= target_buffer_get_u32(target
, pc
->value
);
1278 CHECK_RETVAL(arc_restore_context(target
));
1280 LOG_DEBUG("Target resumes from PC=0x%" PRIx32
", pc.dirty=%i, pc.valid=%i",
1281 resume_pc
, pc
->dirty
, pc
->valid
);
1283 /* check if GDB tells to set our PC where to continue from */
1284 if (pc
->valid
&& resume_pc
== target_buffer_get_u32(target
, pc
->value
)) {
1285 value
= target_buffer_get_u32(target
, pc
->value
);
1286 LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32
, value
);
1287 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_PC_REG
, value
));
1290 /* Restore IRQ state if not in debug_execution*/
1291 if (!debug_execution
)
1292 CHECK_RETVAL(arc_enable_interrupts(target
, arc
->irq_state
));
1294 CHECK_RETVAL(arc_enable_interrupts(target
, !debug_execution
));
1296 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1298 /* ready to get us going again */
1299 target
->state
= TARGET_RUNNING
;
1300 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &value
));
1301 value
&= ~SET_CORE_HALT_BIT
; /* clear the HALT bit */
1302 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1303 LOG_DEBUG("Core started to run");
1305 /* registers are now invalid */
1306 register_cache_invalidate(arc
->core_and_aux_cache
);
1308 if (!debug_execution
) {
1309 target
->state
= TARGET_RUNNING
;
1310 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
1311 LOG_DEBUG("target resumed at 0x%08" PRIx32
, resume_pc
);
1313 target
->state
= TARGET_DEBUG_RUNNING
;
1314 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
));
1315 LOG_DEBUG("target debug resumed at 0x%08" PRIx32
, resume_pc
);
1321 static int arc_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
1323 CHECK_RETVAL(arc_build_reg_cache(target
));
1324 CHECK_RETVAL(arc_build_bcr_reg_cache(target
));
1325 target
->debug_reason
= DBG_REASON_DBGRQ
;
1329 static void arc_free_reg_cache(struct reg_cache
*cache
)
1331 free(cache
->reg_list
);
1335 static void arc_deinit_target(struct target
*target
)
1337 struct arc_common
*arc
= target_to_arc(target
);
1339 LOG_DEBUG("deinitialization of target");
1340 if (arc
->core_aux_cache_built
)
1341 arc_free_reg_cache(arc
->core_and_aux_cache
);
1342 if (arc
->bcr_cache_built
)
1343 arc_free_reg_cache(arc
->bcr_cache
);
1345 struct arc_reg_data_type
*type
, *n
;
1346 struct arc_reg_desc
*desc
, *k
;
1348 /* Free arc-specific reg_data_types allocations*/
1349 list_for_each_entry_safe_reverse(type
, n
, &arc
->reg_data_types
, list
) {
1350 if (type
->data_type
.type_class
== REG_TYPE_CLASS_STRUCT
) {
1351 free(type
->reg_type_struct_field
);
1352 free(type
->bitfields
);
1354 } else if (type
->data_type
.type_class
== REG_TYPE_CLASS_FLAGS
) {
1355 free(type
->reg_type_flags_field
);
1356 free(type
->bitfields
);
1361 /* Free standard_gdb_types reg_data_types allocations */
1362 type
= list_first_entry(&arc
->reg_data_types
, struct arc_reg_data_type
, list
);
1365 list_for_each_entry_safe(desc
, k
, &arc
->aux_reg_descriptions
, list
)
1366 free_reg_desc(desc
);
1368 list_for_each_entry_safe(desc
, k
, &arc
->core_reg_descriptions
, list
)
1369 free_reg_desc(desc
);
1371 list_for_each_entry_safe(desc
, k
, &arc
->bcr_reg_descriptions
, list
)
1372 free_reg_desc(desc
);
1374 free(arc
->actionpoints_list
);
1379 static int arc_target_create(struct target
*target
, Jim_Interp
*interp
)
1381 struct arc_common
*arc
= calloc(1, sizeof(*arc
));
1384 LOG_ERROR("Unable to allocate memory");
1388 LOG_DEBUG("Entering");
1389 CHECK_RETVAL(arc_init_arch_info(target
, arc
, target
->tap
));
1395 * Write 4-byte instruction to memory. This is like target_write_u32, however
1396 * in case of little endian ARC instructions are in middle endian format, not
1397 * little endian, so different type of conversion should be done.
1398 * Middle endian: instruction "aabbccdd", stored as "bbaaddcc"
1400 static int arc_write_instruction_u32(struct target
*target
, uint32_t address
,
1403 uint8_t value_buf
[4];
1404 if (!target_was_examined(target
)) {
1405 LOG_ERROR("Target not examined yet");
1409 LOG_DEBUG("Address: 0x%08" PRIx32
", value: 0x%08" PRIx32
, address
,
1412 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
1413 arc_h_u32_to_me(value_buf
, instr
);
1415 h_u32_to_be(value_buf
, instr
);
1417 CHECK_RETVAL(target_write_buffer(target
, address
, 4, value_buf
));
1423 * Read 32-bit instruction from memory. It is like target_read_u32, however in
1424 * case of little endian ARC instructions are in middle endian format, so
1425 * different type of conversion should be done.
1427 static int arc_read_instruction_u32(struct target
*target
, uint32_t address
,
1430 uint8_t value_buf
[4];
1432 if (!target_was_examined(target
)) {
1433 LOG_ERROR("Target not examined yet");
1438 CHECK_RETVAL(target_read_buffer(target
, address
, 4, value_buf
));
1440 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
1441 *value
= arc_me_to_h_u32(value_buf
);
1443 *value
= be_to_h_u32(value_buf
);
1445 LOG_DEBUG("Address: 0x%08" PRIx32
", value: 0x%08" PRIx32
, address
,
1451 /* Actionpoint mechanism allows to setup HW breakpoints
1452 * and watchpoints. Each actionpoint is controlled by
1453 * 3 aux registers: Actionpoint(AP) match mask(AP_AMM), AP match value(AP_AMV)
1454 * and AP control(AC).
1455 * This function is for setting/unsetting actionpoints:
1456 * at - actionpoint target: trigger on mem/reg access
1457 * tt - transaction type : trigger on r/w. */
1458 static int arc_configure_actionpoint(struct target
*target
, uint32_t ap_num
,
1459 uint32_t match_value
, uint32_t control_tt
, uint32_t control_at
)
1461 struct arc_common
*arc
= target_to_arc(target
);
1463 if (control_tt
!= AP_AC_TT_DISABLE
) {
1465 if (arc
->actionpoints_num_avail
< 1) {
1466 LOG_ERROR("No free actionpoints, maximum amount is %u",
1467 arc
->actionpoints_num
);
1468 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1471 /* Names of register to set - 24 chars should be enough. Looks a little
1472 * bit out-of-place for C code, but makes it aligned to the bigger
1473 * concept of "ARC registers are defined in TCL" as far as possible.
1475 char ap_amv_reg_name
[24], ap_amm_reg_name
[24], ap_ac_reg_name
[24];
1476 snprintf(ap_amv_reg_name
, 24, "ap_amv%" PRIu32
, ap_num
);
1477 snprintf(ap_amm_reg_name
, 24, "ap_amm%" PRIu32
, ap_num
);
1478 snprintf(ap_ac_reg_name
, 24, "ap_ac%" PRIu32
, ap_num
);
1479 CHECK_RETVAL(arc_set_register_value(target
, ap_amv_reg_name
,
1481 CHECK_RETVAL(arc_set_register_value(target
, ap_amm_reg_name
, 0));
1482 CHECK_RETVAL(arc_set_register_value(target
, ap_ac_reg_name
,
1483 control_tt
| control_at
));
1484 arc
->actionpoints_num_avail
--;
1486 char ap_ac_reg_name
[24];
1487 snprintf(ap_ac_reg_name
, 24, "ap_ac%" PRIu32
, ap_num
);
1488 CHECK_RETVAL(arc_set_register_value(target
, ap_ac_reg_name
,
1490 arc
->actionpoints_num_avail
++;
1496 static int arc_set_breakpoint(struct target
*target
,
1497 struct breakpoint
*breakpoint
)
1499 if (breakpoint
->is_set
) {
1500 LOG_WARNING("breakpoint already set");
1504 if (breakpoint
->type
== BKPT_SOFT
) {
1505 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1507 if (breakpoint
->length
== 4) {
1508 uint32_t verify
= 0xffffffff;
1510 CHECK_RETVAL(target_read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1511 breakpoint
->orig_instr
));
1513 CHECK_RETVAL(arc_write_instruction_u32(target
, breakpoint
->address
,
1516 CHECK_RETVAL(arc_read_instruction_u32(target
, breakpoint
->address
, &verify
));
1518 if (verify
!= ARC_SDBBP_32
) {
1519 LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
1520 " - check that memory is read/writable", breakpoint
->address
);
1523 } else if (breakpoint
->length
== 2) {
1524 uint16_t verify
= 0xffff;
1526 CHECK_RETVAL(target_read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1527 breakpoint
->orig_instr
));
1528 CHECK_RETVAL(target_write_u16(target
, breakpoint
->address
, ARC_SDBBP_16
));
1530 CHECK_RETVAL(target_read_u16(target
, breakpoint
->address
, &verify
));
1531 if (verify
!= ARC_SDBBP_16
) {
1532 LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
1533 " - check that memory is read/writable", breakpoint
->address
);
1537 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1538 return ERROR_COMMAND_ARGUMENT_INVALID
;
1541 breakpoint
->is_set
= true;
1542 } else if (breakpoint
->type
== BKPT_HARD
) {
1543 struct arc_common
*arc
= target_to_arc(target
);
1544 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1545 unsigned int bp_num
;
1547 for (bp_num
= 0; bp_num
< arc
->actionpoints_num
; bp_num
++) {
1548 if (!ap_list
[bp_num
].used
)
1552 if (bp_num
>= arc
->actionpoints_num
) {
1553 LOG_ERROR("No free actionpoints, maximum amount is %u",
1554 arc
->actionpoints_num
);
1555 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1558 int retval
= arc_configure_actionpoint(target
, bp_num
,
1559 breakpoint
->address
, AP_AC_TT_READWRITE
, AP_AC_AT_INST_ADDR
);
1561 if (retval
== ERROR_OK
) {
1562 breakpoint_hw_set(breakpoint
, bp_num
);
1563 ap_list
[bp_num
].used
= 1;
1564 ap_list
[bp_num
].bp_value
= breakpoint
->address
;
1565 ap_list
[bp_num
].type
= ARC_AP_BREAKPOINT
;
1567 LOG_DEBUG("bpid: %" PRIu32
", bp_num %u bp_value 0x%" PRIx32
,
1568 breakpoint
->unique_id
, bp_num
, ap_list
[bp_num
].bp_value
);
1572 LOG_DEBUG("ERROR: setting unknown breakpoint type");
1579 static int arc_unset_breakpoint(struct target
*target
,
1580 struct breakpoint
*breakpoint
)
1582 int retval
= ERROR_OK
;
1584 if (!breakpoint
->is_set
) {
1585 LOG_WARNING("breakpoint not set");
1589 if (breakpoint
->type
== BKPT_SOFT
) {
1590 /* restore original instruction (kept in target endianness) */
1591 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1592 if (breakpoint
->length
== 4) {
1593 uint32_t current_instr
;
1595 /* check that user program has not modified breakpoint instruction */
1596 CHECK_RETVAL(arc_read_instruction_u32(target
, breakpoint
->address
, ¤t_instr
));
1598 if (current_instr
== ARC_SDBBP_32
) {
1599 retval
= target_write_buffer(target
, breakpoint
->address
,
1600 breakpoint
->length
, breakpoint
->orig_instr
);
1601 if (retval
!= ERROR_OK
)
1604 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1605 " has been overwritten outside of debugger."
1606 "Expected: @0x%x, got: @0x%" PRIx32
,
1607 breakpoint
->address
, ARC_SDBBP_32
, current_instr
);
1609 } else if (breakpoint
->length
== 2) {
1610 uint16_t current_instr
;
1612 /* check that user program has not modified breakpoint instruction */
1613 CHECK_RETVAL(target_read_u16(target
, breakpoint
->address
, ¤t_instr
));
1614 if (current_instr
== ARC_SDBBP_16
) {
1615 retval
= target_write_buffer(target
, breakpoint
->address
,
1616 breakpoint
->length
, breakpoint
->orig_instr
);
1617 if (retval
!= ERROR_OK
)
1620 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1621 " has been overwritten outside of debugger. "
1622 "Expected: 0x%04x, got: 0x%04" PRIx16
,
1623 breakpoint
->address
, ARC_SDBBP_16
, current_instr
);
1626 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1627 return ERROR_COMMAND_ARGUMENT_INVALID
;
1629 breakpoint
->is_set
= false;
1631 } else if (breakpoint
->type
== BKPT_HARD
) {
1632 struct arc_common
*arc
= target_to_arc(target
);
1633 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1634 unsigned int bp_num
= breakpoint
->number
;
1636 if (bp_num
>= arc
->actionpoints_num
) {
1637 LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32
,
1638 bp_num
, breakpoint
->unique_id
);
1642 retval
= arc_configure_actionpoint(target
, bp_num
,
1643 breakpoint
->address
, AP_AC_TT_DISABLE
, AP_AC_AT_INST_ADDR
);
1645 if (retval
== ERROR_OK
) {
1646 breakpoint
->is_set
= false;
1647 ap_list
[bp_num
].used
= 0;
1648 ap_list
[bp_num
].bp_value
= 0;
1650 LOG_DEBUG("bpid: %" PRIu32
" - released actionpoint ID: %u",
1651 breakpoint
->unique_id
, bp_num
);
1654 LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
1662 static int arc_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1664 if (target
->state
== TARGET_HALTED
) {
1665 return arc_set_breakpoint(target
, breakpoint
);
1668 LOG_TARGET_ERROR(target
, "not halted (add breakpoint)");
1669 return ERROR_TARGET_NOT_HALTED
;
1673 static int arc_remove_breakpoint(struct target
*target
,
1674 struct breakpoint
*breakpoint
)
1676 if (target
->state
== TARGET_HALTED
) {
1677 if (breakpoint
->is_set
)
1678 CHECK_RETVAL(arc_unset_breakpoint(target
, breakpoint
));
1680 LOG_TARGET_ERROR(target
, "not halted (remove breakpoint)");
1681 return ERROR_TARGET_NOT_HALTED
;
1687 static void arc_reset_actionpoints(struct target
*target
)
1689 struct arc_common
*arc
= target_to_arc(target
);
1690 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1691 struct breakpoint
*next_b
;
1692 struct watchpoint
*next_w
;
1694 while (target
->breakpoints
) {
1695 next_b
= target
->breakpoints
->next
;
1696 arc_remove_breakpoint(target
, target
->breakpoints
);
1697 free(target
->breakpoints
->orig_instr
);
1698 free(target
->breakpoints
);
1699 target
->breakpoints
= next_b
;
1701 while (target
->watchpoints
) {
1702 next_w
= target
->watchpoints
->next
;
1703 arc_remove_watchpoint(target
, target
->watchpoints
);
1704 free(target
->watchpoints
);
1705 target
->watchpoints
= next_w
;
1707 for (unsigned int i
= 0; i
< arc
->actionpoints_num
; i
++) {
1708 if ((ap_list
[i
].used
) && (ap_list
[i
].reg_address
))
1709 arc_remove_auxreg_actionpoint(target
, ap_list
[i
].reg_address
);
1713 int arc_set_actionpoints_num(struct target
*target
, uint32_t ap_num
)
1715 LOG_DEBUG("target=%s actionpoints=%" PRIu32
, target_name(target
), ap_num
);
1716 struct arc_common
*arc
= target_to_arc(target
);
1718 /* Make sure that there are no enabled actionpoints in target. */
1719 arc_reset_actionpoints(target
);
1721 /* Assume that all points have been removed from target. */
1722 free(arc
->actionpoints_list
);
1724 arc
->actionpoints_num_avail
= ap_num
;
1725 arc
->actionpoints_num
= ap_num
;
1726 /* calloc can be safely called when ncount == 0. */
1727 arc
->actionpoints_list
= calloc(ap_num
, sizeof(struct arc_actionpoint
));
1729 if (!arc
->actionpoints_list
) {
1730 LOG_ERROR("Unable to allocate memory");
1737 int arc_add_auxreg_actionpoint(struct target
*target
,
1738 uint32_t auxreg_addr
, uint32_t transaction
)
1740 unsigned int ap_num
= 0;
1741 int retval
= ERROR_OK
;
1743 if (target
->state
!= TARGET_HALTED
)
1744 return ERROR_TARGET_NOT_HALTED
;
1746 struct arc_common
*arc
= target_to_arc(target
);
1747 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1749 while (ap_list
[ap_num
].used
)
1752 if (ap_num
>= arc
->actionpoints_num
) {
1753 LOG_ERROR("No actionpoint free, maximum amount is %u",
1754 arc
->actionpoints_num
);
1755 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1758 retval
= arc_configure_actionpoint(target
, ap_num
,
1759 auxreg_addr
, transaction
, AP_AC_AT_AUXREG_ADDR
);
1761 if (retval
== ERROR_OK
) {
1762 ap_list
[ap_num
].used
= 1;
1763 ap_list
[ap_num
].reg_address
= auxreg_addr
;
1769 int arc_remove_auxreg_actionpoint(struct target
*target
, uint32_t auxreg_addr
)
1771 int retval
= ERROR_OK
;
1772 bool ap_found
= false;
1773 unsigned int ap_num
= 0;
1775 if (target
->state
!= TARGET_HALTED
)
1776 return ERROR_TARGET_NOT_HALTED
;
1778 struct arc_common
*arc
= target_to_arc(target
);
1779 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1781 while ((ap_list
[ap_num
].used
) && (ap_num
< arc
->actionpoints_num
)) {
1782 if (ap_list
[ap_num
].reg_address
== auxreg_addr
) {
1790 retval
= arc_configure_actionpoint(target
, ap_num
,
1791 auxreg_addr
, AP_AC_TT_DISABLE
, AP_AC_AT_AUXREG_ADDR
);
1793 if (retval
== ERROR_OK
) {
1794 ap_list
[ap_num
].used
= 0;
1795 ap_list
[ap_num
].bp_value
= 0;
1798 LOG_ERROR("Register actionpoint not found");
1804 static int arc_set_watchpoint(struct target
*target
,
1805 struct watchpoint
*watchpoint
)
1807 unsigned int wp_num
;
1808 struct arc_common
*arc
= target_to_arc(target
);
1809 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1811 if (watchpoint
->is_set
) {
1812 LOG_WARNING("watchpoint already set");
1816 for (wp_num
= 0; wp_num
< arc
->actionpoints_num
; wp_num
++) {
1817 if (!ap_list
[wp_num
].used
)
1821 if (wp_num
>= arc
->actionpoints_num
) {
1822 LOG_ERROR("No free actionpoints, maximum amount is %u",
1823 arc
->actionpoints_num
);
1824 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1827 if (watchpoint
->length
!= 4) {
1828 LOG_ERROR("Only watchpoints of length 4 are supported");
1829 return ERROR_TARGET_UNALIGNED_ACCESS
;
1832 int enable
= AP_AC_TT_DISABLE
;
1833 switch (watchpoint
->rw
) {
1835 enable
= AP_AC_TT_READ
;
1838 enable
= AP_AC_TT_WRITE
;
1841 enable
= AP_AC_TT_READWRITE
;
1844 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
1848 int retval
= arc_configure_actionpoint(target
, wp_num
,
1849 watchpoint
->address
, enable
, AP_AC_AT_MEMORY_ADDR
);
1851 if (retval
== ERROR_OK
) {
1852 watchpoint_set(watchpoint
, wp_num
);
1853 ap_list
[wp_num
].used
= 1;
1854 ap_list
[wp_num
].bp_value
= watchpoint
->address
;
1855 ap_list
[wp_num
].type
= ARC_AP_WATCHPOINT
;
1857 LOG_DEBUG("wpid: %" PRIu32
", wp_num %u wp_value 0x%" PRIx32
,
1858 watchpoint
->unique_id
, wp_num
, ap_list
[wp_num
].bp_value
);
1864 static int arc_unset_watchpoint(struct target
*target
,
1865 struct watchpoint
*watchpoint
)
1867 /* get pointers to arch-specific information */
1868 struct arc_common
*arc
= target_to_arc(target
);
1869 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1871 if (!watchpoint
->is_set
) {
1872 LOG_WARNING("watchpoint not set");
1876 unsigned int wp_num
= watchpoint
->number
;
1877 if (wp_num
>= arc
->actionpoints_num
) {
1878 LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32
,
1879 wp_num
, watchpoint
->unique_id
);
1883 int retval
= arc_configure_actionpoint(target
, wp_num
,
1884 watchpoint
->address
, AP_AC_TT_DISABLE
, AP_AC_AT_MEMORY_ADDR
);
1886 if (retval
== ERROR_OK
) {
1887 watchpoint
->is_set
= false;
1888 ap_list
[wp_num
].used
= 0;
1889 ap_list
[wp_num
].bp_value
= 0;
1891 LOG_DEBUG("wpid: %" PRIu32
" - releasing actionpoint ID: %u",
1892 watchpoint
->unique_id
, wp_num
);
1898 static int arc_add_watchpoint(struct target
*target
,
1899 struct watchpoint
*watchpoint
)
1901 if (target
->state
!= TARGET_HALTED
) {
1902 LOG_TARGET_ERROR(target
, "not halted");
1903 return ERROR_TARGET_NOT_HALTED
;
1906 CHECK_RETVAL(arc_set_watchpoint(target
, watchpoint
));
1911 static int arc_remove_watchpoint(struct target
*target
,
1912 struct watchpoint
*watchpoint
)
1914 if (target
->state
!= TARGET_HALTED
) {
1915 LOG_TARGET_ERROR(target
, "not halted");
1916 return ERROR_TARGET_NOT_HALTED
;
1919 if (watchpoint
->is_set
)
1920 CHECK_RETVAL(arc_unset_watchpoint(target
, watchpoint
));
1925 static int arc_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
1928 assert(hit_watchpoint
);
1930 struct arc_actionpoint
*actionpoint
= NULL
;
1931 CHECK_RETVAL(get_current_actionpoint(target
, &actionpoint
));
1934 if (!actionpoint
->used
)
1935 LOG_WARNING("Target halted by unused actionpoint.");
1937 /* If this check fails - that is some sort of an error in OpenOCD. */
1938 if (actionpoint
->type
!= ARC_AP_WATCHPOINT
)
1939 LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint.");
1941 for (struct watchpoint
*watchpoint
= target
->watchpoints
;
1943 watchpoint
= watchpoint
->next
) {
1944 if (actionpoint
->bp_value
== watchpoint
->address
) {
1945 *hit_watchpoint
= watchpoint
;
1946 LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32
", watchpoint num: %u",
1947 watchpoint
->unique_id
, watchpoint
->number
);
1956 /* Helper function which switches core to single_step mode by
1957 * doing aux r/w operations. */
1958 static int arc_config_step(struct target
*target
, int enable_step
)
1962 struct arc_common
*arc
= target_to_arc(target
);
1964 /* enable core debug step mode */
1966 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
,
1968 value
&= ~SET_CORE_AE_BIT
; /* clear the AE bit */
1969 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
,
1971 LOG_DEBUG(" [status32:0x%08" PRIx32
"]", value
);
1973 /* Doing read-modify-write, because DEBUG might contain manually set
1974 * bits like UB or ED, which should be preserved. */
1975 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
,
1976 AUX_DEBUG_REG
, &value
));
1977 value
|= SET_CORE_SINGLE_INSTR_STEP
; /* set the IS bit */
1978 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1980 LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32
"]", value
);
1982 } else { /* disable core debug step mode */
1983 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1985 value
&= ~SET_CORE_SINGLE_INSTR_STEP
; /* clear the IS bit */
1986 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1988 LOG_DEBUG("core debug step mode disabled");
1994 static int arc_step(struct target
*target
, int current
, target_addr_t address
,
1995 int handle_breakpoints
)
1997 /* get pointers to arch-specific information */
1998 struct arc_common
*arc
= target_to_arc(target
);
1999 struct breakpoint
*breakpoint
= NULL
;
2000 struct reg
*pc
= &(arc
->core_and_aux_cache
->reg_list
[arc
->pc_index_in_cache
]);
2002 if (target
->state
!= TARGET_HALTED
) {
2003 LOG_TARGET_ERROR(target
, "not halted");
2004 return ERROR_TARGET_NOT_HALTED
;
2007 /* current = 1: continue on current pc, otherwise continue at <address> */
2009 buf_set_u32(pc
->value
, 0, 32, address
);
2014 LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32
,
2015 buf_get_u32(pc
->value
, 0, 32));
2017 /* the front-end may request us not to handle breakpoints */
2018 if (handle_breakpoints
) {
2019 breakpoint
= breakpoint_find(target
, buf_get_u32(pc
->value
, 0, 32));
2021 CHECK_RETVAL(arc_unset_breakpoint(target
, breakpoint
));
2024 /* restore context */
2025 CHECK_RETVAL(arc_restore_context(target
));
2027 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2029 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
2031 /* disable interrupts while stepping */
2032 CHECK_RETVAL(arc_enable_interrupts(target
, 0));
2034 /* do a single step */
2035 CHECK_RETVAL(arc_config_step(target
, 1));
2037 /* make sure we done our step */
2040 /* registers are now invalid */
2041 register_cache_invalidate(arc
->core_and_aux_cache
);
2044 CHECK_RETVAL(arc_set_breakpoint(target
, breakpoint
));
2046 LOG_DEBUG("target stepped ");
2048 target
->state
= TARGET_HALTED
;
2050 /* Saving context */
2051 CHECK_RETVAL(arc_debug_entry(target
));
2052 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
2058 /* This function invalidates icache. */
2059 static int arc_icache_invalidate(struct target
*target
)
2063 struct arc_common
*arc
= target_to_arc(target
);
2065 /* Don't waste time if already done. */
2066 if (!arc
->has_icache
|| arc
->icache_invalidated
)
2069 LOG_DEBUG("Invalidating I$.");
2071 value
= IC_IVIC_INVALIDATE
; /* invalidate I$ */
2072 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_IC_IVIC_REG
, value
));
2074 arc
->icache_invalidated
= true;
2079 /* This function invalidates dcache */
2080 static int arc_dcache_invalidate(struct target
*target
)
2082 uint32_t value
, dc_ctrl_value
;
2084 struct arc_common
*arc
= target_to_arc(target
);
2086 if (!arc
->has_dcache
|| arc
->dcache_invalidated
)
2089 LOG_DEBUG("Invalidating D$.");
2091 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, &value
));
2092 dc_ctrl_value
= value
;
2093 value
&= ~DC_CTRL_IM
;
2095 /* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
2096 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, value
));
2097 value
= DC_IVDC_INVALIDATE
; /* invalidate D$ */
2098 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_IVDC_REG
, value
));
2100 /* restore DC_CTRL invalidate mode */
2101 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, dc_ctrl_value
));
2103 arc
->dcache_invalidated
= true;
2108 /* This function invalidates l2 cache. */
2109 static int arc_l2cache_invalidate(struct target
*target
)
2111 uint32_t value
, slc_ctrl_value
;
2113 struct arc_common
*arc
= target_to_arc(target
);
2115 if (!arc
->has_l2cache
|| arc
->l2cache_invalidated
)
2118 LOG_DEBUG("Invalidating L2$.");
2120 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, &value
));
2121 slc_ctrl_value
= value
;
2122 value
&= ~L2_CTRL_IM
;
2124 /* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
2125 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, value
));
2126 /* invalidate L2$ */
2127 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_INV
, L2_INV_IV
));
2129 /* Wait until invalidate operation ends */
2131 LOG_DEBUG("Waiting for invalidation end.");
2132 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, &value
));
2133 } while (value
& L2_CTRL_BS
);
2135 /* restore L2_CTRL invalidate mode */
2136 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, slc_ctrl_value
));
2138 arc
->l2cache_invalidated
= true;
2144 int arc_cache_invalidate(struct target
*target
)
2146 CHECK_RETVAL(arc_icache_invalidate(target
));
2147 CHECK_RETVAL(arc_dcache_invalidate(target
));
2148 CHECK_RETVAL(arc_l2cache_invalidate(target
));
2153 /* Flush data cache. This function is cheap to call and return quickly if D$
2154 * already has been flushed since target had been halted. JTAG debugger reads
2155 * values directly from memory, bypassing cache, so if there are unflushed
2156 * lines debugger will read invalid values, which will cause a lot of troubles.
2158 static int arc_dcache_flush(struct target
*target
)
2160 uint32_t value
, dc_ctrl_value
;
2161 bool has_to_set_dc_ctrl_im
;
2163 struct arc_common
*arc
= target_to_arc(target
);
2165 /* Don't waste time if already done. */
2166 if (!arc
->has_dcache
|| arc
->dcache_flushed
)
2169 LOG_DEBUG("Flushing D$.");
2171 /* Store current value of DC_CTRL */
2172 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, &dc_ctrl_value
));
2174 /* Set DC_CTRL invalidate mode to flush (if not already set) */
2175 has_to_set_dc_ctrl_im
= (dc_ctrl_value
& DC_CTRL_IM
) == 0;
2176 if (has_to_set_dc_ctrl_im
) {
2177 value
= dc_ctrl_value
| DC_CTRL_IM
;
2178 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, value
));
2182 value
= DC_IVDC_INVALIDATE
;
2183 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_IVDC_REG
, value
));
2185 /* Restore DC_CTRL invalidate mode (even of flush failed) */
2186 if (has_to_set_dc_ctrl_im
)
2187 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, dc_ctrl_value
));
2189 arc
->dcache_flushed
= true;
2194 /* This function flushes l2cache. */
2195 static int arc_l2cache_flush(struct target
*target
)
2199 struct arc_common
*arc
= target_to_arc(target
);
2201 /* Don't waste time if already done. */
2202 if (!arc
->has_l2cache
|| arc
->l2cache_flushed
)
2205 LOG_DEBUG("Flushing L2$.");
2207 /* Flush L2 cache */
2208 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_FLUSH
, L2_FLUSH_FL
));
2210 /* Wait until flush operation ends */
2212 LOG_DEBUG("Waiting for flushing end.");
2213 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, &value
));
2214 } while (value
& L2_CTRL_BS
);
2216 arc
->l2cache_flushed
= true;
2221 int arc_cache_flush(struct target
*target
)
2223 CHECK_RETVAL(arc_dcache_flush(target
));
2224 CHECK_RETVAL(arc_l2cache_flush(target
));
2230 struct target_type arcv2_target
= {
2235 .arch_state
= arc_arch_state
,
2237 /* TODO That seems like something similar to metaware hostlink, so perhaps
2238 * we can exploit this in the future. */
2239 .target_request_data
= NULL
,
2242 .resume
= arc_resume
,
2245 .assert_reset
= arc_assert_reset
,
2246 .deassert_reset
= arc_deassert_reset
,
2248 /* TODO Implement soft_reset_halt */
2249 .soft_reset_halt
= NULL
,
2251 .get_gdb_reg_list
= arc_get_gdb_reg_list
,
2253 .read_memory
= arc_mem_read
,
2254 .write_memory
= arc_mem_write
,
2255 .checksum_memory
= NULL
,
2256 .blank_check_memory
= NULL
,
2258 .add_breakpoint
= arc_add_breakpoint
,
2259 .add_context_breakpoint
= NULL
,
2260 .add_hybrid_breakpoint
= NULL
,
2261 .remove_breakpoint
= arc_remove_breakpoint
,
2262 .add_watchpoint
= arc_add_watchpoint
,
2263 .remove_watchpoint
= arc_remove_watchpoint
,
2264 .hit_watchpoint
= arc_hit_watchpoint
,
2266 .run_algorithm
= NULL
,
2267 .start_algorithm
= NULL
,
2268 .wait_algorithm
= NULL
,
2270 .commands
= arc_monitor_command_handlers
,
2272 .target_create
= arc_target_create
,
2273 .init_target
= arc_init_target
,
2274 .deinit_target
= arc_deinit_target
,
2275 .examine
= arc_examine
,
2278 .read_phys_memory
= NULL
,
2279 .write_phys_memory
= NULL
,
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