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added at91sam9260.cfg, nslu2.cfg, pxa255.cfg, pxa255_sst.cfg
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "arm11.h"
24 #include "jtag.h"
25 #include "log.h"
26
27 #include <stdlib.h>
28 #include <string.h>
29
30 #if 0
31 #define _DEBUG_INSTRUCTION_EXECUTION_
32 #endif
33
34
35 #if 0
36 #define FNC_INFO DEBUG("-")
37 #else
38 #define FNC_INFO
39 #endif
40
41 #if 1
42 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
43 #else
44 #define FNC_INFO_NOTIMPLEMENTED
45 #endif
46
47 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
48
49
50 int arm11_config_memwrite_burst = 1;
51 int arm11_config_memwrite_error_fatal = 1;
52 u32 arm11_vcr = 0;
53
54
55 #define ARM11_HANDLER(x) \
56 .x = arm11_##x
57
58 target_type_t arm11_target =
59 {
60 .name = "arm11",
61
62 ARM11_HANDLER(poll),
63 ARM11_HANDLER(arch_state),
64
65 ARM11_HANDLER(target_request_data),
66
67 ARM11_HANDLER(halt),
68 ARM11_HANDLER(resume),
69 ARM11_HANDLER(step),
70
71 ARM11_HANDLER(assert_reset),
72 ARM11_HANDLER(deassert_reset),
73 ARM11_HANDLER(soft_reset_halt),
74 ARM11_HANDLER(prepare_reset_halt),
75
76 ARM11_HANDLER(get_gdb_reg_list),
77
78 ARM11_HANDLER(read_memory),
79 ARM11_HANDLER(write_memory),
80
81 ARM11_HANDLER(bulk_write_memory),
82
83 ARM11_HANDLER(checksum_memory),
84
85 ARM11_HANDLER(add_breakpoint),
86 ARM11_HANDLER(remove_breakpoint),
87 ARM11_HANDLER(add_watchpoint),
88 ARM11_HANDLER(remove_watchpoint),
89
90 ARM11_HANDLER(run_algorithm),
91
92 ARM11_HANDLER(register_commands),
93 ARM11_HANDLER(target_command),
94 ARM11_HANDLER(init_target),
95 ARM11_HANDLER(quit),
96 };
97
98 int arm11_regs_arch_type = -1;
99
100
101 enum arm11_regtype
102 {
103 ARM11_REGISTER_CORE,
104 ARM11_REGISTER_CPSR,
105
106 ARM11_REGISTER_FX,
107 ARM11_REGISTER_FPS,
108
109 ARM11_REGISTER_FIQ,
110 ARM11_REGISTER_SVC,
111 ARM11_REGISTER_ABT,
112 ARM11_REGISTER_IRQ,
113 ARM11_REGISTER_UND,
114 ARM11_REGISTER_MON,
115
116 ARM11_REGISTER_SPSR_FIQ,
117 ARM11_REGISTER_SPSR_SVC,
118 ARM11_REGISTER_SPSR_ABT,
119 ARM11_REGISTER_SPSR_IRQ,
120 ARM11_REGISTER_SPSR_UND,
121 ARM11_REGISTER_SPSR_MON,
122
123 /* debug regs */
124 ARM11_REGISTER_DSCR,
125 ARM11_REGISTER_WDTR,
126 ARM11_REGISTER_RDTR,
127 };
128
129
130 typedef struct arm11_reg_defs_s
131 {
132 char * name;
133 u32 num;
134 int gdb_num;
135 enum arm11_regtype type;
136 } arm11_reg_defs_t;
137
138 /* update arm11_regcache_ids when changing this */
139 static const arm11_reg_defs_t arm11_reg_defs[] =
140 {
141 {"r0", 0, 0, ARM11_REGISTER_CORE},
142 {"r1", 1, 1, ARM11_REGISTER_CORE},
143 {"r2", 2, 2, ARM11_REGISTER_CORE},
144 {"r3", 3, 3, ARM11_REGISTER_CORE},
145 {"r4", 4, 4, ARM11_REGISTER_CORE},
146 {"r5", 5, 5, ARM11_REGISTER_CORE},
147 {"r6", 6, 6, ARM11_REGISTER_CORE},
148 {"r7", 7, 7, ARM11_REGISTER_CORE},
149 {"r8", 8, 8, ARM11_REGISTER_CORE},
150 {"r9", 9, 9, ARM11_REGISTER_CORE},
151 {"r10", 10, 10, ARM11_REGISTER_CORE},
152 {"r11", 11, 11, ARM11_REGISTER_CORE},
153 {"r12", 12, 12, ARM11_REGISTER_CORE},
154 {"sp", 13, 13, ARM11_REGISTER_CORE},
155 {"lr", 14, 14, ARM11_REGISTER_CORE},
156 {"pc", 15, 15, ARM11_REGISTER_CORE},
157
158 #if ARM11_REGCACHE_FREGS
159 {"f0", 0, 16, ARM11_REGISTER_FX},
160 {"f1", 1, 17, ARM11_REGISTER_FX},
161 {"f2", 2, 18, ARM11_REGISTER_FX},
162 {"f3", 3, 19, ARM11_REGISTER_FX},
163 {"f4", 4, 20, ARM11_REGISTER_FX},
164 {"f5", 5, 21, ARM11_REGISTER_FX},
165 {"f6", 6, 22, ARM11_REGISTER_FX},
166 {"f7", 7, 23, ARM11_REGISTER_FX},
167 {"fps", 0, 24, ARM11_REGISTER_FPS},
168 #endif
169
170 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
171
172 #if ARM11_REGCACHE_MODEREGS
173 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
174 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
175 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
176 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
177 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
178 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
179 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
180 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
181
182 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
183 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
184 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
185
186 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
187 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
188 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
189
190 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
191 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
192 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
193
194 {"r13_und", 13, -1, ARM11_REGISTER_UND},
195 {"r14_und", 14, -1, ARM11_REGISTER_UND},
196 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
197
198 /* ARM1176 only */
199 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
200 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
201 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
202 #endif
203
204 /* Debug Registers */
205 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
206 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
207 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
208 };
209
210 enum arm11_regcache_ids
211 {
212 ARM11_RC_R0,
213 ARM11_RC_RX = ARM11_RC_R0,
214
215 ARM11_RC_R1,
216 ARM11_RC_R2,
217 ARM11_RC_R3,
218 ARM11_RC_R4,
219 ARM11_RC_R5,
220 ARM11_RC_R6,
221 ARM11_RC_R7,
222 ARM11_RC_R8,
223 ARM11_RC_R9,
224 ARM11_RC_R10,
225 ARM11_RC_R11,
226 ARM11_RC_R12,
227 ARM11_RC_R13,
228 ARM11_RC_SP = ARM11_RC_R13,
229 ARM11_RC_R14,
230 ARM11_RC_LR = ARM11_RC_R14,
231 ARM11_RC_R15,
232 ARM11_RC_PC = ARM11_RC_R15,
233
234 #if ARM11_REGCACHE_FREGS
235 ARM11_RC_F0,
236 ARM11_RC_FX = ARM11_RC_F0,
237 ARM11_RC_F1,
238 ARM11_RC_F2,
239 ARM11_RC_F3,
240 ARM11_RC_F4,
241 ARM11_RC_F5,
242 ARM11_RC_F6,
243 ARM11_RC_F7,
244 ARM11_RC_FPS,
245 #endif
246
247 ARM11_RC_CPSR,
248
249 #if ARM11_REGCACHE_MODEREGS
250 ARM11_RC_R8_FIQ,
251 ARM11_RC_R9_FIQ,
252 ARM11_RC_R10_FIQ,
253 ARM11_RC_R11_FIQ,
254 ARM11_RC_R12_FIQ,
255 ARM11_RC_R13_FIQ,
256 ARM11_RC_R14_FIQ,
257 ARM11_RC_SPSR_FIQ,
258
259 ARM11_RC_R13_SVC,
260 ARM11_RC_R14_SVC,
261 ARM11_RC_SPSR_SVC,
262
263 ARM11_RC_R13_ABT,
264 ARM11_RC_R14_ABT,
265 ARM11_RC_SPSR_ABT,
266
267 ARM11_RC_R13_IRQ,
268 ARM11_RC_R14_IRQ,
269 ARM11_RC_SPSR_IRQ,
270
271 ARM11_RC_R13_UND,
272 ARM11_RC_R14_UND,
273 ARM11_RC_SPSR_UND,
274
275 ARM11_RC_R13_MON,
276 ARM11_RC_R14_MON,
277 ARM11_RC_SPSR_MON,
278 #endif
279
280 ARM11_RC_DSCR,
281 ARM11_RC_WDTR,
282 ARM11_RC_RDTR,
283
284
285 ARM11_RC_MAX,
286 };
287
288 #define ARM11_GDB_REGISTER_COUNT 26
289
290 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
291
292 reg_t arm11_gdb_dummy_fp_reg =
293 {
294 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
295 };
296
297 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
298
299 reg_t arm11_gdb_dummy_fps_reg =
300 {
301 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
302 };
303
304
305
306 /** Check and if necessary take control of the system
307 *
308 * \param arm11 Target state variable.
309 * \param dscr If the current DSCR content is
310 * available a pointer to a word holding the
311 * DSCR can be passed. Otherwise use NULL.
312 */
313 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
314 {
315 FNC_INFO;
316
317 u32 dscr_local_tmp_copy;
318
319 if (!dscr)
320 {
321 dscr = &dscr_local_tmp_copy;
322 *dscr = arm11_read_DSCR(arm11);
323 }
324
325 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
326 {
327 DEBUG("Bringing target into debug mode");
328
329 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
330 arm11_write_DSCR(arm11, *dscr);
331
332 /* add further reset initialization here */
333
334 if (*dscr & ARM11_DSCR_CORE_HALTED)
335 {
336 arm11->target->state = TARGET_HALTED;
337 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
338 }
339 else
340 {
341 arm11->target->state = TARGET_RUNNING;
342 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
343 }
344
345 arm11_sc7_clear_vbw(arm11);
346 }
347 }
348
349
350
351 #define R(x) \
352 (arm11->reg_values[ARM11_RC_##x])
353
354 /** Save processor state.
355 *
356 * This is called when the HALT instruction has succeeded
357 * or on other occasions that stop the processor.
358 *
359 */
360 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
361 {
362 FNC_INFO;
363
364 {size_t i;
365 for(i = 0; i < asizeof(arm11->reg_values); i++)
366 {
367 arm11->reg_list[i].valid = 1;
368 arm11->reg_list[i].dirty = 0;
369 }}
370
371 /* Save DSCR */
372
373 R(DSCR) = arm11_read_DSCR(arm11);
374
375 /* Save wDTR */
376
377 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
378 {
379 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
380
381 arm11_add_IR(arm11, ARM11_INTEST, -1);
382
383 scan_field_t chain5_fields[3];
384
385 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
386 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
387 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
388
389 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
390 }
391 else
392 {
393 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
394 }
395
396
397 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
398 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
399 ARM1136 seems to require this to issue ITR's as well */
400
401 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
402
403 /* this executes JTAG queue: */
404
405 arm11_write_DSCR(arm11, new_dscr);
406
407 /* jtag_execute_queue(); */
408
409
410 /*
411 DEBUG("SAVE DSCR %08x", R(DSCR));
412
413 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
414 DEBUG("SAVE wDTR %08x", R(WDTR));
415 */
416
417
418 /* From the spec:
419 Before executing any instruction in debug state you have to drain the write buffer.
420 This ensures that no imprecise Data Aborts can return at a later point:*/
421
422 /** \todo TODO: Test drain write buffer. */
423
424 #if 0
425 while (1)
426 {
427 /* MRC p14,0,R0,c5,c10,0 */
428 /* arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); */
429
430 /* mcr 15, 0, r0, cr7, cr10, {4} */
431 arm11_run_instr_no_data1(arm11, 0xee070f9a);
432
433 u32 dscr = arm11_read_DSCR(arm11);
434
435 DEBUG("DRAIN, DSCR %08x", dscr);
436
437 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
438 {
439 arm11_run_instr_no_data1(arm11, 0xe320f000);
440
441 dscr = arm11_read_DSCR(arm11);
442
443 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
444
445 break;
446 }
447 }
448 #endif
449
450
451 arm11_run_instr_data_prepare(arm11);
452
453 /* save r0 - r14 */
454
455
456 /** \todo TODO: handle other mode registers */
457
458 {size_t i;
459 for (i = 0; i < 15; i++)
460 {
461 /* MCR p14,0,R?,c0,c5,0 */
462 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
463 }}
464
465
466 /* save rDTR */
467
468 /* check rDTRfull in DSCR */
469
470 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
471 {
472 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
473 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
474 }
475 else
476 {
477 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
478 }
479
480 /* save CPSR */
481
482 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
483 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
484
485 /* save PC */
486
487 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
488 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
489
490 /* adjust PC depending on ARM state */
491
492 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 0;
495 }
496 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 4;
499 }
500 else /* ARM state */
501 {
502 arm11->reg_values[ARM11_RC_PC] -= 8;
503 }
504
505 /* DEBUG("SAVE PC %08x", R(PC)); */
506
507 arm11_run_instr_data_finish(arm11);
508
509 arm11_dump_reg_changes(arm11);
510 }
511
512 void arm11_dump_reg_changes(arm11_common_t * arm11)
513 {
514 {size_t i;
515 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
516 {
517 if (!arm11->reg_list[i].valid)
518 {
519 if (arm11->reg_history[i].valid)
520 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
521 }
522 else
523 {
524 if (arm11->reg_history[i].valid)
525 {
526 if (arm11->reg_history[i].value != arm11->reg_values[i])
527 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
528 }
529 else
530 {
531 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
532 }
533 }
534 }}
535 }
536
537
538 /** Restore processor state
539 *
540 * This is called in preparation for the RESTART function.
541 *
542 */
543 void arm11_leave_debug_state(arm11_common_t * arm11)
544 {
545 FNC_INFO;
546
547 arm11_run_instr_data_prepare(arm11);
548
549 /** \todo TODO: handle other mode registers */
550
551 /* restore R1 - R14 */
552 {size_t i;
553 for (i = 1; i < 15; i++)
554 {
555 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
556 continue;
557
558 /* MRC p14,0,r?,c0,c5,0 */
559 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
560
561 /* DEBUG("RESTORE R%d %08x", i, R(RX + i)); */
562 }}
563
564 arm11_run_instr_data_finish(arm11);
565
566
567 /* spec says clear wDTR and rDTR; we assume they are clear as
568 otherwise our programming would be sloppy */
569
570 {
571 u32 DSCR = arm11_read_DSCR(arm11);
572
573 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
574 {
575 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
576 }
577 }
578
579 arm11_run_instr_data_prepare(arm11);
580
581 /* restore original wDTR */
582
583 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
584 {
585 /* MCR p14,0,R0,c0,c5,0 */
586 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
587 }
588
589 /* restore CPSR */
590
591 /* MSR CPSR,R0*/
592 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
593
594
595 /* restore PC */
596
597 /* MOV PC,R0 */
598 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
599
600
601 /* restore R0 */
602
603 /* MRC p14,0,r0,c0,c5,0 */
604 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
605
606 arm11_run_instr_data_finish(arm11);
607
608
609 /* restore DSCR */
610
611 arm11_write_DSCR(arm11, R(DSCR));
612
613
614 /* restore rDTR */
615
616 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
617 {
618 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
619
620 arm11_add_IR(arm11, ARM11_EXTEST, -1);
621
622 scan_field_t chain5_fields[3];
623
624 u8 Ready = 0; /* ignored */
625 u8 Valid = 0; /* ignored */
626
627 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
628 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
629 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
630
631 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
632 }
633
634 arm11_record_register_history(arm11);
635 }
636
637 void arm11_record_register_history(arm11_common_t * arm11)
638 {
639 {size_t i;
640 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
641 {
642 arm11->reg_history[i].value = arm11->reg_values[i];
643 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
644
645 arm11->reg_list[i].valid = 0;
646 arm11->reg_list[i].dirty = 0;
647 }}
648 }
649
650
651 /* poll current target status */
652 int arm11_poll(struct target_s *target)
653 {
654 FNC_INFO;
655
656 arm11_common_t * arm11 = target->arch_info;
657
658 if (arm11->trst_active)
659 return ERROR_OK;
660
661 u32 dscr = arm11_read_DSCR(arm11);
662
663 DEBUG("DSCR %08x", dscr);
664
665 arm11_check_init(arm11, &dscr);
666
667 if (dscr & ARM11_DSCR_CORE_HALTED)
668 {
669 if (target->state != TARGET_HALTED)
670 {
671 enum target_state old_state = target->state;
672
673 DEBUG("enter TARGET_HALTED");
674 target->state = TARGET_HALTED;
675 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
676 arm11_on_enter_debug_state(arm11);
677
678 target_call_event_callbacks(target,
679 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
680 }
681 }
682 else
683 {
684 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
685 {
686 DEBUG("enter TARGET_RUNNING");
687 target->state = TARGET_RUNNING;
688 target->debug_reason = DBG_REASON_NOTHALTED;
689 }
690 }
691
692 return ERROR_OK;
693 }
694 /* architecture specific status reply */
695 int arm11_arch_state(struct target_s *target)
696 {
697 FNC_INFO_NOTIMPLEMENTED;
698
699 return ERROR_OK;
700 }
701
702
703 /* target request support */
704 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
705 {
706 FNC_INFO_NOTIMPLEMENTED;
707
708 return ERROR_OK;
709 }
710
711
712
713 /* target execution control */
714 int arm11_halt(struct target_s *target)
715 {
716 FNC_INFO;
717
718 arm11_common_t * arm11 = target->arch_info;
719
720 DEBUG("target->state: %s", target_state_strings[target->state]);
721
722 if (target->state == TARGET_HALTED)
723 {
724 WARNING("target was already halted");
725 return ERROR_TARGET_ALREADY_HALTED;
726 }
727
728 if (arm11->trst_active)
729 {
730 arm11->halt_requested = 1;
731 return ERROR_OK;
732 }
733
734 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
735
736 jtag_execute_queue();
737
738 u32 dscr;
739
740 while (1)
741 {
742 dscr = arm11_read_DSCR(arm11);
743
744 if (dscr & ARM11_DSCR_CORE_HALTED)
745 break;
746 }
747
748 arm11_on_enter_debug_state(arm11);
749
750 enum target_state old_state = target->state;
751
752 target->state = TARGET_HALTED;
753 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
754
755 target_call_event_callbacks(target,
756 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
757
758 return ERROR_OK;
759 }
760
761
762 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
763 {
764 FNC_INFO;
765
766 /*
767 DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
768 current, address, handle_breakpoints, debug_execution);
769 */
770
771 arm11_common_t * arm11 = target->arch_info;
772
773 DEBUG("target->state: %s", target_state_strings[target->state]);
774
775 if (target->state != TARGET_HALTED)
776 {
777 WARNING("target was not halted");
778 return ERROR_TARGET_NOT_HALTED;
779 }
780
781 if (!current)
782 R(PC) = address;
783
784 INFO("RESUME PC %08x", R(PC));
785
786 /* clear breakpoints/watchpoints and VCR*/
787 arm11_sc7_clear_vbw(arm11);
788
789 /* Set up breakpoints */
790 if (!debug_execution)
791 {
792 /* check if one matches PC and step over it if necessary */
793
794 breakpoint_t * bp;
795
796 for (bp = target->breakpoints; bp; bp = bp->next)
797 {
798 if (bp->address == R(PC))
799 {
800 DEBUG("must step over %08x", bp->address);
801 arm11_step(target, 1, 0, 0);
802 break;
803 }
804 }
805
806 /* set all breakpoints */
807
808 size_t brp_num = 0;
809
810 for (bp = target->breakpoints; bp; bp = bp->next)
811 {
812 arm11_sc7_action_t brp[2];
813
814 brp[0].write = 1;
815 brp[0].address = ARM11_SC7_BVR0 + brp_num;
816 brp[0].value = bp->address;
817 brp[1].write = 1;
818 brp[1].address = ARM11_SC7_BCR0 + brp_num;
819 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
820
821 arm11_sc7_run(arm11, brp, asizeof(brp));
822
823 DEBUG("Add BP %d at %08x", brp_num, bp->address);
824
825 brp_num++;
826 }
827
828 arm11_sc7_set_vcr(arm11, arm11_vcr);
829 }
830
831
832 arm11_leave_debug_state(arm11);
833
834 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
835
836 jtag_execute_queue();
837
838 while (1)
839 {
840 u32 dscr = arm11_read_DSCR(arm11);
841
842 DEBUG("DSCR %08x", dscr);
843
844 if (dscr & ARM11_DSCR_CORE_RESTARTED)
845 break;
846 }
847
848 if (!debug_execution)
849 {
850 target->state = TARGET_RUNNING;
851 target->debug_reason = DBG_REASON_NOTHALTED;
852 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
853 }
854 else
855 {
856 target->state = TARGET_DEBUG_RUNNING;
857 target->debug_reason = DBG_REASON_NOTHALTED;
858 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
859 }
860
861 return ERROR_OK;
862 }
863
864 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
865 {
866 FNC_INFO;
867
868 DEBUG("target->state: %s", target_state_strings[target->state]);
869
870 if (target->state != TARGET_HALTED)
871 {
872 WARNING("target was not halted");
873 return ERROR_TARGET_NOT_HALTED;
874 }
875
876 arm11_common_t * arm11 = target->arch_info;
877
878 if (!current)
879 R(PC) = address;
880
881 INFO("STEP PC %08x", R(PC));
882
883 /** \todo TODO: Thumb not supported here */
884
885 u32 next_instruction;
886
887 arm11_read_memory_word(arm11, R(PC), &next_instruction);
888
889 /** skip over BKPT */
890 if ((next_instruction & 0xFFF00070) == 0xe1200070)
891 {
892 R(PC) += 4;
893 arm11->reg_list[ARM11_RC_PC].valid = 1;
894 arm11->reg_list[ARM11_RC_PC].dirty = 0;
895 INFO("Skipping BKPT");
896 }
897 /* ignore B to self */
898 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
899 {
900 INFO("Not stepping jump to self");
901 }
902 else
903 {
904 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
905 * with this. */
906
907 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
908 * the VCR might be something worth looking into. */
909
910
911 /* Set up breakpoint for stepping */
912
913 arm11_sc7_action_t brp[2];
914
915 brp[0].write = 1;
916 brp[0].address = ARM11_SC7_BVR0;
917 brp[0].value = R(PC);
918 brp[1].write = 1;
919 brp[1].address = ARM11_SC7_BCR0;
920 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
921
922 arm11_sc7_run(arm11, brp, asizeof(brp));
923
924 /* resume */
925
926 arm11_leave_debug_state(arm11);
927
928 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
929
930 jtag_execute_queue();
931
932 /** \todo TODO: add a timeout */
933
934 /* wait for halt */
935
936 while (1)
937 {
938 u32 dscr = arm11_read_DSCR(arm11);
939
940 DEBUG("DSCR %08x", dscr);
941
942 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
943 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
944 break;
945 }
946
947 /* clear breakpoint */
948 arm11_sc7_clear_vbw(arm11);
949
950 /* save state */
951 arm11_on_enter_debug_state(arm11);
952 }
953
954 /* target->state = TARGET_HALTED; */
955 target->debug_reason = DBG_REASON_SINGLESTEP;
956
957 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
958
959 return ERROR_OK;
960 }
961
962
963 /* target reset control */
964 int arm11_assert_reset(struct target_s *target)
965 {
966 FNC_INFO;
967
968 #if 0
969 /* assert reset lines */
970 /* resets only the DBGTAP, not the ARM */
971
972 jtag_add_reset(1, 0);
973 jtag_add_sleep(5000);
974
975 arm11_common_t * arm11 = target->arch_info;
976 arm11->trst_active = 1;
977 #endif
978
979 return ERROR_OK;
980 }
981
982 int arm11_deassert_reset(struct target_s *target)
983 {
984 FNC_INFO;
985
986 #if 0
987 DEBUG("target->state: %s", target_state_strings[target->state]);
988
989 /* deassert reset lines */
990 jtag_add_reset(0, 0);
991
992 arm11_common_t * arm11 = target->arch_info;
993 arm11->trst_active = false;
994
995 if (arm11->halt_requested)
996 return arm11_halt(target);
997 #endif
998
999 return ERROR_OK;
1000 }
1001
1002 int arm11_soft_reset_halt(struct target_s *target)
1003 {
1004 FNC_INFO_NOTIMPLEMENTED;
1005
1006 return ERROR_OK;
1007 }
1008
1009 int arm11_prepare_reset_halt(struct target_s *target)
1010 {
1011 FNC_INFO_NOTIMPLEMENTED;
1012
1013 return ERROR_OK;
1014 }
1015
1016
1017 /* target register access for gdb */
1018 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1019 {
1020 FNC_INFO;
1021
1022 arm11_common_t * arm11 = target->arch_info;
1023
1024 if (target->state != TARGET_HALTED)
1025 {
1026 return ERROR_TARGET_NOT_HALTED;
1027 }
1028
1029 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1030 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1031
1032 {size_t i;
1033 for (i = 16; i < 24; i++)
1034 {
1035 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1036 }}
1037
1038 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1039
1040
1041 {size_t i;
1042 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1043 {
1044 if (arm11_reg_defs[i].gdb_num == -1)
1045 continue;
1046
1047 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1048 }}
1049
1050 return ERROR_OK;
1051 }
1052
1053
1054 /* target memory access
1055 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1056 * count: number of items of <size>
1057 */
1058 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1059 {
1060 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1061
1062 FNC_INFO;
1063
1064 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1065
1066 arm11_common_t * arm11 = target->arch_info;
1067
1068 arm11_run_instr_data_prepare(arm11);
1069
1070 /* MRC p14,0,r0,c0,c5,0 */
1071 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1072
1073 switch (size)
1074 {
1075 case 1:
1076 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1077 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1078
1079 while (count--)
1080 {
1081 /* ldrb r1, [r0], #1 */
1082 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1083
1084 u32 res;
1085 /* MCR p14,0,R1,c0,c5,0 */
1086 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1087
1088 *buffer++ = res;
1089 }
1090 break;
1091
1092 case 2:
1093 {
1094 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1095
1096 u16 * buf16 = (u16*)buffer;
1097
1098 while (count--)
1099 {
1100 /* ldrh r1, [r0], #2 */
1101 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1102
1103 u32 res;
1104
1105 /* MCR p14,0,R1,c0,c5,0 */
1106 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1107
1108 *buf16++ = res;
1109 }
1110 break;
1111 }
1112
1113 case 4:
1114
1115 /* LDC p14,c5,[R0],#4 */
1116 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1117 break;
1118 }
1119
1120 arm11_run_instr_data_finish(arm11);
1121
1122 return ERROR_OK;
1123 }
1124
1125 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1126 {
1127 FNC_INFO;
1128
1129 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1130
1131 arm11_common_t * arm11 = target->arch_info;
1132
1133 arm11_run_instr_data_prepare(arm11);
1134
1135 /* MRC p14,0,r0,c0,c5,0 */
1136 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1137
1138 switch (size)
1139 {
1140 case 1:
1141 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1142
1143 while (count--)
1144 {
1145 /* MRC p14,0,r1,c0,c5,0 */
1146 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1147
1148 /* strb r1, [r0], #1 */
1149 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1150 }
1151 break;
1152
1153 case 2:
1154 {
1155 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1156
1157 u16 * buf16 = (u16*)buffer;
1158
1159 while (count--)
1160 {
1161 /* MRC p14,0,r1,c0,c5,0 */
1162 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1163
1164 /* strh r1, [r0], #2 */
1165 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1166 }
1167 break;
1168 }
1169
1170 case 4:
1171 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1172
1173 if (!arm11_config_memwrite_burst)
1174 {
1175 /* STC p14,c5,[R0],#4 */
1176 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1177 }
1178 else
1179 {
1180 /* STC p14,c5,[R0],#4 */
1181 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1182 }
1183
1184 break;
1185 }
1186
1187 #if 1
1188 /* r0 verification */
1189 {
1190 u32 r0;
1191
1192 /* MCR p14,0,R0,c0,c5,0 */
1193 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1194
1195 if (address + size * count != r0)
1196 {
1197 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1198
1199 if (arm11_config_memwrite_burst)
1200 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1201
1202 if (arm11_config_memwrite_error_fatal)
1203 exit(-1);
1204 }
1205 }
1206 #endif
1207
1208
1209 arm11_run_instr_data_finish(arm11);
1210
1211
1212
1213
1214 return ERROR_OK;
1215 }
1216
1217
1218 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1219 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1220 {
1221 FNC_INFO;
1222
1223 return arm11_write_memory(target, address, 4, count, buffer);
1224 }
1225
1226
1227 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1228 {
1229 FNC_INFO_NOTIMPLEMENTED;
1230
1231 return ERROR_OK;
1232 }
1233
1234
1235 /* target break-/watchpoint control
1236 * rw: 0 = write, 1 = read, 2 = access
1237 */
1238 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1239 {
1240 FNC_INFO;
1241
1242 arm11_common_t * arm11 = target->arch_info;
1243
1244 #if 0
1245 if (breakpoint->type == BKPT_SOFT)
1246 {
1247 INFO("sw breakpoint requested, but software breakpoints not enabled");
1248 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1249 }
1250 #endif
1251
1252 if (!arm11->free_brps)
1253 {
1254 INFO("no breakpoint unit available for hardware breakpoint");
1255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1256 }
1257
1258 if (breakpoint->length != 4)
1259 {
1260 INFO("only breakpoints of four bytes length supported");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1262 }
1263
1264 arm11->free_brps--;
1265
1266 return ERROR_OK;
1267 }
1268
1269 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1270 {
1271 FNC_INFO;
1272
1273 arm11_common_t * arm11 = target->arch_info;
1274
1275 arm11->free_brps++;
1276
1277 return ERROR_OK;
1278 }
1279
1280 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1281 {
1282 FNC_INFO_NOTIMPLEMENTED;
1283
1284 return ERROR_OK;
1285 }
1286
1287 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1288 {
1289 FNC_INFO_NOTIMPLEMENTED;
1290
1291 return ERROR_OK;
1292 }
1293
1294
1295 /* target algorithm support */
1296 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1297 {
1298 FNC_INFO_NOTIMPLEMENTED;
1299
1300 return ERROR_OK;
1301 }
1302
1303 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1304 {
1305 FNC_INFO;
1306
1307 if (argc < 4)
1308 {
1309 ERROR("'target arm11' 4th argument <jtag chain pos>");
1310 exit(-1);
1311 }
1312
1313 int chain_pos = strtoul(args[3], NULL, 0);
1314
1315 NEW(arm11_common_t, arm11, 1);
1316
1317 arm11->target = target;
1318
1319 /* prepare JTAG information for the new target */
1320 arm11->jtag_info.chain_pos = chain_pos;
1321 arm11->jtag_info.scann_size = 5;
1322
1323 arm_jtag_setup_connection(&arm11->jtag_info);
1324
1325 jtag_device_t *device = jtag_get_device(chain_pos);
1326
1327 if (device->ir_length != 5)
1328 {
1329 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1330 exit(-1);
1331 }
1332
1333 target->arch_info = arm11;
1334
1335 return ERROR_OK;
1336 }
1337
1338 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1339 {
1340 FNC_INFO;
1341
1342 arm11_common_t * arm11 = target->arch_info;
1343
1344 /* check IDCODE */
1345
1346 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1347
1348 scan_field_t idcode_field;
1349
1350 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1351
1352 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1353
1354 /* check DIDR */
1355
1356 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1357
1358 arm11_add_IR(arm11, ARM11_INTEST, -1);
1359
1360 scan_field_t chain0_fields[2];
1361
1362 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1363 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1364
1365 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1366
1367 jtag_execute_queue();
1368
1369
1370 switch (arm11->device_id & 0x0FFFF000)
1371 {
1372 case 0x07B36000: INFO("found ARM1136"); break;
1373 case 0x07B56000: INFO("found ARM1156"); break;
1374 case 0x07B76000: INFO("found ARM1176"); break;
1375 default:
1376 {
1377 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1378 exit(-1);
1379 }
1380 }
1381
1382 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1383
1384 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1385 arm11->debug_version != ARM11_DEBUG_V61)
1386 {
1387 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1388 exit(-1);
1389 }
1390
1391
1392 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1393 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1394
1395 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1396 arm11->free_brps = arm11->brp;
1397 arm11->free_wrps = arm11->wrp;
1398
1399 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1400 arm11->device_id,
1401 arm11->implementor,
1402 arm11->didr);
1403
1404 arm11_build_reg_cache(target);
1405
1406
1407 /* as a side-effect this reads DSCR and thus
1408 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1409 * as suggested by the spec.
1410 */
1411
1412 arm11_check_init(arm11, NULL);
1413
1414 return ERROR_OK;
1415 }
1416
1417 int arm11_quit(void)
1418 {
1419 FNC_INFO_NOTIMPLEMENTED;
1420
1421 return ERROR_OK;
1422 }
1423
1424 /** Load a register that is marked !valid in the register cache */
1425 int arm11_get_reg(reg_t *reg)
1426 {
1427 FNC_INFO;
1428
1429 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1430
1431 if (target->state != TARGET_HALTED)
1432 {
1433 return ERROR_TARGET_NOT_HALTED;
1434 }
1435
1436 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1437
1438 #if 0
1439 arm11_common_t *arm11 = target->arch_info;
1440 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1441 #endif
1442
1443 return ERROR_OK;
1444 }
1445
1446 /** Change a value in the register cache */
1447 int arm11_set_reg(reg_t *reg, u8 *buf)
1448 {
1449 FNC_INFO;
1450
1451 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1452 arm11_common_t *arm11 = target->arch_info;
1453 /* const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; */
1454
1455 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1456 reg->valid = 1;
1457 reg->dirty = 1;
1458
1459 return ERROR_OK;
1460 }
1461
1462
1463 void arm11_build_reg_cache(target_t *target)
1464 {
1465 arm11_common_t *arm11 = target->arch_info;
1466
1467 NEW(reg_cache_t, cache, 1);
1468 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1469 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1470
1471 if (arm11_regs_arch_type == -1)
1472 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1473
1474 arm11->reg_list = reg_list;
1475
1476 /* Build the process context cache */
1477 cache->name = "arm11 registers";
1478 cache->next = NULL;
1479 cache->reg_list = reg_list;
1480 cache->num_regs = ARM11_REGCACHE_COUNT;
1481
1482 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1483 (*cache_p) = cache;
1484
1485 /* armv7m->core_cache = cache; */
1486 /* armv7m->process_context = cache; */
1487
1488 size_t i;
1489
1490 /* Not very elegant assertion */
1491 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1492 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1493 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1494 {
1495 ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1496 exit(-1);
1497 }
1498
1499 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1500 {
1501 reg_t * r = reg_list + i;
1502 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1503 arm11_reg_state_t * rs = arm11_reg_states + i;
1504
1505 r->name = rd->name;
1506 r->size = 32;
1507 r->value = (u8 *)(arm11->reg_values + i);
1508 r->dirty = 0;
1509 r->valid = 0;
1510 r->bitfield_desc = NULL;
1511 r->num_bitfields = 0;
1512 r->arch_type = arm11_regs_arch_type;
1513 r->arch_info = rs;
1514
1515 rs->def_index = i;
1516 rs->target = target;
1517 }
1518 }
1519
1520
1521
1522 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, int * var, char * name)
1523 {
1524 if (argc == 0)
1525 {
1526 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1527 return ERROR_OK;
1528 }
1529
1530 if (argc != 1)
1531 return ERROR_COMMAND_SYNTAX_ERROR;
1532
1533 switch (args[0][0])
1534 {
1535 case '0': /* 0 */
1536 case 'f': /* false */
1537 case 'F':
1538 case 'd': /* disable */
1539 case 'D':
1540 *var = 0;
1541 break;
1542
1543 case '1': /* 1 */
1544 case 't': /* true */
1545 case 'T':
1546 case 'e': /* enable */
1547 case 'E':
1548 *var = 1;
1549 break;
1550 }
1551
1552 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1553
1554 return ERROR_OK;
1555 }
1556
1557
1558 #define BOOL_WRAPPER(name, print_name) \
1559 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1560 { \
1561 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1562 }
1563
1564 #define RC_TOP(name, descr, more) \
1565 { \
1566 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1567 command_t * top_cmd = new_cmd; \
1568 more \
1569 }
1570
1571 #define RC_FINAL(name, descr, handler) \
1572 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1573
1574 #define RC_FINAL_BOOL(name, descr, var) \
1575 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1576
1577
1578 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1579 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1580
1581
1582 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1583 {
1584 if (argc == 1)
1585 {
1586 arm11_vcr = strtoul(args[0], NULL, 0);
1587 }
1588 else if (argc != 0)
1589 {
1590 return ERROR_COMMAND_SYNTAX_ERROR;
1591 }
1592
1593 INFO("VCR 0x%08X", arm11_vcr);
1594 return ERROR_OK;
1595 }
1596
1597
1598 int arm11_register_commands(struct command_context_s *cmd_ctx)
1599 {
1600 FNC_INFO;
1601
1602 command_t * top_cmd = NULL;
1603
1604 RC_TOP( "arm11", "arm11 specific commands",
1605
1606 RC_TOP( "memwrite", "Control memory write transfer mode",
1607
1608 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1609 memwrite_burst)
1610
1611 RC_FINAL_BOOL( "error_fatal",
1612 "Terminate program if transfer error was found (default: enabled)",
1613 memwrite_error_fatal)
1614 )
1615
1616 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1617 arm11_handle_vcr)
1618 )
1619
1620 return ERROR_OK;
1621 }
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