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[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "time_support.h"
33 #include "target_type.h"
34
35
36 #if 0
37 #define _DEBUG_INSTRUCTION_EXECUTION_
38 #endif
39
40 #if 0
41 #define FNC_INFO LOG_DEBUG("-")
42 #else
43 #define FNC_INFO
44 #endif
45
46 #if 1
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #else
49 #define FNC_INFO_NOTIMPLEMENTED
50 #endif
51
52 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
53
54 bool arm11_config_memwrite_burst = true;
55 bool arm11_config_memwrite_error_fatal = true;
56 uint32_t arm11_vcr = 0;
57 bool arm11_config_step_irq_enable = false;
58 bool arm11_config_hardware_step = false;
59
60 #define ARM11_HANDLER(x) \
61 .x = arm11_##x
62
63 target_type_t arm11_target =
64 {
65 .name = "arm11",
66
67 ARM11_HANDLER(poll),
68 ARM11_HANDLER(arch_state),
69
70 ARM11_HANDLER(target_request_data),
71
72 ARM11_HANDLER(halt),
73 ARM11_HANDLER(resume),
74 ARM11_HANDLER(step),
75
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
79
80 ARM11_HANDLER(get_gdb_reg_list),
81
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
84
85 ARM11_HANDLER(bulk_write_memory),
86
87 ARM11_HANDLER(checksum_memory),
88
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
93
94 ARM11_HANDLER(run_algorithm),
95
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
100 ARM11_HANDLER(quit),
101 };
102
103 int arm11_regs_arch_type = -1;
104
105
106 enum arm11_regtype
107 {
108 ARM11_REGISTER_CORE,
109 ARM11_REGISTER_CPSR,
110
111 ARM11_REGISTER_FX,
112 ARM11_REGISTER_FPS,
113
114 ARM11_REGISTER_FIQ,
115 ARM11_REGISTER_SVC,
116 ARM11_REGISTER_ABT,
117 ARM11_REGISTER_IRQ,
118 ARM11_REGISTER_UND,
119 ARM11_REGISTER_MON,
120
121 ARM11_REGISTER_SPSR_FIQ,
122 ARM11_REGISTER_SPSR_SVC,
123 ARM11_REGISTER_SPSR_ABT,
124 ARM11_REGISTER_SPSR_IRQ,
125 ARM11_REGISTER_SPSR_UND,
126 ARM11_REGISTER_SPSR_MON,
127
128 /* debug regs */
129 ARM11_REGISTER_DSCR,
130 ARM11_REGISTER_WDTR,
131 ARM11_REGISTER_RDTR,
132 };
133
134
135 typedef struct arm11_reg_defs_s
136 {
137 char * name;
138 uint32_t num;
139 int gdb_num;
140 enum arm11_regtype type;
141 } arm11_reg_defs_t;
142
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs[] =
145 {
146 {"r0", 0, 0, ARM11_REGISTER_CORE},
147 {"r1", 1, 1, ARM11_REGISTER_CORE},
148 {"r2", 2, 2, ARM11_REGISTER_CORE},
149 {"r3", 3, 3, ARM11_REGISTER_CORE},
150 {"r4", 4, 4, ARM11_REGISTER_CORE},
151 {"r5", 5, 5, ARM11_REGISTER_CORE},
152 {"r6", 6, 6, ARM11_REGISTER_CORE},
153 {"r7", 7, 7, ARM11_REGISTER_CORE},
154 {"r8", 8, 8, ARM11_REGISTER_CORE},
155 {"r9", 9, 9, ARM11_REGISTER_CORE},
156 {"r10", 10, 10, ARM11_REGISTER_CORE},
157 {"r11", 11, 11, ARM11_REGISTER_CORE},
158 {"r12", 12, 12, ARM11_REGISTER_CORE},
159 {"sp", 13, 13, ARM11_REGISTER_CORE},
160 {"lr", 14, 14, ARM11_REGISTER_CORE},
161 {"pc", 15, 15, ARM11_REGISTER_CORE},
162
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX},
165 {"f1", 1, 17, ARM11_REGISTER_FX},
166 {"f2", 2, 18, ARM11_REGISTER_FX},
167 {"f3", 3, 19, ARM11_REGISTER_FX},
168 {"f4", 4, 20, ARM11_REGISTER_FX},
169 {"f5", 5, 21, ARM11_REGISTER_FX},
170 {"f6", 6, 22, ARM11_REGISTER_FX},
171 {"f7", 7, 23, ARM11_REGISTER_FX},
172 {"fps", 0, 24, ARM11_REGISTER_FPS},
173 #endif
174
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
176
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
186
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
190
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
194
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
198
199 {"r13_und", 13, -1, ARM11_REGISTER_UND},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
202
203 /* ARM1176 only */
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
207 #endif
208
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
213 };
214
215 enum arm11_regcache_ids
216 {
217 ARM11_RC_R0,
218 ARM11_RC_RX = ARM11_RC_R0,
219
220 ARM11_RC_R1,
221 ARM11_RC_R2,
222 ARM11_RC_R3,
223 ARM11_RC_R4,
224 ARM11_RC_R5,
225 ARM11_RC_R6,
226 ARM11_RC_R7,
227 ARM11_RC_R8,
228 ARM11_RC_R9,
229 ARM11_RC_R10,
230 ARM11_RC_R11,
231 ARM11_RC_R12,
232 ARM11_RC_R13,
233 ARM11_RC_SP = ARM11_RC_R13,
234 ARM11_RC_R14,
235 ARM11_RC_LR = ARM11_RC_R14,
236 ARM11_RC_R15,
237 ARM11_RC_PC = ARM11_RC_R15,
238
239 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_F0,
241 ARM11_RC_FX = ARM11_RC_F0,
242 ARM11_RC_F1,
243 ARM11_RC_F2,
244 ARM11_RC_F3,
245 ARM11_RC_F4,
246 ARM11_RC_F5,
247 ARM11_RC_F6,
248 ARM11_RC_F7,
249 ARM11_RC_FPS,
250 #endif
251
252 ARM11_RC_CPSR,
253
254 #if ARM11_REGCACHE_MODEREGS
255 ARM11_RC_R8_FIQ,
256 ARM11_RC_R9_FIQ,
257 ARM11_RC_R10_FIQ,
258 ARM11_RC_R11_FIQ,
259 ARM11_RC_R12_FIQ,
260 ARM11_RC_R13_FIQ,
261 ARM11_RC_R14_FIQ,
262 ARM11_RC_SPSR_FIQ,
263
264 ARM11_RC_R13_SVC,
265 ARM11_RC_R14_SVC,
266 ARM11_RC_SPSR_SVC,
267
268 ARM11_RC_R13_ABT,
269 ARM11_RC_R14_ABT,
270 ARM11_RC_SPSR_ABT,
271
272 ARM11_RC_R13_IRQ,
273 ARM11_RC_R14_IRQ,
274 ARM11_RC_SPSR_IRQ,
275
276 ARM11_RC_R13_UND,
277 ARM11_RC_R14_UND,
278 ARM11_RC_SPSR_UND,
279
280 ARM11_RC_R13_MON,
281 ARM11_RC_R14_MON,
282 ARM11_RC_SPSR_MON,
283 #endif
284
285 ARM11_RC_DSCR,
286 ARM11_RC_WDTR,
287 ARM11_RC_RDTR,
288
289 ARM11_RC_MAX,
290 };
291
292 #define ARM11_GDB_REGISTER_COUNT 26
293
294 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295
296 reg_t arm11_gdb_dummy_fp_reg =
297 {
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
299 };
300
301 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
302
303 reg_t arm11_gdb_dummy_fps_reg =
304 {
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 };
307
308
309
310 /** Check and if necessary take control of the system
311 *
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
316 */
317 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
318 {
319 FNC_INFO;
320
321 uint32_t dscr_local_tmp_copy;
322
323 if (!dscr)
324 {
325 dscr = &dscr_local_tmp_copy;
326
327 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
328 }
329
330 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
331 {
332 LOG_DEBUG("Bringing target into debug mode");
333
334 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
335 arm11_write_DSCR(arm11, *dscr);
336
337 /* add further reset initialization here */
338
339 arm11->simulate_reset_on_next_halt = true;
340
341 if (*dscr & ARM11_DSCR_CORE_HALTED)
342 {
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called.
345 * As a result we don't read the actual register states from
346 * the target.
347 */
348
349 arm11->target->state = TARGET_HALTED;
350 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
351 }
352 else
353 {
354 arm11->target->state = TARGET_RUNNING;
355 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
356 }
357
358 arm11_sc7_clear_vbw(arm11);
359 }
360
361 return ERROR_OK;
362 }
363
364
365
366 #define R(x) \
367 (arm11->reg_values[ARM11_RC_##x])
368
369 /** Save processor state.
370 *
371 * This is called when the HALT instruction has succeeded
372 * or on other occasions that stop the processor.
373 *
374 */
375 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
376 {
377 int retval;
378 FNC_INFO;
379
380 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
381 {
382 arm11->reg_list[i].valid = 1;
383 arm11->reg_list[i].dirty = 0;
384 }
385
386 /* Save DSCR */
387 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
388
389 /* Save wDTR */
390
391 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
392 {
393 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
394
395 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
396
397 scan_field_t chain5_fields[3];
398
399 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
400 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
401 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
402
403 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
404 }
405 else
406 {
407 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
408 }
409
410
411 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
412 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
413 ARM1136 seems to require this to issue ITR's as well */
414
415 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
416
417 /* this executes JTAG queue: */
418
419 arm11_write_DSCR(arm11, new_dscr);
420
421
422 /* From the spec:
423 Before executing any instruction in debug state you have to drain the write buffer.
424 This ensures that no imprecise Data Aborts can return at a later point:*/
425
426 /** \todo TODO: Test drain write buffer. */
427
428 #if 0
429 while (1)
430 {
431 /* MRC p14,0,R0,c5,c10,0 */
432 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
433
434 /* mcr 15, 0, r0, cr7, cr10, {4} */
435 arm11_run_instr_no_data1(arm11, 0xee070f9a);
436
437 uint32_t dscr = arm11_read_DSCR(arm11);
438
439 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
440
441 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
442 {
443 arm11_run_instr_no_data1(arm11, 0xe320f000);
444
445 dscr = arm11_read_DSCR(arm11);
446
447 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
448
449 break;
450 }
451 }
452 #endif
453
454 retval = arm11_run_instr_data_prepare(arm11);
455 if (retval != ERROR_OK)
456 return retval;
457
458 /* save r0 - r14 */
459
460 /** \todo TODO: handle other mode registers */
461
462 for (size_t i = 0; i < 15; i++)
463 {
464 /* MCR p14,0,R?,c0,c5,0 */
465 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
466 if (retval != ERROR_OK)
467 return retval;
468 }
469
470 /* save rDTR */
471
472 /* check rDTRfull in DSCR */
473
474 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
475 {
476 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
477 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
478 if (retval != ERROR_OK)
479 return retval;
480 }
481 else
482 {
483 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
484 }
485
486 /* save CPSR */
487
488 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
489 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
490 if (retval != ERROR_OK)
491 return retval;
492
493 /* save PC */
494
495 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
496 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
497 if (retval != ERROR_OK)
498 return retval;
499
500 /* adjust PC depending on ARM state */
501
502 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
503 {
504 arm11->reg_values[ARM11_RC_PC] -= 0;
505 }
506 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
507 {
508 arm11->reg_values[ARM11_RC_PC] -= 4;
509 }
510 else /* ARM state */
511 {
512 arm11->reg_values[ARM11_RC_PC] -= 8;
513 }
514
515 if (arm11->simulate_reset_on_next_halt)
516 {
517 arm11->simulate_reset_on_next_halt = false;
518
519 LOG_DEBUG("Reset c1 Control Register");
520
521 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
522
523 /* MCR p15,0,R0,c1,c0,0 */
524 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
525 if (retval != ERROR_OK)
526 return retval;
527
528 }
529
530 retval = arm11_run_instr_data_finish(arm11);
531 if (retval != ERROR_OK)
532 return retval;
533
534 arm11_dump_reg_changes(arm11);
535
536 return ERROR_OK;
537 }
538
539 void arm11_dump_reg_changes(arm11_common_t * arm11)
540 {
541
542 if (!(debug_level >= LOG_LVL_DEBUG))
543 {
544 return;
545 }
546
547 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
548 {
549 if (!arm11->reg_list[i].valid)
550 {
551 if (arm11->reg_history[i].valid)
552 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
553 }
554 else
555 {
556 if (arm11->reg_history[i].valid)
557 {
558 if (arm11->reg_history[i].value != arm11->reg_values[i])
559 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
560 }
561 else
562 {
563 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
564 }
565 }
566 }
567 }
568
569 /** Restore processor state
570 *
571 * This is called in preparation for the RESTART function.
572 *
573 */
574 int arm11_leave_debug_state(arm11_common_t * arm11)
575 {
576 FNC_INFO;
577 int retval;
578
579 retval = arm11_run_instr_data_prepare(arm11);
580 if (retval != ERROR_OK)
581 return retval;
582
583 /** \todo TODO: handle other mode registers */
584
585 /* restore R1 - R14 */
586
587 for (size_t i = 1; i < 15; i++)
588 {
589 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
590 continue;
591
592 /* MRC p14,0,r?,c0,c5,0 */
593 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
594
595 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
596 }
597
598 retval = arm11_run_instr_data_finish(arm11);
599 if (retval != ERROR_OK)
600 return retval;
601
602 /* spec says clear wDTR and rDTR; we assume they are clear as
603 otherwise our programming would be sloppy */
604 {
605 uint32_t DSCR;
606
607 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
608
609 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
610 {
611 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
612 return ERROR_FAIL;
613 }
614 }
615
616 retval = arm11_run_instr_data_prepare(arm11);
617 if (retval != ERROR_OK)
618 return retval;
619
620 /* restore original wDTR */
621
622 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
623 {
624 /* MCR p14,0,R0,c0,c5,0 */
625 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
626 if (retval != ERROR_OK)
627 return retval;
628 }
629
630 /* restore CPSR */
631
632 /* MSR CPSR,R0*/
633 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
634 if (retval != ERROR_OK)
635 return retval;
636
637
638 /* restore PC */
639
640 /* MOV PC,R0 */
641 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
642 if (retval != ERROR_OK)
643 return retval;
644
645
646 /* restore R0 */
647
648 /* MRC p14,0,r0,c0,c5,0 */
649 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
650
651 retval = arm11_run_instr_data_finish(arm11);
652 if (retval != ERROR_OK)
653 return retval;
654
655 /* restore DSCR */
656
657 arm11_write_DSCR(arm11, R(DSCR));
658
659 /* restore rDTR */
660
661 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
662 {
663 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
664
665 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
666
667 scan_field_t chain5_fields[3];
668
669 uint8_t Ready = 0; /* ignored */
670 uint8_t Valid = 0; /* ignored */
671
672 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
673 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
674 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
675
676 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
677 }
678
679 arm11_record_register_history(arm11);
680
681 return ERROR_OK;
682 }
683
684 void arm11_record_register_history(arm11_common_t * arm11)
685 {
686 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
687 {
688 arm11->reg_history[i].value = arm11->reg_values[i];
689 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
690
691 arm11->reg_list[i].valid = 0;
692 arm11->reg_list[i].dirty = 0;
693 }
694 }
695
696
697 /* poll current target status */
698 int arm11_poll(struct target_s *target)
699 {
700 FNC_INFO;
701 int retval;
702
703 arm11_common_t * arm11 = target->arch_info;
704
705 if (arm11->trst_active)
706 return ERROR_OK;
707
708 uint32_t dscr;
709
710 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
711
712 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
713
714 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
715
716 if (dscr & ARM11_DSCR_CORE_HALTED)
717 {
718 if (target->state != TARGET_HALTED)
719 {
720 enum target_state old_state = target->state;
721
722 LOG_DEBUG("enter TARGET_HALTED");
723 target->state = TARGET_HALTED;
724 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
725 retval = arm11_on_enter_debug_state(arm11);
726 if (retval != ERROR_OK)
727 return retval;
728
729 target_call_event_callbacks(target,
730 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
731 }
732 }
733 else
734 {
735 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
736 {
737 LOG_DEBUG("enter TARGET_RUNNING");
738 target->state = TARGET_RUNNING;
739 target->debug_reason = DBG_REASON_NOTHALTED;
740 }
741 }
742
743 return ERROR_OK;
744 }
745 /* architecture specific status reply */
746 int arm11_arch_state(struct target_s *target)
747 {
748 arm11_common_t * arm11 = target->arch_info;
749
750 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
751 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
752 R(CPSR),
753 R(PC));
754
755 return ERROR_OK;
756 }
757
758 /* target request support */
759 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
760 {
761 FNC_INFO_NOTIMPLEMENTED;
762
763 return ERROR_OK;
764 }
765
766 /* target execution control */
767 int arm11_halt(struct target_s *target)
768 {
769 FNC_INFO;
770
771 arm11_common_t * arm11 = target->arch_info;
772
773 LOG_DEBUG("target->state: %s",
774 target_state_name(target));
775
776 if (target->state == TARGET_UNKNOWN)
777 {
778 arm11->simulate_reset_on_next_halt = true;
779 }
780
781 if (target->state == TARGET_HALTED)
782 {
783 LOG_DEBUG("target was already halted");
784 return ERROR_OK;
785 }
786
787 if (arm11->trst_active)
788 {
789 arm11->halt_requested = true;
790 return ERROR_OK;
791 }
792
793 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
794
795 CHECK_RETVAL(jtag_execute_queue());
796
797 uint32_t dscr;
798
799 int i = 0;
800 while (1)
801 {
802 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
803
804 if (dscr & ARM11_DSCR_CORE_HALTED)
805 break;
806
807
808 long long then = 0;
809 if (i == 1000)
810 {
811 then = timeval_ms();
812 }
813 if (i >= 1000)
814 {
815 if ((timeval_ms()-then) > 1000)
816 {
817 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
818 return ERROR_FAIL;
819 }
820 }
821 i++;
822 }
823
824 arm11_on_enter_debug_state(arm11);
825
826 enum target_state old_state = target->state;
827
828 target->state = TARGET_HALTED;
829 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
830
831 CHECK_RETVAL(
832 target_call_event_callbacks(target,
833 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
834
835 return ERROR_OK;
836 }
837
838 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
839 {
840 FNC_INFO;
841
842 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
843 // current, address, handle_breakpoints, debug_execution);
844
845 arm11_common_t * arm11 = target->arch_info;
846
847 LOG_DEBUG("target->state: %s",
848 target_state_name(target));
849
850
851 if (target->state != TARGET_HALTED)
852 {
853 LOG_ERROR("Target not halted");
854 return ERROR_TARGET_NOT_HALTED;
855 }
856
857 if (!current)
858 R(PC) = address;
859
860 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
861
862 /* clear breakpoints/watchpoints and VCR*/
863 arm11_sc7_clear_vbw(arm11);
864
865 /* Set up breakpoints */
866 if (!debug_execution)
867 {
868 /* check if one matches PC and step over it if necessary */
869
870 breakpoint_t * bp;
871
872 for (bp = target->breakpoints; bp; bp = bp->next)
873 {
874 if (bp->address == R(PC))
875 {
876 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
877 arm11_step(target, 1, 0, 0);
878 break;
879 }
880 }
881
882 /* set all breakpoints */
883
884 size_t brp_num = 0;
885
886 for (bp = target->breakpoints; bp; bp = bp->next)
887 {
888 arm11_sc7_action_t brp[2];
889
890 brp[0].write = 1;
891 brp[0].address = ARM11_SC7_BVR0 + brp_num;
892 brp[0].value = bp->address;
893 brp[1].write = 1;
894 brp[1].address = ARM11_SC7_BCR0 + brp_num;
895 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
896
897 arm11_sc7_run(arm11, brp, asizeof(brp));
898
899 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
900
901 brp_num++;
902 }
903
904 arm11_sc7_set_vcr(arm11, arm11_vcr);
905 }
906
907 arm11_leave_debug_state(arm11);
908
909 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
910
911 CHECK_RETVAL(jtag_execute_queue());
912
913 int i = 0;
914 while (1)
915 {
916 uint32_t dscr;
917
918 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
919
920 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
921
922 if (dscr & ARM11_DSCR_CORE_RESTARTED)
923 break;
924
925
926 long long then = 0;
927 if (i == 1000)
928 {
929 then = timeval_ms();
930 }
931 if (i >= 1000)
932 {
933 if ((timeval_ms()-then) > 1000)
934 {
935 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
936 return ERROR_FAIL;
937 }
938 }
939 i++;
940 }
941
942 if (!debug_execution)
943 {
944 target->state = TARGET_RUNNING;
945 target->debug_reason = DBG_REASON_NOTHALTED;
946
947 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
948 }
949 else
950 {
951 target->state = TARGET_DEBUG_RUNNING;
952 target->debug_reason = DBG_REASON_NOTHALTED;
953
954 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
955 }
956
957 return ERROR_OK;
958 }
959
960
961 static int armv4_5_to_arm11(int reg)
962 {
963 if (reg < 16)
964 return reg;
965 switch (reg)
966 {
967 case ARMV4_5_CPSR:
968 return ARM11_RC_CPSR;
969 case 16:
970 /* FIX!!! handle thumb better! */
971 return ARM11_RC_CPSR;
972 default:
973 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
974 exit(-1);
975 }
976 }
977
978
979 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
980 {
981 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
982
983 reg=armv4_5_to_arm11(reg);
984
985 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
986 }
987
988 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
989 {
990 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
991
992 reg=armv4_5_to_arm11(reg);
993
994 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
995 }
996
997 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
998 {
999 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1000
1001 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
1002 }
1003
1004 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
1005 {
1006 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1007
1008 /* FIX!!!! we should implement thumb for arm11 */
1009 return ARMV4_5_STATE_ARM;
1010 }
1011
1012 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
1013 {
1014 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1015
1016 /* FIX!!!! we should implement thumb for arm11 */
1017 LOG_ERROR("Not implemetned!");
1018 }
1019
1020
1021 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1022 {
1023 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1024
1025 /* FIX!!!! we should implement something that returns the current mode here!!! */
1026 return ARMV4_5_MODE_USR;
1027 }
1028
1029 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1030 {
1031 struct arm_sim_interface sim;
1032
1033 sim.user_data=target->arch_info;
1034 sim.get_reg=&arm11_sim_get_reg;
1035 sim.set_reg=&arm11_sim_set_reg;
1036 sim.get_reg_mode=&arm11_sim_get_reg;
1037 sim.set_reg_mode=&arm11_sim_set_reg;
1038 sim.get_cpsr=&arm11_sim_get_cpsr;
1039 sim.get_mode=&arm11_sim_get_mode;
1040 sim.get_state=&arm11_sim_get_state;
1041 sim.set_state=&arm11_sim_set_state;
1042
1043 return arm_simulate_step_core(target, dry_run_pc, &sim);
1044
1045 }
1046
1047 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1048 {
1049 FNC_INFO;
1050
1051 LOG_DEBUG("target->state: %s",
1052 target_state_name(target));
1053
1054 if (target->state != TARGET_HALTED)
1055 {
1056 LOG_WARNING("target was not halted");
1057 return ERROR_TARGET_NOT_HALTED;
1058 }
1059
1060 arm11_common_t * arm11 = target->arch_info;
1061
1062 if (!current)
1063 R(PC) = address;
1064
1065 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1066
1067
1068 /** \todo TODO: Thumb not supported here */
1069
1070 uint32_t next_instruction;
1071
1072 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1073
1074 /* skip over BKPT */
1075 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1076 {
1077 R(PC) += 4;
1078 arm11->reg_list[ARM11_RC_PC].valid = 1;
1079 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1080 LOG_DEBUG("Skipping BKPT");
1081 }
1082 /* skip over Wait for interrupt / Standby */
1083 /* mcr 15, 0, r?, cr7, cr0, {4} */
1084 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1085 {
1086 R(PC) += 4;
1087 arm11->reg_list[ARM11_RC_PC].valid = 1;
1088 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1089 LOG_DEBUG("Skipping WFI");
1090 }
1091 /* ignore B to self */
1092 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1093 {
1094 LOG_DEBUG("Not stepping jump to self");
1095 }
1096 else
1097 {
1098 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1099 * with this. */
1100
1101 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1102 * the VCR might be something worth looking into. */
1103
1104
1105 /* Set up breakpoint for stepping */
1106
1107 arm11_sc7_action_t brp[2];
1108
1109 brp[0].write = 1;
1110 brp[0].address = ARM11_SC7_BVR0;
1111 brp[1].write = 1;
1112 brp[1].address = ARM11_SC7_BCR0;
1113
1114 if (arm11_config_hardware_step)
1115 {
1116 /* hardware single stepping be used if possible or is it better to
1117 * always use the same code path? Hardware single stepping is not supported
1118 * on all hardware
1119 */
1120 brp[0].value = R(PC);
1121 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1122 } else
1123 {
1124 /* sets a breakpoint on the next PC(calculated by simulation),
1125 */
1126 uint32_t next_pc;
1127 int retval;
1128 retval = arm11_simulate_step(target, &next_pc);
1129 if (retval != ERROR_OK)
1130 return retval;
1131
1132 brp[0].value = next_pc;
1133 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1134 }
1135
1136 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1137
1138 /* resume */
1139
1140
1141 if (arm11_config_step_irq_enable)
1142 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1143 else
1144 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1145
1146
1147 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1148
1149 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1150
1151 CHECK_RETVAL(jtag_execute_queue());
1152
1153 /* wait for halt */
1154 int i = 0;
1155 while (1)
1156 {
1157 uint32_t dscr;
1158
1159 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1160
1161 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1162
1163 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1164 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1165 break;
1166
1167 long long then = 0;
1168 if (i == 1000)
1169 {
1170 then = timeval_ms();
1171 }
1172 if (i >= 1000)
1173 {
1174 if ((timeval_ms()-then) > 1000)
1175 {
1176 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1177 return ERROR_FAIL;
1178 }
1179 }
1180 i++;
1181 }
1182
1183 /* clear breakpoint */
1184 arm11_sc7_clear_vbw(arm11);
1185
1186 /* save state */
1187 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1188
1189 /* restore default state */
1190 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1191
1192 }
1193
1194 // target->state = TARGET_HALTED;
1195 target->debug_reason = DBG_REASON_SINGLESTEP;
1196
1197 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1198
1199 return ERROR_OK;
1200 }
1201
1202 /* target reset control */
1203 int arm11_assert_reset(struct target_s *target)
1204 {
1205 FNC_INFO;
1206
1207 #if 0
1208 /* assert reset lines */
1209 /* resets only the DBGTAP, not the ARM */
1210
1211 jtag_add_reset(1, 0);
1212 jtag_add_sleep(5000);
1213
1214 arm11_common_t * arm11 = target->arch_info;
1215 arm11->trst_active = true;
1216 #endif
1217
1218 if (target->reset_halt)
1219 {
1220 CHECK_RETVAL(target_halt(target));
1221 }
1222
1223 return ERROR_OK;
1224 }
1225
1226 int arm11_deassert_reset(struct target_s *target)
1227 {
1228 FNC_INFO;
1229
1230 #if 0
1231 LOG_DEBUG("target->state: %s",
1232 target_state_name(target));
1233
1234
1235 /* deassert reset lines */
1236 jtag_add_reset(0, 0);
1237
1238 arm11_common_t * arm11 = target->arch_info;
1239 arm11->trst_active = false;
1240
1241 if (arm11->halt_requested)
1242 return arm11_halt(target);
1243 #endif
1244
1245 return ERROR_OK;
1246 }
1247
1248 int arm11_soft_reset_halt(struct target_s *target)
1249 {
1250 FNC_INFO_NOTIMPLEMENTED;
1251
1252 return ERROR_OK;
1253 }
1254
1255 /* target register access for gdb */
1256 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1257 {
1258 FNC_INFO;
1259
1260 arm11_common_t * arm11 = target->arch_info;
1261
1262 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1263 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1264
1265 for (size_t i = 16; i < 24; i++)
1266 {
1267 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1268 }
1269
1270 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1271
1272 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1273 {
1274 if (arm11_reg_defs[i].gdb_num == -1)
1275 continue;
1276
1277 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1278 }
1279
1280 return ERROR_OK;
1281 }
1282
1283 /* target memory access
1284 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1285 * count: number of items of <size>
1286 *
1287 * arm11_config_memrw_no_increment - in the future we may want to be able
1288 * to read/write a range of data to a "port". a "port" is an action on
1289 * read memory address for some peripheral.
1290 */
1291 int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1292 bool arm11_config_memrw_no_increment)
1293 {
1294 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1295 int retval;
1296
1297 FNC_INFO;
1298
1299 if (target->state != TARGET_HALTED)
1300 {
1301 LOG_WARNING("target was not halted");
1302 return ERROR_TARGET_NOT_HALTED;
1303 }
1304
1305 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1306
1307 arm11_common_t * arm11 = target->arch_info;
1308
1309 retval = arm11_run_instr_data_prepare(arm11);
1310 if (retval != ERROR_OK)
1311 return retval;
1312
1313 /* MRC p14,0,r0,c0,c5,0 */
1314 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1315 if (retval != ERROR_OK)
1316 return retval;
1317
1318 switch (size)
1319 {
1320 case 1:
1321 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1322 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1323
1324 for (size_t i = 0; i < count; i++)
1325 {
1326 /* ldrb r1, [r0], #1 */
1327 /* ldrb r1, [r0] */
1328 arm11_run_instr_no_data1(arm11,
1329 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1330
1331 uint32_t res;
1332 /* MCR p14,0,R1,c0,c5,0 */
1333 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1334
1335 *buffer++ = res;
1336 }
1337
1338 break;
1339
1340 case 2:
1341 {
1342 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1343
1344 for (size_t i = 0; i < count; i++)
1345 {
1346 /* ldrh r1, [r0], #2 */
1347 arm11_run_instr_no_data1(arm11,
1348 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1349
1350 uint32_t res;
1351
1352 /* MCR p14,0,R1,c0,c5,0 */
1353 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1354
1355 uint16_t svalue = res;
1356 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1357 }
1358
1359 break;
1360 }
1361
1362 case 4:
1363 {
1364 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1365 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1366 uint32_t *words = (uint32_t *)buffer;
1367
1368 /* LDC p14,c5,[R0],#4 */
1369 /* LDC p14,c5,[R0] */
1370 arm11_run_instr_data_from_core(arm11, instr, words, count);
1371 break;
1372 }
1373 }
1374
1375 return arm11_run_instr_data_finish(arm11);
1376 }
1377
1378 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1379 {
1380 return arm11_read_memory_inner(target, address, size, count, buffer, false);
1381 }
1382
1383 /*
1384 * arm11_config_memrw_no_increment - in the future we may want to be able
1385 * to read/write a range of data to a "port". a "port" is an action on
1386 * read memory address for some peripheral.
1387 */
1388 int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1389 bool arm11_config_memrw_no_increment)
1390 {
1391 int retval;
1392 FNC_INFO;
1393
1394 if (target->state != TARGET_HALTED)
1395 {
1396 LOG_WARNING("target was not halted");
1397 return ERROR_TARGET_NOT_HALTED;
1398 }
1399
1400 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1401
1402 arm11_common_t * arm11 = target->arch_info;
1403
1404 arm11_run_instr_data_prepare(arm11);
1405
1406 /* MRC p14,0,r0,c0,c5,0 */
1407 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1408 if (retval != ERROR_OK)
1409 return retval;
1410
1411 /* burst writes are not used for single words as those may well be
1412 * reset init script writes.
1413 *
1414 * The other advantage is that as burst writes are default, we'll
1415 * now exercise both burst and non-burst code paths with the
1416 * default settings, increasing code coverage.
1417 */
1418 bool burst = arm11_config_memwrite_burst && (count > 1);
1419
1420 switch (size)
1421 {
1422 case 1:
1423 {
1424 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1425
1426 for (size_t i = 0; i < count; i++)
1427 {
1428 /* MRC p14,0,r1,c0,c5,0 */
1429 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1430 if (retval != ERROR_OK)
1431 return retval;
1432
1433 /* strb r1, [r0], #1 */
1434 /* strb r1, [r0] */
1435 retval = arm11_run_instr_no_data1(arm11,
1436 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1437 if (retval != ERROR_OK)
1438 return retval;
1439 }
1440
1441 break;
1442 }
1443
1444 case 2:
1445 {
1446 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1447
1448 for (size_t i = 0; i < count; i++)
1449 {
1450 uint16_t value;
1451 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1452
1453 /* MRC p14,0,r1,c0,c5,0 */
1454 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1455 if (retval != ERROR_OK)
1456 return retval;
1457
1458 /* strh r1, [r0], #2 */
1459 /* strh r1, [r0] */
1460 retval = arm11_run_instr_no_data1(arm11,
1461 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1462 if (retval != ERROR_OK)
1463 return retval;
1464 }
1465
1466 break;
1467 }
1468
1469 case 4: {
1470 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1471
1472 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1473 uint32_t *words = (uint32_t*)buffer;
1474
1475 if (!burst)
1476 {
1477 /* STC p14,c5,[R0],#4 */
1478 /* STC p14,c5,[R0]*/
1479 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1480 if (retval != ERROR_OK)
1481 return retval;
1482 }
1483 else
1484 {
1485 /* STC p14,c5,[R0],#4 */
1486 /* STC p14,c5,[R0]*/
1487 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1488 if (retval != ERROR_OK)
1489 return retval;
1490 }
1491
1492 break;
1493 }
1494 }
1495
1496 /* r0 verification */
1497 if (!arm11_config_memrw_no_increment)
1498 {
1499 uint32_t r0;
1500
1501 /* MCR p14,0,R0,c0,c5,0 */
1502 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1503 if (retval != ERROR_OK)
1504 return retval;
1505
1506 if (address + size * count != r0)
1507 {
1508 LOG_ERROR("Data transfer failed. Expected end "
1509 "address 0x%08x, got 0x%08x",
1510 (unsigned) (address + size * count),
1511 (unsigned) r0);
1512
1513 if (burst)
1514 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1515
1516 if (arm11_config_memwrite_error_fatal)
1517 return ERROR_FAIL;
1518 }
1519 }
1520
1521 return arm11_run_instr_data_finish(arm11);
1522 }
1523
1524 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1525 {
1526 return arm11_write_memory_inner(target, address, size, count, buffer, false);
1527 }
1528
1529 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1530 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1531 {
1532 FNC_INFO;
1533
1534 if (target->state != TARGET_HALTED)
1535 {
1536 LOG_WARNING("target was not halted");
1537 return ERROR_TARGET_NOT_HALTED;
1538 }
1539
1540 return arm11_write_memory(target, address, 4, count, buffer);
1541 }
1542
1543 /* here we have nothing target specific to contribute, so we fail and then the
1544 * fallback code will read data from the target and calculate the CRC on the
1545 * host.
1546 */
1547 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1548 {
1549 return ERROR_FAIL;
1550 }
1551
1552 /* target break-/watchpoint control
1553 * rw: 0 = write, 1 = read, 2 = access
1554 */
1555 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1556 {
1557 FNC_INFO;
1558
1559 arm11_common_t * arm11 = target->arch_info;
1560
1561 #if 0
1562 if (breakpoint->type == BKPT_SOFT)
1563 {
1564 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1565 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1566 }
1567 #endif
1568
1569 if (!arm11->free_brps)
1570 {
1571 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1572 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1573 }
1574
1575 if (breakpoint->length != 4)
1576 {
1577 LOG_DEBUG("only breakpoints of four bytes length supported");
1578 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1579 }
1580
1581 arm11->free_brps--;
1582
1583 return ERROR_OK;
1584 }
1585
1586 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1587 {
1588 FNC_INFO;
1589
1590 arm11_common_t * arm11 = target->arch_info;
1591
1592 arm11->free_brps++;
1593
1594 return ERROR_OK;
1595 }
1596
1597 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1598 {
1599 FNC_INFO_NOTIMPLEMENTED;
1600
1601 return ERROR_OK;
1602 }
1603
1604 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1605 {
1606 FNC_INFO_NOTIMPLEMENTED;
1607
1608 return ERROR_OK;
1609 }
1610
1611 // HACKHACKHACK - FIXME mode/state
1612 /* target algorithm support */
1613 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1614 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1615 int timeout_ms, void *arch_info)
1616 {
1617 arm11_common_t *arm11 = target->arch_info;
1618 // enum armv4_5_state core_state = arm11->core_state;
1619 // enum armv4_5_mode core_mode = arm11->core_mode;
1620 uint32_t context[16];
1621 uint32_t cpsr;
1622 int exit_breakpoint_size = 0;
1623 int retval = ERROR_OK;
1624 LOG_DEBUG("Running algorithm");
1625
1626
1627 if (target->state != TARGET_HALTED)
1628 {
1629 LOG_WARNING("target not halted");
1630 return ERROR_TARGET_NOT_HALTED;
1631 }
1632
1633 // FIXME
1634 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1635 // return ERROR_FAIL;
1636
1637 // Save regs
1638 for (size_t i = 0; i < 16; i++)
1639 {
1640 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1641 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1642 }
1643
1644 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1645 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1646
1647 for (int i = 0; i < num_mem_params; i++)
1648 {
1649 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1650 }
1651
1652 // Set register parameters
1653 for (int i = 0; i < num_reg_params; i++)
1654 {
1655 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1656 if (!reg)
1657 {
1658 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1659 exit(-1);
1660 }
1661
1662 if (reg->size != reg_params[i].size)
1663 {
1664 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1665 exit(-1);
1666 }
1667 arm11_set_reg(reg,reg_params[i].value);
1668 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1669 }
1670
1671 exit_breakpoint_size = 4;
1672
1673 /* arm11->core_state = arm11_algorithm_info->core_state;
1674 if (arm11->core_state == ARMV4_5_STATE_ARM)
1675 exit_breakpoint_size = 4;
1676 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1677 exit_breakpoint_size = 2;
1678 else
1679 {
1680 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1681 exit(-1);
1682 }
1683 */
1684
1685
1686 /* arm11 at this point only supports ARM not THUMB mode
1687 however if this test needs to be reactivated the current state can be read back
1688 from CPSR */
1689 #if 0
1690 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1691 {
1692 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1693 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1694 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1695 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1696 }
1697 #endif
1698
1699 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1700 {
1701 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1702 retval = ERROR_TARGET_FAILURE;
1703 goto restore;
1704 }
1705
1706 // no debug, otherwise breakpoint is not set
1707 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1708
1709 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1710
1711 if (target->state != TARGET_HALTED)
1712 {
1713 CHECK_RETVAL(target_halt(target));
1714
1715 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1716
1717 retval = ERROR_TARGET_TIMEOUT;
1718
1719 goto del_breakpoint;
1720 }
1721
1722 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1723 {
1724 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1725 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1726 retval = ERROR_TARGET_TIMEOUT;
1727 goto del_breakpoint;
1728 }
1729
1730 for (int i = 0; i < num_mem_params; i++)
1731 {
1732 if (mem_params[i].direction != PARAM_OUT)
1733 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1734 }
1735
1736 for (int i = 0; i < num_reg_params; i++)
1737 {
1738 if (reg_params[i].direction != PARAM_OUT)
1739 {
1740 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1741 if (!reg)
1742 {
1743 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1744 exit(-1);
1745 }
1746
1747 if (reg->size != reg_params[i].size)
1748 {
1749 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1750 exit(-1);
1751 }
1752
1753 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1754 }
1755 }
1756
1757 del_breakpoint:
1758 breakpoint_remove(target, exit_point);
1759
1760 restore:
1761 // Restore context
1762 for (size_t i = 0; i < 16; i++)
1763 {
1764 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1765 arm11->reg_list[i].name, context[i]);
1766 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1767 }
1768 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1769 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1770
1771 // arm11->core_state = core_state;
1772 // arm11->core_mode = core_mode;
1773
1774 return retval;
1775 }
1776
1777 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1778 {
1779 FNC_INFO;
1780
1781 NEW(arm11_common_t, arm11, 1);
1782
1783 arm11->target = target;
1784
1785 if (target->tap == NULL)
1786 return ERROR_FAIL;
1787
1788 if (target->tap->ir_length != 5)
1789 {
1790 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1791 return ERROR_COMMAND_SYNTAX_ERROR;
1792 }
1793
1794 target->arch_info = arm11;
1795
1796 return ERROR_OK;
1797 }
1798
1799 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1800 {
1801 /* Initialize anything we can set up without talking to the target */
1802 return arm11_build_reg_cache(target);
1803 }
1804
1805 /* talk to the target and set things up */
1806 int arm11_examine(struct target_s *target)
1807 {
1808 FNC_INFO;
1809
1810 arm11_common_t * arm11 = target->arch_info;
1811
1812 /* check IDCODE */
1813
1814 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1815
1816 scan_field_t idcode_field;
1817
1818 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1819
1820 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1821
1822 /* check DIDR */
1823
1824 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1825
1826 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1827
1828 scan_field_t chain0_fields[2];
1829
1830 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1831 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1832
1833 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1834
1835 CHECK_RETVAL(jtag_execute_queue());
1836
1837 switch (arm11->device_id & 0x0FFFF000)
1838 {
1839 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1840 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1841 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1842 default:
1843 {
1844 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1845 return ERROR_FAIL;
1846 }
1847 }
1848
1849 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1850
1851 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1852 arm11->debug_version != ARM11_DEBUG_V61)
1853 {
1854 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1855 return ERROR_FAIL;
1856 }
1857
1858 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1859 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1860
1861 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1862 arm11->free_brps = arm11->brp;
1863 arm11->free_wrps = arm11->wrp;
1864
1865 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1866 arm11->device_id,
1867 (int)(arm11->implementor),
1868 arm11->didr);
1869
1870 /* as a side-effect this reads DSCR and thus
1871 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1872 * as suggested by the spec.
1873 */
1874
1875 arm11_check_init(arm11, NULL);
1876
1877 target_set_examined(target);
1878
1879 return ERROR_OK;
1880 }
1881
1882 int arm11_quit(void)
1883 {
1884 FNC_INFO_NOTIMPLEMENTED;
1885
1886 return ERROR_OK;
1887 }
1888
1889 /** Load a register that is marked !valid in the register cache */
1890 int arm11_get_reg(reg_t *reg)
1891 {
1892 FNC_INFO;
1893
1894 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1895
1896 if (target->state != TARGET_HALTED)
1897 {
1898 LOG_WARNING("target was not halted");
1899 return ERROR_TARGET_NOT_HALTED;
1900 }
1901
1902 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1903
1904 #if 0
1905 arm11_common_t *arm11 = target->arch_info;
1906 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1907 #endif
1908
1909 return ERROR_OK;
1910 }
1911
1912 /** Change a value in the register cache */
1913 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1914 {
1915 FNC_INFO;
1916
1917 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1918 arm11_common_t *arm11 = target->arch_info;
1919 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1920
1921 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1922 reg->valid = 1;
1923 reg->dirty = 1;
1924
1925 return ERROR_OK;
1926 }
1927
1928 int arm11_build_reg_cache(target_t *target)
1929 {
1930 arm11_common_t *arm11 = target->arch_info;
1931
1932 NEW(reg_cache_t, cache, 1);
1933 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1934 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1935
1936 if (arm11_regs_arch_type == -1)
1937 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1938
1939 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1940 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1941
1942 arm11->reg_list = reg_list;
1943
1944 /* Build the process context cache */
1945 cache->name = "arm11 registers";
1946 cache->next = NULL;
1947 cache->reg_list = reg_list;
1948 cache->num_regs = ARM11_REGCACHE_COUNT;
1949
1950 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1951 (*cache_p) = cache;
1952
1953 arm11->core_cache = cache;
1954 // armv7m->process_context = cache;
1955
1956 size_t i;
1957
1958 /* Not very elegant assertion */
1959 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1960 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1961 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1962 {
1963 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1964 exit(-1);
1965 }
1966
1967 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1968 {
1969 reg_t * r = reg_list + i;
1970 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1971 arm11_reg_state_t * rs = arm11_reg_states + i;
1972
1973 r->name = rd->name;
1974 r->size = 32;
1975 r->value = (uint8_t *)(arm11->reg_values + i);
1976 r->dirty = 0;
1977 r->valid = 0;
1978 r->bitfield_desc = NULL;
1979 r->num_bitfields = 0;
1980 r->arch_type = arm11_regs_arch_type;
1981 r->arch_info = rs;
1982
1983 rs->def_index = i;
1984 rs->target = target;
1985 }
1986
1987 return ERROR_OK;
1988 }
1989
1990 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1991 {
1992 if (argc == 0)
1993 {
1994 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1995 return ERROR_OK;
1996 }
1997
1998 if (argc != 1)
1999 return ERROR_COMMAND_SYNTAX_ERROR;
2000
2001 switch (args[0][0])
2002 {
2003 case '0': /* 0 */
2004 case 'f': /* false */
2005 case 'F':
2006 case 'd': /* disable */
2007 case 'D':
2008 *var = false;
2009 break;
2010
2011 case '1': /* 1 */
2012 case 't': /* true */
2013 case 'T':
2014 case 'e': /* enable */
2015 case 'E':
2016 *var = true;
2017 break;
2018 }
2019
2020 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2021
2022 return ERROR_OK;
2023 }
2024
2025 #define BOOL_WRAPPER(name, print_name) \
2026 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
2027 { \
2028 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
2029 }
2030
2031 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
2032 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
2033 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
2034 BOOL_WRAPPER(hardware_step, "hardware single step")
2035
2036 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2037 {
2038 if (argc == 1)
2039 {
2040 arm11_vcr = strtoul(args[0], NULL, 0);
2041 }
2042 else if (argc != 0)
2043 {
2044 return ERROR_COMMAND_SYNTAX_ERROR;
2045 }
2046
2047 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2048 return ERROR_OK;
2049 }
2050
2051 const uint32_t arm11_coproc_instruction_limits[] =
2052 {
2053 15, /* coprocessor */
2054 7, /* opcode 1 */
2055 15, /* CRn */
2056 15, /* CRm */
2057 7, /* opcode 2 */
2058 0xFFFFFFFF, /* value */
2059 };
2060
2061 arm11_common_t * arm11_find_target(const char * arg)
2062 {
2063 jtag_tap_t * tap;
2064 target_t * t;
2065
2066 tap = jtag_tap_by_string(arg);
2067
2068 if (!tap)
2069 return 0;
2070
2071 for (t = all_targets; t; t = t->next)
2072 {
2073 if (t->tap != tap)
2074 continue;
2075
2076 /* if (t->type == arm11_target) */
2077 if (0 == strcmp(target_get_name(t), "arm11"))
2078 return t->arch_info;
2079 }
2080
2081 return 0;
2082 }
2083
2084 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2085 {
2086 int retval;
2087
2088 if (argc != (read ? 6 : 7))
2089 {
2090 LOG_ERROR("Invalid number of arguments.");
2091 return ERROR_COMMAND_SYNTAX_ERROR;
2092 }
2093
2094 arm11_common_t * arm11 = arm11_find_target(args[0]);
2095
2096 if (!arm11)
2097 {
2098 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2099 return ERROR_COMMAND_SYNTAX_ERROR;
2100 }
2101
2102 if (arm11->target->state != TARGET_HALTED)
2103 {
2104 LOG_WARNING("target was not halted");
2105 return ERROR_TARGET_NOT_HALTED;
2106 }
2107
2108 uint32_t values[6];
2109
2110 for (size_t i = 0; i < (read ? 5 : 6); i++)
2111 {
2112 values[i] = strtoul(args[i + 1], NULL, 0);
2113
2114 if (values[i] > arm11_coproc_instruction_limits[i])
2115 {
2116 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2117 (long)(i + 2),
2118 arm11_coproc_instruction_limits[i]);
2119 return ERROR_COMMAND_SYNTAX_ERROR;
2120 }
2121 }
2122
2123 uint32_t instr = 0xEE000010 |
2124 (values[0] << 8) |
2125 (values[1] << 21) |
2126 (values[2] << 16) |
2127 (values[3] << 0) |
2128 (values[4] << 5);
2129
2130 if (read)
2131 instr |= 0x00100000;
2132
2133 retval = arm11_run_instr_data_prepare(arm11);
2134 if (retval != ERROR_OK)
2135 return retval;
2136
2137 if (read)
2138 {
2139 uint32_t result;
2140 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2141 if (retval != ERROR_OK)
2142 return retval;
2143
2144 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2145 (int)(values[0]),
2146 (int)(values[1]),
2147 (int)(values[2]),
2148 (int)(values[3]),
2149 (int)(values[4]), result, result);
2150 }
2151 else
2152 {
2153 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2154 if (retval != ERROR_OK)
2155 return retval;
2156
2157 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2158 (int)(values[0]), (int)(values[1]),
2159 values[5],
2160 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2161 }
2162
2163 return arm11_run_instr_data_finish(arm11);
2164 }
2165
2166 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2167 {
2168 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2169 }
2170
2171 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2172 {
2173 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2174 }
2175
2176 int arm11_register_commands(struct command_context_s *cmd_ctx)
2177 {
2178 FNC_INFO;
2179
2180 command_t *top_cmd, *mw_cmd;
2181
2182 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2183 NULL, COMMAND_ANY, NULL);
2184
2185 /* "hardware_step" is only here to check if the default
2186 * simulate + breakpoint implementation is broken.
2187 * TEMPORARY! NOT DOCUMENTED!
2188 */
2189 register_command(cmd_ctx, top_cmd, "hardware_step",
2190 arm11_handle_bool_hardware_step, COMMAND_ANY,
2191 "DEBUG ONLY - Hardware single stepping"
2192 " (default: disabled)");
2193
2194 register_command(cmd_ctx, top_cmd, "mcr",
2195 arm11_handle_mcr, COMMAND_ANY,
2196 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2197
2198 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2199 NULL, COMMAND_ANY, NULL);
2200 register_command(cmd_ctx, mw_cmd, "burst",
2201 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2202 "Enable/Disable non-standard but fast burst mode"
2203 " (default: enabled)");
2204 register_command(cmd_ctx, mw_cmd, "error_fatal",
2205 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2206 "Terminate program if transfer error was found"
2207 " (default: enabled)");
2208
2209 register_command(cmd_ctx, top_cmd, "mrc",
2210 arm11_handle_mrc, COMMAND_ANY,
2211 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2212 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2213 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2214 "Enable interrupts while stepping"
2215 " (default: disabled)");
2216 register_command(cmd_ctx, top_cmd, "vcr",
2217 arm11_handle_vcr, COMMAND_ANY,
2218 "Control (Interrupt) Vector Catch Register");
2219
2220 return ERROR_OK;
2221 }
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