1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define _DEBUG_INSTRUCTION_EXECUTION_
39 #define FNC_INFO LOG_DEBUG("-")
45 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #define FNC_INFO_NOTIMPLEMENTED
50 static void arm11_on_enter_debug_state(arm11_common_t
* arm11
);
53 bool arm11_config_memwrite_burst
= true;
54 bool arm11_config_memwrite_error_fatal
= true;
58 #define ARM11_HANDLER(x) \
61 target_type_t arm11_target
=
66 ARM11_HANDLER(arch_state
),
68 ARM11_HANDLER(target_request_data
),
71 ARM11_HANDLER(resume
),
74 ARM11_HANDLER(assert_reset
),
75 ARM11_HANDLER(deassert_reset
),
76 ARM11_HANDLER(soft_reset_halt
),
78 ARM11_HANDLER(get_gdb_reg_list
),
80 ARM11_HANDLER(read_memory
),
81 ARM11_HANDLER(write_memory
),
83 ARM11_HANDLER(bulk_write_memory
),
85 ARM11_HANDLER(checksum_memory
),
87 ARM11_HANDLER(add_breakpoint
),
88 ARM11_HANDLER(remove_breakpoint
),
89 ARM11_HANDLER(add_watchpoint
),
90 ARM11_HANDLER(remove_watchpoint
),
92 ARM11_HANDLER(run_algorithm
),
94 ARM11_HANDLER(register_commands
),
95 ARM11_HANDLER(target_command
),
96 ARM11_HANDLER(init_target
),
97 ARM11_HANDLER(examine
),
101 int arm11_regs_arch_type
= -1;
119 ARM11_REGISTER_SPSR_FIQ
,
120 ARM11_REGISTER_SPSR_SVC
,
121 ARM11_REGISTER_SPSR_ABT
,
122 ARM11_REGISTER_SPSR_IRQ
,
123 ARM11_REGISTER_SPSR_UND
,
124 ARM11_REGISTER_SPSR_MON
,
133 typedef struct arm11_reg_defs_s
138 enum arm11_regtype type
;
141 /* update arm11_regcache_ids when changing this */
142 static const arm11_reg_defs_t arm11_reg_defs
[] =
144 {"r0", 0, 0, ARM11_REGISTER_CORE
},
145 {"r1", 1, 1, ARM11_REGISTER_CORE
},
146 {"r2", 2, 2, ARM11_REGISTER_CORE
},
147 {"r3", 3, 3, ARM11_REGISTER_CORE
},
148 {"r4", 4, 4, ARM11_REGISTER_CORE
},
149 {"r5", 5, 5, ARM11_REGISTER_CORE
},
150 {"r6", 6, 6, ARM11_REGISTER_CORE
},
151 {"r7", 7, 7, ARM11_REGISTER_CORE
},
152 {"r8", 8, 8, ARM11_REGISTER_CORE
},
153 {"r9", 9, 9, ARM11_REGISTER_CORE
},
154 {"r10", 10, 10, ARM11_REGISTER_CORE
},
155 {"r11", 11, 11, ARM11_REGISTER_CORE
},
156 {"r12", 12, 12, ARM11_REGISTER_CORE
},
157 {"sp", 13, 13, ARM11_REGISTER_CORE
},
158 {"lr", 14, 14, ARM11_REGISTER_CORE
},
159 {"pc", 15, 15, ARM11_REGISTER_CORE
},
161 #if ARM11_REGCACHE_FREGS
162 {"f0", 0, 16, ARM11_REGISTER_FX
},
163 {"f1", 1, 17, ARM11_REGISTER_FX
},
164 {"f2", 2, 18, ARM11_REGISTER_FX
},
165 {"f3", 3, 19, ARM11_REGISTER_FX
},
166 {"f4", 4, 20, ARM11_REGISTER_FX
},
167 {"f5", 5, 21, ARM11_REGISTER_FX
},
168 {"f6", 6, 22, ARM11_REGISTER_FX
},
169 {"f7", 7, 23, ARM11_REGISTER_FX
},
170 {"fps", 0, 24, ARM11_REGISTER_FPS
},
173 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
175 #if ARM11_REGCACHE_MODEREGS
176 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
177 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
178 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
179 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
180 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
181 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
182 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
183 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
185 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
186 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
187 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
189 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
190 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
191 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
193 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
194 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
195 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
197 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
198 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
199 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
202 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
203 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
204 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
207 /* Debug Registers */
208 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
209 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
210 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
213 enum arm11_regcache_ids
216 ARM11_RC_RX
= ARM11_RC_R0
,
231 ARM11_RC_SP
= ARM11_RC_R13
,
233 ARM11_RC_LR
= ARM11_RC_R14
,
235 ARM11_RC_PC
= ARM11_RC_R15
,
237 #if ARM11_REGCACHE_FREGS
239 ARM11_RC_FX
= ARM11_RC_F0
,
252 #if ARM11_REGCACHE_MODEREGS
290 #define ARM11_GDB_REGISTER_COUNT 26
292 u8 arm11_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
294 reg_t arm11_gdb_dummy_fp_reg
=
296 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
299 u8 arm11_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
301 reg_t arm11_gdb_dummy_fps_reg
=
303 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
308 /** Check and if necessary take control of the system
310 * \param arm11 Target state variable.
311 * \param dscr If the current DSCR content is
312 * available a pointer to a word holding the
313 * DSCR can be passed. Otherwise use NULL.
315 void arm11_check_init(arm11_common_t
* arm11
, u32
* dscr
)
319 u32 dscr_local_tmp_copy
;
323 dscr
= &dscr_local_tmp_copy
;
324 *dscr
= arm11_read_DSCR(arm11
);
327 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
329 LOG_DEBUG("Bringing target into debug mode");
331 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
332 arm11_write_DSCR(arm11
, *dscr
);
334 /* add further reset initialization here */
336 arm11
->simulate_reset_on_next_halt
= true;
338 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
340 /** \todo TODO: this needs further scrutiny because
341 * arm11_on_enter_debug_state() never gets properly called
344 arm11
->target
->state
= TARGET_HALTED
;
345 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
349 arm11
->target
->state
= TARGET_RUNNING
;
350 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
353 arm11_sc7_clear_vbw(arm11
);
360 (arm11->reg_values[ARM11_RC_##x])
362 /** Save processor state.
364 * This is called when the HALT instruction has succeeded
365 * or on other occasions that stop the processor.
368 static void arm11_on_enter_debug_state(arm11_common_t
* arm11
)
373 for(i
= 0; i
< asizeof(arm11
->reg_values
); i
++)
375 arm11
->reg_list
[i
].valid
= 1;
376 arm11
->reg_list
[i
].dirty
= 0;
381 R(DSCR
) = arm11_read_DSCR(arm11
);
385 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
387 arm11_add_debug_SCAN_N(arm11
, 0x05, -1);
389 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
391 scan_field_t chain5_fields
[3];
393 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
394 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
395 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
397 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
401 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
405 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
406 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
407 ARM1136 seems to require this to issue ITR's as well */
409 u32 new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
411 /* this executes JTAG queue: */
413 arm11_write_DSCR(arm11
, new_dscr
);
417 Before executing any instruction in debug state you have to drain the write buffer.
418 This ensures that no imprecise Data Aborts can return at a later point:*/
420 /** \todo TODO: Test drain write buffer. */
425 /* MRC p14,0,R0,c5,c10,0 */
426 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
428 /* mcr 15, 0, r0, cr7, cr10, {4} */
429 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
431 u32 dscr
= arm11_read_DSCR(arm11
);
433 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
435 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
437 arm11_run_instr_no_data1(arm11
, 0xe320f000);
439 dscr
= arm11_read_DSCR(arm11
);
441 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
449 arm11_run_instr_data_prepare(arm11
);
454 /** \todo TODO: handle other mode registers */
457 for (i
= 0; i
< 15; i
++)
459 /* MCR p14,0,R?,c0,c5,0 */
460 arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
466 /* check rDTRfull in DSCR */
468 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
470 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
471 arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
475 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
480 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
481 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
485 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
488 /* adjust PC depending on ARM state */
490 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
492 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
494 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
496 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
500 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
503 if (arm11
->simulate_reset_on_next_halt
)
505 arm11
->simulate_reset_on_next_halt
= false;
507 LOG_DEBUG("Reset c1 Control Register");
509 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
511 /* MCR p15,0,R0,c1,c0,0 */
512 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
516 arm11_run_instr_data_finish(arm11
);
518 arm11_dump_reg_changes(arm11
);
521 void arm11_dump_reg_changes(arm11_common_t
* arm11
)
524 for(i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
526 if (!arm11
->reg_list
[i
].valid
)
528 if (arm11
->reg_history
[i
].valid
)
529 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
533 if (arm11
->reg_history
[i
].valid
)
535 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
536 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
540 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
547 /** Restore processor state
549 * This is called in preparation for the RESTART function.
552 void arm11_leave_debug_state(arm11_common_t
* arm11
)
556 arm11_run_instr_data_prepare(arm11
);
558 /** \todo TODO: handle other mode registers */
560 /* restore R1 - R14 */
562 for (i
= 1; i
< 15; i
++)
564 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
567 /* MRC p14,0,r?,c0,c5,0 */
568 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
570 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
573 arm11_run_instr_data_finish(arm11
);
576 /* spec says clear wDTR and rDTR; we assume they are clear as
577 otherwise our programming would be sloppy */
580 u32 DSCR
= arm11_read_DSCR(arm11
);
582 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
584 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR
);
588 arm11_run_instr_data_prepare(arm11
);
590 /* restore original wDTR */
592 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
594 /* MCR p14,0,R0,c0,c5,0 */
595 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
601 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
607 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
612 /* MRC p14,0,r0,c0,c5,0 */
613 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
615 arm11_run_instr_data_finish(arm11
);
620 arm11_write_DSCR(arm11
, R(DSCR
));
625 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
627 arm11_add_debug_SCAN_N(arm11
, 0x05, -1);
629 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
631 scan_field_t chain5_fields
[3];
633 u8 Ready
= 0; /* ignored */
634 u8 Valid
= 0; /* ignored */
636 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
637 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
638 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
640 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
643 arm11_record_register_history(arm11
);
646 void arm11_record_register_history(arm11_common_t
* arm11
)
649 for(i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
651 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
652 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
654 arm11
->reg_list
[i
].valid
= 0;
655 arm11
->reg_list
[i
].dirty
= 0;
660 /* poll current target status */
661 int arm11_poll(struct target_s
*target
)
665 arm11_common_t
* arm11
= target
->arch_info
;
667 if (arm11
->trst_active
)
670 u32 dscr
= arm11_read_DSCR(arm11
);
672 LOG_DEBUG("DSCR %08x", dscr
);
674 arm11_check_init(arm11
, &dscr
);
676 if (dscr
& ARM11_DSCR_CORE_HALTED
)
678 if (target
->state
!= TARGET_HALTED
)
680 enum target_state old_state
= target
->state
;
682 LOG_DEBUG("enter TARGET_HALTED");
683 target
->state
= TARGET_HALTED
;
684 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
685 arm11_on_enter_debug_state(arm11
);
687 target_call_event_callbacks(target
,
688 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
693 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
695 LOG_DEBUG("enter TARGET_RUNNING");
696 target
->state
= TARGET_RUNNING
;
697 target
->debug_reason
= DBG_REASON_NOTHALTED
;
703 /* architecture specific status reply */
704 int arm11_arch_state(struct target_s
*target
)
706 FNC_INFO_NOTIMPLEMENTED
;
712 /* target request support */
713 int arm11_target_request_data(struct target_s
*target
, u32 size
, u8
*buffer
)
715 FNC_INFO_NOTIMPLEMENTED
;
722 /* target execution control */
723 int arm11_halt(struct target_s
*target
)
727 arm11_common_t
* arm11
= target
->arch_info
;
729 LOG_DEBUG("target->state: %s",
730 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
732 if (target
->state
== TARGET_UNKNOWN
)
734 arm11
->simulate_reset_on_next_halt
= true;
737 if (target
->state
== TARGET_HALTED
)
739 LOG_DEBUG("target was already halted");
743 if (arm11
->trst_active
)
745 arm11
->halt_requested
= true;
749 arm11_add_IR(arm11
, ARM11_HALT
, TAP_RTI
);
751 jtag_execute_queue();
757 dscr
= arm11_read_DSCR(arm11
);
759 if (dscr
& ARM11_DSCR_CORE_HALTED
)
763 arm11_on_enter_debug_state(arm11
);
765 enum target_state old_state
= target
->state
;
767 target
->state
= TARGET_HALTED
;
768 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
770 target_call_event_callbacks(target
,
771 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
777 int arm11_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
781 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
782 // current, address, handle_breakpoints, debug_execution);
784 arm11_common_t
* arm11
= target
->arch_info
;
786 LOG_DEBUG("target->state: %s",
787 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
790 if (target
->state
!= TARGET_HALTED
)
792 LOG_ERROR("Target not halted");
793 return ERROR_TARGET_NOT_HALTED
;
799 LOG_INFO("RESUME PC %08x%s", R(PC
), !current
? "!" : "");
801 /* clear breakpoints/watchpoints and VCR*/
802 arm11_sc7_clear_vbw(arm11
);
804 /* Set up breakpoints */
805 if (!debug_execution
)
807 /* check if one matches PC and step over it if necessary */
811 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
813 if (bp
->address
== R(PC
))
815 LOG_DEBUG("must step over %08x", bp
->address
);
816 arm11_step(target
, 1, 0, 0);
821 /* set all breakpoints */
825 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
827 arm11_sc7_action_t brp
[2];
830 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
831 brp
[0].value
= bp
->address
;
833 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
834 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
836 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
838 LOG_DEBUG("Add BP " ZU
" at %08x", brp_num
, bp
->address
);
843 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
847 arm11_leave_debug_state(arm11
);
849 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_RTI
);
851 jtag_execute_queue();
855 u32 dscr
= arm11_read_DSCR(arm11
);
857 LOG_DEBUG("DSCR %08x", dscr
);
859 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
863 if (!debug_execution
)
865 target
->state
= TARGET_RUNNING
;
866 target
->debug_reason
= DBG_REASON_NOTHALTED
;
867 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
871 target
->state
= TARGET_DEBUG_RUNNING
;
872 target
->debug_reason
= DBG_REASON_NOTHALTED
;
873 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
879 int arm11_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
883 LOG_DEBUG("target->state: %s",
884 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
886 if (target
->state
!= TARGET_HALTED
)
888 LOG_WARNING("target was not halted");
889 return ERROR_TARGET_NOT_HALTED
;
892 arm11_common_t
* arm11
= target
->arch_info
;
897 LOG_INFO("STEP PC %08x%s", R(PC
), !current
? "!" : "");
899 /** \todo TODO: Thumb not supported here */
901 u32 next_instruction
;
903 arm11_read_memory_word(arm11
, R(PC
), &next_instruction
);
906 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
909 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
910 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
911 LOG_INFO("Skipping BKPT");
913 /* skip over Wait for interrupt / Standby */
914 /* mcr 15, 0, r?, cr7, cr0, {4} */
915 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
918 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
919 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
920 LOG_INFO("Skipping WFI");
922 /* ignore B to self */
923 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
925 LOG_INFO("Not stepping jump to self");
929 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
932 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
933 * the VCR might be something worth looking into. */
936 /* Set up breakpoint for stepping */
938 arm11_sc7_action_t brp
[2];
941 brp
[0].address
= ARM11_SC7_BVR0
;
942 brp
[0].value
= R(PC
);
944 brp
[1].address
= ARM11_SC7_BCR0
;
945 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
947 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
951 arm11_leave_debug_state(arm11
);
953 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_RTI
);
955 jtag_execute_queue();
957 /** \todo TODO: add a timeout */
963 u32 dscr
= arm11_read_DSCR(arm11
);
965 LOG_DEBUG("DSCR %08x", dscr
);
967 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
968 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
972 /* clear breakpoint */
973 arm11_sc7_clear_vbw(arm11
);
976 arm11_on_enter_debug_state(arm11
);
979 // target->state = TARGET_HALTED;
980 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
982 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
988 /* target reset control */
989 int arm11_assert_reset(struct target_s
*target
)
994 /* assert reset lines */
995 /* resets only the DBGTAP, not the ARM */
997 jtag_add_reset(1, 0);
998 jtag_add_sleep(5000);
1000 arm11_common_t
* arm11
= target
->arch_info
;
1001 arm11
->trst_active
= true;
1004 if (target
->reset_halt
)
1007 if ((retval
= target_halt(target
))!=ERROR_OK
)
1014 int arm11_deassert_reset(struct target_s
*target
)
1019 LOG_DEBUG("target->state: %s",
1020 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
1023 /* deassert reset lines */
1024 jtag_add_reset(0, 0);
1026 arm11_common_t
* arm11
= target
->arch_info
;
1027 arm11
->trst_active
= false;
1029 if (arm11
->halt_requested
)
1030 return arm11_halt(target
);
1036 int arm11_soft_reset_halt(struct target_s
*target
)
1038 FNC_INFO_NOTIMPLEMENTED
;
1045 /* target register access for gdb */
1046 int arm11_get_gdb_reg_list(struct target_s
*target
, struct reg_s
**reg_list
[], int *reg_list_size
)
1050 arm11_common_t
* arm11
= target
->arch_info
;
1052 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1053 *reg_list
= malloc(sizeof(reg_t
*) * ARM11_GDB_REGISTER_COUNT
);
1056 for (i
= 16; i
< 24; i
++)
1058 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1061 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1065 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1067 if (arm11_reg_defs
[i
].gdb_num
== -1)
1070 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1077 /* target memory access
1078 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1079 * count: number of items of <size>
1081 int arm11_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1083 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1087 if (target
->state
!= TARGET_HALTED
)
1089 LOG_WARNING("target was not halted");
1090 return ERROR_TARGET_NOT_HALTED
;
1093 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address
, size
, count
);
1095 arm11_common_t
* arm11
= target
->arch_info
;
1097 arm11_run_instr_data_prepare(arm11
);
1099 /* MRC p14,0,r0,c0,c5,0 */
1100 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1105 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1106 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1109 for (i
= 0; i
< count
; i
++)
1111 /* ldrb r1, [r0], #1 */
1112 arm11_run_instr_no_data1(arm11
, 0xe4d01001);
1115 /* MCR p14,0,R1,c0,c5,0 */
1116 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1125 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1127 u16
* buf16
= (u16
*)buffer
;
1130 for (i
= 0; i
< count
; i
++)
1132 /* ldrh r1, [r0], #2 */
1133 arm11_run_instr_no_data1(arm11
, 0xe0d010b2);
1137 /* MCR p14,0,R1,c0,c5,0 */
1138 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1148 /* LDC p14,c5,[R0],#4 */
1149 arm11_run_instr_data_from_core(arm11
, 0xecb05e01, (u32
*)buffer
, count
);
1153 arm11_run_instr_data_finish(arm11
);
1158 int arm11_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1162 if (target
->state
!= TARGET_HALTED
)
1164 LOG_WARNING("target was not halted");
1165 return ERROR_TARGET_NOT_HALTED
;
1168 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address
, size
, count
);
1170 arm11_common_t
* arm11
= target
->arch_info
;
1172 arm11_run_instr_data_prepare(arm11
);
1174 /* MRC p14,0,r0,c0,c5,0 */
1175 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1181 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1184 for (i
= 0; i
< count
; i
++)
1186 /* MRC p14,0,r1,c0,c5,0 */
1187 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1189 /* strb r1, [r0], #1 */
1190 arm11_run_instr_no_data1(arm11
, 0xe4c01001);
1198 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1200 u16
* buf16
= (u16
*)buffer
;
1203 for (i
= 0; i
< count
; i
++)
1205 /* MRC p14,0,r1,c0,c5,0 */
1206 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buf16
++);
1208 /* strh r1, [r0], #2 */
1209 arm11_run_instr_no_data1(arm11
, 0xe0c010b2);
1216 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1218 if (!arm11_config_memwrite_burst
)
1220 /* STC p14,c5,[R0],#4 */
1221 arm11_run_instr_data_to_core(arm11
, 0xeca05e01, (u32
*)buffer
, count
);
1225 /* STC p14,c5,[R0],#4 */
1226 arm11_run_instr_data_to_core_noack(arm11
, 0xeca05e01, (u32
*)buffer
, count
);
1233 /* r0 verification */
1237 /* MCR p14,0,R0,c0,c5,0 */
1238 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1240 if (address
+ size
* count
!= r0
)
1242 LOG_ERROR("Data transfer failed. (%d)", (r0
- address
) - size
* count
);
1244 if (arm11_config_memwrite_burst
)
1245 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1247 if (arm11_config_memwrite_error_fatal
)
1254 arm11_run_instr_data_finish(arm11
);
1263 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1264 int arm11_bulk_write_memory(struct target_s
*target
, u32 address
, u32 count
, u8
*buffer
)
1268 if (target
->state
!= TARGET_HALTED
)
1270 LOG_WARNING("target was not halted");
1271 return ERROR_TARGET_NOT_HALTED
;
1274 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1278 int arm11_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
1280 FNC_INFO_NOTIMPLEMENTED
;
1286 /* target break-/watchpoint control
1287 * rw: 0 = write, 1 = read, 2 = access
1289 int arm11_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1293 arm11_common_t
* arm11
= target
->arch_info
;
1296 if (breakpoint
->type
== BKPT_SOFT
)
1298 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1299 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1303 if (!arm11
->free_brps
)
1305 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1306 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1309 if (breakpoint
->length
!= 4)
1311 LOG_INFO("only breakpoints of four bytes length supported");
1312 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1320 int arm11_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1324 arm11_common_t
* arm11
= target
->arch_info
;
1331 int arm11_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1333 FNC_INFO_NOTIMPLEMENTED
;
1338 int arm11_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1340 FNC_INFO_NOTIMPLEMENTED
;
1346 /* target algorithm support */
1347 int arm11_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_param
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
1349 FNC_INFO_NOTIMPLEMENTED
;
1354 int arm11_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
1360 return ERROR_COMMAND_SYNTAX_ERROR
;
1363 int chain_pos
= strtoul(args
[3], NULL
, 0);
1365 NEW(arm11_common_t
, arm11
, 1);
1367 arm11
->target
= target
;
1369 /* prepare JTAG information for the new target */
1370 arm11
->jtag_info
.chain_pos
= chain_pos
;
1371 arm11
->jtag_info
.scann_size
= 5;
1373 arm_jtag_setup_connection(&arm11
->jtag_info
);
1375 jtag_device_t
*device
= jtag_get_device(chain_pos
);
1377 if (device
->ir_length
!= 5)
1379 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1380 return ERROR_COMMAND_SYNTAX_ERROR
;
1383 target
->arch_info
= arm11
;
1388 int arm11_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
1390 /* Initialize anything we can set up without talking to the target */
1394 /* talk to the target and set things up */
1395 int arm11_examine(struct target_s
*target
)
1400 arm11_common_t
* arm11
= target
->arch_info
;
1404 arm11_add_IR(arm11
, ARM11_IDCODE
, -1);
1406 scan_field_t idcode_field
;
1408 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1410 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_PD
);
1414 arm11_add_debug_SCAN_N(arm11
, 0x00, -1);
1416 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
1418 scan_field_t chain0_fields
[2];
1420 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1421 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1423 arm11_add_dr_scan_vc(asizeof(chain0_fields
), chain0_fields
, TAP_RTI
);
1425 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
1429 switch (arm11
->device_id
& 0x0FFFF000)
1431 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1432 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1433 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1436 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1441 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1443 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1444 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1446 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1451 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1452 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1454 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1455 arm11
->free_brps
= arm11
->brp
;
1456 arm11
->free_wrps
= arm11
->wrp
;
1458 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1463 arm11_build_reg_cache(target
);
1466 /* as a side-effect this reads DSCR and thus
1467 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1468 * as suggested by the spec.
1471 arm11_check_init(arm11
, NULL
);
1476 int arm11_quit(void)
1478 FNC_INFO_NOTIMPLEMENTED
;
1483 /** Load a register that is marked !valid in the register cache */
1484 int arm11_get_reg(reg_t
*reg
)
1488 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1490 if (target
->state
!= TARGET_HALTED
)
1492 LOG_WARNING("target was not halted");
1493 return ERROR_TARGET_NOT_HALTED
;
1496 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1499 arm11_common_t
*arm11
= target
->arch_info
;
1500 const arm11_reg_defs_t
* arm11_reg_info
= arm11_reg_defs
+ ((arm11_reg_state_t
*)reg
->arch_info
)->def_index
;
1506 /** Change a value in the register cache */
1507 int arm11_set_reg(reg_t
*reg
, u8
*buf
)
1511 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1512 arm11_common_t
*arm11
= target
->arch_info
;
1513 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1515 arm11
->reg_values
[((arm11_reg_state_t
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1523 void arm11_build_reg_cache(target_t
*target
)
1525 arm11_common_t
*arm11
= target
->arch_info
;
1527 NEW(reg_cache_t
, cache
, 1);
1528 NEW(reg_t
, reg_list
, ARM11_REGCACHE_COUNT
);
1529 NEW(arm11_reg_state_t
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1531 if (arm11_regs_arch_type
== -1)
1532 arm11_regs_arch_type
= register_reg_arch_type(arm11_get_reg
, arm11_set_reg
);
1534 arm11
->reg_list
= reg_list
;
1536 /* Build the process context cache */
1537 cache
->name
= "arm11 registers";
1539 cache
->reg_list
= reg_list
;
1540 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1542 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1545 // armv7m->core_cache = cache;
1546 // armv7m->process_context = cache;
1550 /* Not very elegant assertion */
1551 if (ARM11_REGCACHE_COUNT
!= asizeof(arm11
->reg_values
) ||
1552 ARM11_REGCACHE_COUNT
!= asizeof(arm11_reg_defs
) ||
1553 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1555 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, asizeof(arm11
->reg_values
), asizeof(arm11_reg_defs
), ARM11_RC_MAX
);
1559 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1561 reg_t
* r
= reg_list
+ i
;
1562 const arm11_reg_defs_t
* rd
= arm11_reg_defs
+ i
;
1563 arm11_reg_state_t
* rs
= arm11_reg_states
+ i
;
1567 r
->value
= (u8
*)(arm11
->reg_values
+ i
);
1570 r
->bitfield_desc
= NULL
;
1571 r
->num_bitfields
= 0;
1572 r
->arch_type
= arm11_regs_arch_type
;
1576 rs
->target
= target
;
1582 int arm11_handle_bool(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool * var
, char * name
)
1586 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
1591 return ERROR_COMMAND_SYNTAX_ERROR
;
1596 case 'f': /* false */
1598 case 'd': /* disable */
1604 case 't': /* true */
1606 case 'e': /* enable */
1612 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
1618 #define BOOL_WRAPPER(name, print_name) \
1619 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1621 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1624 #define RC_TOP(name, descr, more) \
1626 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1627 command_t * top_cmd = new_cmd; \
1631 #define RC_FINAL(name, descr, handler) \
1632 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1634 #define RC_FINAL_BOOL(name, descr, var) \
1635 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1638 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1639 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1642 int arm11_handle_vcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1646 arm11_vcr
= strtoul(args
[0], NULL
, 0);
1650 return ERROR_COMMAND_SYNTAX_ERROR
;
1653 LOG_INFO("VCR 0x%08X", arm11_vcr
);
1657 const u32 arm11_coproc_instruction_limits
[] =
1659 15, /* coprocessor */
1664 0xFFFFFFFF, /* value */
1667 const char arm11_mrc_syntax
[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1668 const char arm11_mcr_syntax
[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1671 arm11_common_t
* arm11_find_target(const char * arg
)
1673 size_t jtag_target
= strtoul(arg
, NULL
, 0);
1676 for (t
= all_targets
; t
; t
= t
->next
)
1678 if (t
->type
!= &arm11_target
)
1681 arm11_common_t
* arm11
= t
->arch_info
;
1683 if (arm11
->jtag_info
.chain_pos
!= jtag_target
)
1692 int arm11_handle_mrc_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool read
)
1694 if (argc
!= (read
? 6 : 7))
1696 LOG_ERROR("Invalid number of arguments. %s", read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1700 arm11_common_t
* arm11
= arm11_find_target(args
[0]);
1704 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1705 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1711 if (arm11
->target
->state
!= TARGET_HALTED
)
1713 LOG_WARNING("target was not halted");
1714 return ERROR_TARGET_NOT_HALTED
;
1721 for (i
= 0; i
< (read
? 5 : 6); i
++)
1723 values
[i
] = strtoul(args
[i
+ 1], NULL
, 0);
1725 if (values
[i
] > arm11_coproc_instruction_limits
[i
])
1727 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1728 (long)(i
+ 2), arm11_coproc_instruction_limits
[i
],
1729 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1734 u32 instr
= 0xEE000010 |
1742 instr
|= 0x00100000;
1745 arm11_run_instr_data_prepare(arm11
);
1750 arm11_run_instr_data_from_core_via_r0(arm11
, instr
, &result
);
1752 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1753 values
[0], values
[1], values
[2], values
[3], values
[4], result
, result
);
1757 arm11_run_instr_data_to_core_via_r0(arm11
, instr
, values
[5]);
1759 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1760 values
[0], values
[1],
1762 values
[2], values
[3], values
[4]);
1765 arm11_run_instr_data_finish(arm11
);
1771 int arm11_handle_mrc(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1773 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, true);
1776 int arm11_handle_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1778 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, false);
1781 int arm11_register_commands(struct command_context_s
*cmd_ctx
)
1785 command_t
* top_cmd
= NULL
;
1787 RC_TOP( "arm11", "arm11 specific commands",
1789 RC_TOP( "memwrite", "Control memory write transfer mode",
1791 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1794 RC_FINAL_BOOL( "error_fatal",
1795 "Terminate program if transfer error was found (default: enabled)",
1796 memwrite_error_fatal
)
1799 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1802 RC_FINAL( "mrc", "Read Coprocessor register",
1805 RC_FINAL( "mcr", "Write Coprocessor register",
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