1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
32 #define JTAG_DEBUG(expr ...) DEBUG(expr)
34 #define JTAG_DEBUG(expr ...) do {} while(0)
37 enum tap_state arm11_move_pi_to_si_via_ci
[] =
39 TAP_E2I
, TAP_UI
, TAP_SDS
, TAP_SIS
, TAP_CI
, TAP_SI
43 int arm11_add_ir_scan_vc(int num_fields
, scan_field_t
*fields
, enum tap_state state
)
45 if (cmd_queue_cur_state
== TAP_PI
)
46 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
48 return jtag_add_ir_scan(num_fields
, fields
, state
);
51 enum tap_state arm11_move_pd_to_sd_via_cd
[] =
53 TAP_E2D
, TAP_UD
, TAP_SDS
, TAP_CD
, TAP_SD
56 int arm11_add_dr_scan_vc(int num_fields
, scan_field_t
*fields
, enum tap_state state
)
58 if (cmd_queue_cur_state
== TAP_PD
)
59 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
61 return jtag_add_dr_scan(num_fields
, fields
, state
);
65 /** Code de-clutter: Construct scan_field_t to write out a value
67 * \param arm11 Target state variable.
68 * \param num_bits Length of the data field
69 * \param out_data pointer to the data that will be sent out
70 * <em>(data is read when it is added to the JTAG queue)</em>
71 * \param in_data pointer to the memory that will receive data that was clocked in
72 * <em>(data is written when the JTAG queue is executed)</em>
73 * \param field target data structure that will be initialized
75 void arm11_setup_field(arm11_common_t
* arm11
, int num_bits
, void * out_data
, void * in_data
, scan_field_t
* field
)
77 field
->device
= arm11
->jtag_info
.chain_pos
;
78 field
->num_bits
= num_bits
;
79 field
->out_mask
= NULL
;
80 field
->in_check_mask
= NULL
;
81 field
->in_check_value
= NULL
;
82 field
->in_handler
= NULL
;
83 field
->in_handler_priv
= NULL
;
85 field
->out_value
= out_data
;
86 field
->in_value
= in_data
;
90 /** Write JTAG instruction register
92 * \param arm11 Target state variable.
93 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
94 * \param state Pass the final TAP state or -1 for the default value (Pause-IR).
96 * \remarks This adds to the JTAG command queue but does \em not execute it.
98 void arm11_add_IR(arm11_common_t
* arm11
, u8 instr
, enum tap_state state
)
100 jtag_device_t
*device
= jtag_get_device(arm11
->jtag_info
.chain_pos
);
102 if (buf_get_u32(device
->cur_instr
, 0, 5) == instr
)
104 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
108 JTAG_DEBUG("IR <= 0x%02x", instr
);
112 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
114 arm11_add_ir_scan_vc(1, &field
, state
== -1 ? TAP_PI
: state
);
117 /** Verify shifted out data from Scan Chain Register (SCREG)
118 * Used as parameter to scan_field_t::in_handler in
119 * arm11_add_debug_SCAN_N().
122 static int arm11_in_handler_SCAN_N(u8
*in_value
, void *priv
, struct scan_field_s
*field
)
124 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
125 u8 v
= *in_value
& 0x1F;
129 ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v
);
133 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v
);
137 /** Select and write to Scan Chain Register (SCREG)
139 * This function sets the instruction register to SCAN_N and writes
140 * the data register with the selected chain number.
142 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
144 * \param arm11 Target state variable.
145 * \param chain Scan chain that will be selected.
146 * \param state Pass the final TAP state or -1 for the default
149 * The chain takes effect when Update-DR is passed (usually when subsequently
150 * the INTEXT/EXTEST instructions are written).
152 * \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
153 * in Pause-DR. The second call, due to the IR caching, will not
154 * go through Capture-DR when shifting in the new scan chain number.
155 * As a result the verification in arm11_in_handler_SCAN_N() must
158 * \remarks This adds to the JTAG command queue but does \em not execute it.
161 void arm11_add_debug_SCAN_N(arm11_common_t
* arm11
, u8 chain
, enum tap_state state
)
163 JTAG_DEBUG("SCREG <= 0x%02x", chain
);
165 arm11_add_IR(arm11
, ARM11_SCAN_N
, -1);
169 arm11_setup_field(arm11
, 5, &chain
, NULL
, &field
);
171 field
.in_handler
= arm11_in_handler_SCAN_N
;
173 arm11_add_dr_scan_vc(1, &field
, state
== -1 ? TAP_PD
: state
);
176 /** Write an instruction into the ITR register
178 * \param arm11 Target state variable.
179 * \param inst An ARM11 processor instruction/opcode.
180 * \param flag Optional parameter to retrieve the InstCompl flag
181 * (this will be written when the JTAG chain is executed).
182 * \param state Pass the final TAP state or -1 for the default
183 * value (Run-Test/Idle).
185 * \remarks By default this ends with Run-Test/Idle state
186 * and causes the instruction to be executed. If
187 * a subsequent write to DTR is needed before
188 * executing the instruction then TAP_PD should be
189 * passed to \p state.
191 * \remarks This adds to the JTAG command queue but does \em not execute it.
193 void arm11_add_debug_INST(arm11_common_t
* arm11
, u32 inst
, u8
* flag
, enum tap_state state
)
195 JTAG_DEBUG("INST <= 0x%08x", inst
);
199 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
200 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
202 arm11_add_dr_scan_vc(asizeof(itr
), itr
, state
== -1 ? TAP_RTI
: state
);
205 /** Read the Debug Status and Control Register (DSCR)
209 * \param arm11 Target state variable.
210 * \return DSCR content
212 * \remarks This is a stand-alone function that executes the JTAG command queue.
214 u32
arm11_read_DSCR(arm11_common_t
* arm11
)
216 arm11_add_debug_SCAN_N(arm11
, 0x01, -1);
218 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
221 scan_field_t chain1_field
;
223 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
225 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_PD
);
227 jtag_execute_queue();
229 if (arm11
->last_dscr
!= dscr
)
230 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
232 arm11
->last_dscr
= dscr
;
237 /** Write the Debug Status and Control Register (DSCR)
241 * \param arm11 Target state variable.
242 * \param dscr DSCR content
244 * \remarks This is a stand-alone function that executes the JTAG command queue.
246 void arm11_write_DSCR(arm11_common_t
* arm11
, u32 dscr
)
248 arm11_add_debug_SCAN_N(arm11
, 0x01, -1);
250 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
252 scan_field_t chain1_field
;
254 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
256 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_PD
);
258 jtag_execute_queue();
260 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
262 arm11
->last_dscr
= dscr
;
267 /** Get the debug reason from Debug Status and Control Register (DSCR)
269 * \param dscr DSCR value to analyze
270 * \return Debug reason
273 enum target_debug_reason
arm11_get_DSCR_debug_reason(u32 dscr
)
275 switch (dscr
& ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
)
277 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
:
278 INFO("Debug entry: JTAG HALT");
279 return DBG_REASON_DBGRQ
;
281 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
:
282 INFO("Debug entry: breakpoint");
283 return DBG_REASON_BREAKPOINT
;
285 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
:
286 INFO("Debug entry: watchpoint");
287 return DBG_REASON_WATCHPOINT
;
289 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
:
290 INFO("Debug entry: BKPT instruction");
291 return DBG_REASON_BREAKPOINT
;
293 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
:
294 INFO("Debug entry: EDBGRQ signal");
295 return DBG_REASON_DBGRQ
;
297 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
:
298 INFO("Debug entry: VCR vector catch");
299 return DBG_REASON_BREAKPOINT
;
302 INFO("Debug entry: unknown");
303 return DBG_REASON_DBGRQ
;
309 /** Prepare the stage for ITR/DTR operations
310 * from the arm11_run_instr... group of functions.
312 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
313 * around a block of arm11_run_instr_... calls.
315 * Select scan chain 5 to allow quick access to DTR. When scan
316 * chain 4 is needed to put in a register the ITRSel instruction
317 * shortcut is used instead of actually changing the Scan_N
320 * \param arm11 Target state variable.
323 void arm11_run_instr_data_prepare(arm11_common_t
* arm11
)
325 arm11_add_debug_SCAN_N(arm11
, 0x05, -1);
328 /** Cleanup after ITR/DTR operations
329 * from the arm11_run_instr... group of functions
331 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
332 * around a block of arm11_run_instr_... calls.
334 * Any RTI can lead to an instruction execution when
335 * scan chains 4 or 5 are selected and the IR holds
336 * INTEST or EXTEST. So we must disable that before
337 * any following activities lead to an RTI.
339 * \param arm11 Target state variable.
342 void arm11_run_instr_data_finish(arm11_common_t
* arm11
)
344 arm11_add_debug_SCAN_N(arm11
, 0x00, -1);
348 /** Execute one or multiple instructions via ITR
350 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
352 * \param arm11 Target state variable.
353 * \param opcode Pointer to sequence of ARM opcodes
354 * \param count Number of opcodes to execute
357 void arm11_run_instr_no_data(arm11_common_t
* arm11
, u32
* opcode
, size_t count
)
359 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
363 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_RTI
);
369 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_RTI
: TAP_PD
);
371 jtag_execute_queue();
379 /** Execute one instruction via ITR
381 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
383 * \param arm11 Target state variable.
384 * \param opcode ARM opcode
387 void arm11_run_instr_no_data1(arm11_common_t
* arm11
, u32 opcode
)
389 arm11_run_instr_no_data(arm11
, &opcode
, 1);
393 /** Execute one instruction via ITR repeatedly while
394 * passing data to the core via DTR on each execution.
396 * The executed instruction \em must read data from DTR.
398 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
400 * \param arm11 Target state variable.
401 * \param opcode ARM opcode
402 * \param data Pointer to the data words to be passed to the core
403 * \param count Number of data words and instruction repetitions
406 void arm11_run_instr_data_to_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
408 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
410 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_PD
);
412 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
414 scan_field_t chain5_fields
[3];
420 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
421 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
422 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
430 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_RTI
);
431 jtag_execute_queue();
433 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
440 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
446 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
447 jtag_execute_queue();
449 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
454 /** JTAG path for arm11_run_instr_data_to_core_noack
456 * The repeated TAP_RTI's do not cause a repeated execution
457 * if passed without leaving the state.
459 * Since this is more than 7 bits (adjustable via adding more
460 * TAP_RTI's) it produces an artificial delay in the lower
461 * layer (FT2232) that is long enough to finish execution on
462 * the core but still shorter than any manually inducible delays.
465 enum tap_state arm11_MOVE_PD_RTI_PD_with_delay
[] =
467 TAP_E2D
, TAP_UD
, TAP_RTI
, TAP_RTI
, TAP_RTI
, TAP_SDS
, TAP_CD
, TAP_SD
472 /** Execute one instruction via ITR repeatedly while
473 * passing data to the core via DTR on each execution.
475 * No Ready check during transmission.
477 * The executed instruction \em must read data from DTR.
479 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
481 * \param arm11 Target state variable.
482 * \param opcode ARM opcode
483 * \param data Pointer to the data words to be passed to the core
484 * \param count Number of data words and instruction repetitions
487 void arm11_run_instr_data_to_core_noack(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
489 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
491 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_PD
);
493 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
495 scan_field_t chain5_fields
[3];
497 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
498 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
499 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
501 u8 Readies
[count
+ 1];
502 u8
* ReadyPos
= Readies
;
506 chain5_fields
[0].out_value
= (void *)(data
++);
507 chain5_fields
[1].in_value
= ReadyPos
++;
511 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
512 jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay
),
513 arm11_MOVE_PD_RTI_PD_with_delay
);
517 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_RTI
);
521 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
523 chain5_fields
[0].out_value
= 0;
524 chain5_fields
[1].in_value
= ReadyPos
++;
526 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
528 jtag_execute_queue();
530 size_t error_count
= 0;
533 for (i
= 0; i
< asizeof(Readies
); i
++)
542 ERROR("Transfer errors " ZU
, error_count
);
546 /** Execute an instruction via ITR while handing data into the core via DTR.
548 * The executed instruction \em must read data from DTR.
550 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
552 * \param arm11 Target state variable.
553 * \param opcode ARM opcode
554 * \param data Data word to be passed to the core via DTR
557 void arm11_run_instr_data_to_core1(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
559 arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
563 /** Execute one instruction via ITR repeatedly while
564 * reading data from the core via DTR on each execution.
566 * The executed instruction \em must write data to DTR.
568 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
570 * \param arm11 Target state variable.
571 * \param opcode ARM opcode
572 * \param data Pointer to an array that receives the data words from the core
573 * \param count Number of data words and instruction repetitions
576 void arm11_run_instr_data_from_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
578 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
580 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_RTI
);
582 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
584 scan_field_t chain5_fields
[3];
590 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
591 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
592 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
598 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, count
? TAP_RTI
: TAP_PD
);
599 jtag_execute_queue();
601 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
609 /** Execute one instruction via ITR
610 * then load r0 into DTR and read DTR from core.
612 * The first executed instruction (\p opcode) should write data to r0.
614 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
616 * \param arm11 Target state variable.
617 * \param opcode ARM opcode to write r0 with the value of interest
618 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
621 void arm11_run_instr_data_from_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32
* data
)
623 arm11_run_instr_no_data1(arm11
, opcode
);
625 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
626 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
629 /** Load data into core via DTR then move it to r0 then
630 * execute one instruction via ITR
632 * The final executed instruction (\p opcode) should read data from r0.
634 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
636 * \param arm11 Target state variable.
637 * \param opcode ARM opcode to read r0 act upon it
638 * \param data Data word that will be written to r0 before \p opcode is executed
641 void arm11_run_instr_data_to_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
643 /* MRC p14,0,r0,c0,c5,0 */
644 arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
646 arm11_run_instr_no_data1(arm11
, opcode
);
649 /** Apply reads and writes to scan chain 7
651 * \see arm11_sc7_action_t
653 * \param arm11 Target state variable.
654 * \param actions A list of read and/or write instructions
655 * \param count Number of instructions in the list.
658 void arm11_sc7_run(arm11_common_t
* arm11
, arm11_sc7_action_t
* actions
, size_t count
)
660 arm11_add_debug_SCAN_N(arm11
, 0x07, -1);
662 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
664 scan_field_t chain7_fields
[3];
673 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
674 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
675 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
678 for (i
= 0; i
< count
+ 1; i
++)
682 nRW
= actions
[i
].write
? 1 : 0;
683 DataOut
= actions
[i
].value
;
684 AddressOut
= actions
[i
].address
;
695 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut
, DataOut
, nRW
);
697 arm11_add_dr_scan_vc(asizeof(chain7_fields
), chain7_fields
, TAP_PD
);
698 jtag_execute_queue();
700 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn
, DataIn
, Ready
);
702 while (!Ready
); /* 'nRW' is 'Ready' on read out */
706 if (actions
[i
- 1].address
!= AddressIn
)
708 WARNING("Scan chain 7 shifted out unexpected address");
711 if (!actions
[i
- 1].write
)
713 actions
[i
- 1].value
= DataIn
;
717 if (actions
[i
- 1].value
!= DataIn
)
719 WARNING("Scan chain 7 shifted out unexpected data");
726 for (i
= 0; i
< count
; i
++)
728 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i
, actions
[i
].address
, actions
[i
].write
? "<=" : "=>", actions
[i
].value
);
732 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
734 * \param arm11 Target state variable.
737 void arm11_sc7_clear_vbw(arm11_common_t
* arm11
)
739 arm11_sc7_action_t clear_bw
[arm11
->brp
+ arm11
->wrp
+ 1];
740 arm11_sc7_action_t
* pos
= clear_bw
;
743 for (i
= 0; i
< asizeof(clear_bw
); i
++)
745 clear_bw
[i
].write
= true;
746 clear_bw
[i
].value
= 0;
750 for (i
= 0; i
< arm11
->brp
; i
++)
751 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
755 for (i
= 0; i
< arm11
->wrp
; i
++)
756 (pos
++)->address
= ARM11_SC7_WCR0
+ i
;
759 (pos
++)->address
= ARM11_SC7_VCR
;
761 arm11_sc7_run(arm11
, clear_bw
, asizeof(clear_bw
));
764 /** Write VCR register
766 * \param arm11 Target state variable.
767 * \param value Value to be written
769 void arm11_sc7_set_vcr(arm11_common_t
* arm11
, u32 value
)
771 arm11_sc7_action_t set_vcr
;
773 set_vcr
.write
= true;
774 set_vcr
.address
= ARM11_SC7_VCR
;
775 set_vcr
.value
= value
;
778 arm11_sc7_run(arm11
, &set_vcr
, 1);
783 /** Read word from address
785 * \param arm11 Target state variable.
786 * \param address Memory address to be read
787 * \param result Pointer where to store result
790 void arm11_read_memory_word(arm11_common_t
* arm11
, u32 address
, u32
* result
)
792 arm11_run_instr_data_prepare(arm11
);
794 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
795 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
797 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
798 arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1);
800 arm11_run_instr_data_finish(arm11
);
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