1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "arm11_dbgtap.h"
30 #include <helper/time_support.h>
33 #define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0)
35 #define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0)
39 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
40 behavior of the FTDI driver IIRC was to go via RTI.
42 Conversely there may be other places in this code where the ARM11 code relies
43 on the driver to hit through RTI when coming from Update-?R.
45 static const tap_state_t arm11_move_pi_to_si_via_ci
[] =
47 TAP_IREXIT2
, TAP_IRUPDATE
, TAP_DRSELECT
, TAP_IRSELECT
, TAP_IRCAPTURE
, TAP_IRSHIFT
51 static int arm11_add_ir_scan_vc(int num_fields
, struct scan_field
*fields
,
54 if (cmd_queue_cur_state
== TAP_IRPAUSE
)
55 jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
57 jtag_add_ir_scan(num_fields
, fields
, state
);
61 static const tap_state_t arm11_move_pd_to_sd_via_cd
[] =
63 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
66 int arm11_add_dr_scan_vc(int num_fields
, struct scan_field
*fields
, tap_state_t state
)
68 if (cmd_queue_cur_state
== TAP_DRPAUSE
)
69 jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
71 jtag_add_dr_scan(num_fields
, fields
, state
);
76 /** Code de-clutter: Construct struct scan_field to write out a value
78 * \param arm11 Target state variable.
79 * \param num_bits Length of the data field
80 * \param out_data pointer to the data that will be sent out
81 * <em > (data is read when it is added to the JTAG queue)</em>
82 * \param in_data pointer to the memory that will receive data that was clocked in
83 * <em > (data is written when the JTAG queue is executed)</em>
84 * \param field target data structure that will be initialized
86 void arm11_setup_field(struct arm11_common
* arm11
, int num_bits
, void * out_data
, void * in_data
, struct scan_field
* field
)
88 field
->tap
= arm11
->arm
.target
->tap
;
89 field
->num_bits
= num_bits
;
90 field
->out_value
= out_data
;
91 field
->in_value
= in_data
;
95 /** Write JTAG instruction register
97 * \param arm11 Target state variable.
98 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
99 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
101 * \remarks This adds to the JTAG command queue but does \em not execute it.
103 void arm11_add_IR(struct arm11_common
* arm11
, uint8_t instr
, tap_state_t state
)
105 struct jtag_tap
*tap
= arm11
->arm
.target
->tap
;
107 if (buf_get_u32(tap
->cur_instr
, 0, 5) == instr
)
109 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
113 JTAG_DEBUG("IR <= 0x%02x", instr
);
115 struct scan_field field
;
117 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
119 arm11_add_ir_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_IRPAUSE
: state
);
122 /** Verify shifted out data from Scan Chain Register (SCREG)
123 * Used as parameter to struct scan_field::in_handler in
124 * arm11_add_debug_SCAN_N().
127 static void arm11_in_handler_SCAN_N(uint8_t *in_value
)
129 /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */
130 uint8_t v
= *in_value
& 0x1F;
134 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v
);
135 jtag_set_error(ERROR_FAIL
);
138 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v
);
141 /** Select and write to Scan Chain Register (SCREG)
143 * This function sets the instruction register to SCAN_N and writes
144 * the data register with the selected chain number.
146 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
148 * \param arm11 Target state variable.
149 * \param chain Scan chain that will be selected.
150 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
153 * The chain takes effect when Update-DR is passed (usually when subsequently
154 * the INTEXT/EXTEST instructions are written).
156 * \warning (Obsolete) Using this twice in a row will \em fail. The first
157 * call will end in Pause-DR. The second call, due to the IR
158 * caching, will not go through Capture-DR when shifting in the
159 * new scan chain number. As a result the verification in
160 * arm11_in_handler_SCAN_N() must fail.
162 * \remarks This adds to the JTAG command queue but does \em not execute it.
165 int arm11_add_debug_SCAN_N(struct arm11_common
* arm11
, uint8_t chain
, tap_state_t state
)
167 JTAG_DEBUG("SCREG <= 0x%02x", chain
);
169 arm11_add_IR(arm11
, ARM11_SCAN_N
, ARM11_TAP_DEFAULT
);
171 struct scan_field field
;
174 arm11_setup_field(arm11
, 5, &chain
, &tmp
, &field
);
176 arm11_add_dr_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_DRPAUSE
: state
);
178 jtag_execute_queue_noclear();
180 arm11_in_handler_SCAN_N(tmp
);
182 arm11
->jtag_info
.cur_scan_chain
= chain
;
184 return jtag_execute_queue();
187 /** Write an instruction into the ITR register
189 * \param arm11 Target state variable.
190 * \param inst An ARM11 processor instruction/opcode.
191 * \param flag Optional parameter to retrieve the InstCompl flag
192 * (this will be written when the JTAG chain is executed).
193 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
194 * value (Run-Test/Idle).
196 * \remarks By default this ends with Run-Test/Idle state
197 * and causes the instruction to be executed. If
198 * a subsequent write to DTR is needed before
199 * executing the instruction then TAP_DRPAUSE should be
200 * passed to \p state.
202 * \remarks This adds to the JTAG command queue but does \em not execute it.
204 static void arm11_add_debug_INST(struct arm11_common
* arm11
,
205 uint32_t inst
, uint8_t * flag
, tap_state_t state
)
207 JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst
);
209 struct scan_field itr
[2];
211 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
212 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
214 arm11_add_dr_scan_vc(ARRAY_SIZE(itr
), itr
, state
== ARM11_TAP_DEFAULT
? TAP_IDLE
: state
);
218 * Read and save the Debug Status and Control Register (DSCR).
220 * \param arm11 Target state variable.
221 * \return Error status; arm11->dscr is updated on success.
223 * \remarks This is a stand-alone function that executes the JTAG
224 * command queue. It does not require the ARM11 debug TAP to be
225 * in any particular state.
227 int arm11_read_DSCR(struct arm11_common
*arm11
)
231 retval
= arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
232 if (retval
!= ERROR_OK
)
235 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
238 struct scan_field chain1_field
;
240 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
242 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
244 CHECK_RETVAL(jtag_execute_queue());
246 if (arm11
->dscr
!= dscr
)
247 JTAG_DEBUG("DSCR = %08x (OLD %08x)",
249 (unsigned) arm11
->dscr
);
256 /** Write the Debug Status and Control Register (DSCR)
260 * \param arm11 Target state variable.
261 * \param dscr DSCR content
263 * \remarks This is a stand-alone function that executes the JTAG command queue.
265 int arm11_write_DSCR(struct arm11_common
* arm11
, uint32_t dscr
)
268 retval
= arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
269 if (retval
!= ERROR_OK
)
272 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
274 struct scan_field chain1_field
;
276 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
278 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
280 CHECK_RETVAL(jtag_execute_queue());
282 JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
284 (unsigned) arm11
->dscr
);
291 /** Prepare the stage for ITR/DTR operations
292 * from the arm11_run_instr... group of functions.
294 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
295 * around a block of arm11_run_instr_... calls.
297 * Select scan chain 5 to allow quick access to DTR. When scan
298 * chain 4 is needed to put in a register the ITRSel instruction
299 * shortcut is used instead of actually changing the Scan_N
302 * \param arm11 Target state variable.
305 int arm11_run_instr_data_prepare(struct arm11_common
* arm11
)
307 return arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
310 /** Cleanup after ITR/DTR operations
311 * from the arm11_run_instr... group of functions
313 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
314 * around a block of arm11_run_instr_... calls.
316 * Any IDLE can lead to an instruction execution when
317 * scan chains 4 or 5 are selected and the IR holds
318 * INTEST or EXTEST. So we must disable that before
319 * any following activities lead to an IDLE.
321 * \param arm11 Target state variable.
324 int arm11_run_instr_data_finish(struct arm11_common
* arm11
)
326 return arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
331 /** Execute one or multiple instructions via ITR
333 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
335 * \param arm11 Target state variable.
336 * \param opcode Pointer to sequence of ARM opcodes
337 * \param count Number of opcodes to execute
341 int arm11_run_instr_no_data(struct arm11_common
* arm11
,
342 uint32_t * opcode
, size_t count
)
344 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
348 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_IDLE
);
355 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_IDLE
: TAP_DRPAUSE
);
357 CHECK_RETVAL(jtag_execute_queue());
370 if ((timeval_ms()-then
) > 1000)
372 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
384 /** Execute one instruction via ITR
386 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
388 * \param arm11 Target state variable.
389 * \param opcode ARM opcode
392 int arm11_run_instr_no_data1(struct arm11_common
* arm11
, uint32_t opcode
)
394 return arm11_run_instr_no_data(arm11
, &opcode
, 1);
398 /** Execute one instruction via ITR repeatedly while
399 * passing data to the core via DTR on each execution.
401 * The executed instruction \em must read data from DTR.
403 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
405 * \param arm11 Target state variable.
406 * \param opcode ARM opcode
407 * \param data Pointer to the data words to be passed to the core
408 * \param count Number of data words and instruction repetitions
411 int arm11_run_instr_data_to_core(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
413 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
415 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
417 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
419 struct scan_field chain5_fields
[3];
425 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
426 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
427 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
436 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_IDLE
));
438 CHECK_RETVAL(jtag_execute_queue());
440 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
450 if ((timeval_ms()-then
) > 1000)
452 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
464 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
471 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
473 CHECK_RETVAL(jtag_execute_queue());
475 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
476 (unsigned) Data
, Ready
, nRetry
);
486 if ((timeval_ms()-then
) > 1000)
488 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
500 /** JTAG path for arm11_run_instr_data_to_core_noack
502 * The repeated TAP_IDLE's do not cause a repeated execution
503 * if passed without leaving the state.
505 * Since this is more than 7 bits (adjustable via adding more
506 * TAP_IDLE's) it produces an artificial delay in the lower
507 * layer (FT2232) that is long enough to finish execution on
508 * the core but still shorter than any manually inducible delays.
510 * To disable this code, try "memwrite burst false"
512 * FIX!!! should we use multiple TAP_IDLE here or not???
514 * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
515 * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
517 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
[] =
519 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_IDLE
, TAP_IDLE
, TAP_IDLE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
524 /** Execute one instruction via ITR repeatedly while
525 * passing data to the core via DTR on each execution.
527 * No Ready check during transmission.
529 * The executed instruction \em must read data from DTR.
531 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
533 * \param arm11 Target state variable.
534 * \param opcode ARM opcode
535 * \param data Pointer to the data words to be passed to the core
536 * \param count Number of data words and instruction repetitions
539 int arm11_run_instr_data_to_core_noack(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
541 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
543 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
545 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
547 struct scan_field chain5_fields
[3];
549 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
550 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
551 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
554 unsigned readiesNum
= count
+ 1;
555 unsigned bytes
= sizeof(*Readies
)*readiesNum
;
557 Readies
= (uint8_t *) malloc(bytes
);
560 LOG_ERROR("Out of memory allocating %u bytes", bytes
);
564 uint8_t * ReadyPos
= Readies
;
568 chain5_fields
[0].out_value
= (void *)(data
++);
569 chain5_fields
[1].in_value
= ReadyPos
++;
573 jtag_add_dr_scan(ARRAY_SIZE(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_DRPAUSE
));
574 jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
),
575 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
);
579 jtag_add_dr_scan(ARRAY_SIZE(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_IDLE
));
583 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
585 chain5_fields
[0].out_value
= 0;
586 chain5_fields
[1].in_value
= ReadyPos
++;
588 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
590 int retval
= jtag_execute_queue();
591 if (retval
== ERROR_OK
)
593 unsigned error_count
= 0;
595 for (size_t i
= 0; i
< readiesNum
; i
++)
603 if (error_count
> 0 )
604 LOG_ERROR("%u words out of %u not transferred",
605 error_count
, readiesNum
);
615 /** Execute an instruction via ITR while handing data into the core via DTR.
617 * The executed instruction \em must read data from DTR.
619 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
621 * \param arm11 Target state variable.
622 * \param opcode ARM opcode
623 * \param data Data word to be passed to the core via DTR
626 int arm11_run_instr_data_to_core1(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t data
)
628 return arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
632 /** Execute one instruction via ITR repeatedly while
633 * reading data from the core via DTR on each execution.
635 * The executed instruction \em must write data to DTR.
637 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
639 * \param arm11 Target state variable.
640 * \param opcode ARM opcode
641 * \param data Pointer to an array that receives the data words from the core
642 * \param count Number of data words and instruction repetitions
645 int arm11_run_instr_data_from_core(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
647 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
649 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_IDLE
);
651 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
653 struct scan_field chain5_fields
[3];
659 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
660 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
661 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
668 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, count
? TAP_IDLE
: TAP_DRPAUSE
);
670 CHECK_RETVAL(jtag_execute_queue());
672 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
673 (unsigned) Data
, Ready
, nRetry
);
683 if ((timeval_ms()-then
) > 1000)
685 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
700 /** Execute one instruction via ITR
701 * then load r0 into DTR and read DTR from core.
703 * The first executed instruction (\p opcode) should write data to r0.
705 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
707 * \param arm11 Target state variable.
708 * \param opcode ARM opcode to write r0 with the value of interest
709 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
712 int arm11_run_instr_data_from_core_via_r0(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
)
715 retval
= arm11_run_instr_no_data1(arm11
, opcode
);
716 if (retval
!= ERROR_OK
)
719 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
720 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
725 /** Load data into core via DTR then move it to r0 then
726 * execute one instruction via ITR
728 * The final executed instruction (\p opcode) should read data from r0.
730 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
732 * \param arm11 Target state variable.
733 * \param opcode ARM opcode to read r0 act upon it
734 * \param data Data word that will be written to r0 before \p opcode is executed
737 int arm11_run_instr_data_to_core_via_r0(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t data
)
740 /* MRC p14,0,r0,c0,c5,0 */
741 retval
= arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
742 if (retval
!= ERROR_OK
)
745 retval
= arm11_run_instr_no_data1(arm11
, opcode
);
746 if (retval
!= ERROR_OK
)
752 /** Apply reads and writes to scan chain 7
754 * \see struct arm11_sc7_action
756 * \param arm11 Target state variable.
757 * \param actions A list of read and/or write instructions
758 * \param count Number of instructions in the list.
761 int arm11_sc7_run(struct arm11_common
* arm11
, struct arm11_sc7_action
* actions
, size_t count
)
765 retval
= arm11_add_debug_SCAN_N(arm11
, 0x07, ARM11_TAP_DEFAULT
);
766 if (retval
!= ERROR_OK
)
769 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
771 struct scan_field chain7_fields
[3];
780 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
781 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
782 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
784 for (size_t i
= 0; i
< count
+ 1; i
++)
788 nRW
= actions
[i
].write
? 1 : 0;
789 DataOut
= actions
[i
].value
;
790 AddressOut
= actions
[i
].address
;
801 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d",
802 (unsigned) AddressOut
,
806 arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields
),
807 chain7_fields
, TAP_DRPAUSE
);
809 CHECK_RETVAL(jtag_execute_queue());
811 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d",
812 (unsigned) AddressIn
,
816 while (!Ready
); /* 'nRW' is 'Ready' on read out */
820 if (actions
[i
- 1].address
!= AddressIn
)
822 LOG_WARNING("Scan chain 7 shifted out unexpected address");
825 if (!actions
[i
- 1].write
)
827 actions
[i
- 1].value
= DataIn
;
831 if (actions
[i
- 1].value
!= DataIn
)
833 LOG_WARNING("Scan chain 7 shifted out unexpected data");
839 for (size_t i
= 0; i
< count
; i
++)
841 JTAG_DEBUG("SC7 %02d: %02x %s %08x",
842 (unsigned) i
, actions
[i
].address
,
843 actions
[i
].write
? "<=" : "=>",
844 (unsigned) actions
[i
].value
);
850 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
852 * \param arm11 Target state variable.
855 void arm11_sc7_clear_vbw(struct arm11_common
* arm11
)
857 size_t clear_bw_size
= arm11
->brp
+ arm11
->wrp
+ 1;
858 struct arm11_sc7_action
*clear_bw
= malloc(sizeof(struct arm11_sc7_action
) * clear_bw_size
);
859 struct arm11_sc7_action
* pos
= clear_bw
;
861 for (size_t i
= 0; i
< clear_bw_size
; i
++)
863 clear_bw
[i
].write
= true;
864 clear_bw
[i
].value
= 0;
867 for (size_t i
= 0; i
< arm11
->brp
; i
++)
868 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
871 for (size_t i
= 0; i
< arm11
->wrp
; i
++)
872 (pos
++)->address
= ARM11_SC7_WCR0
+ i
;
875 (pos
++)->address
= ARM11_SC7_VCR
;
877 arm11_sc7_run(arm11
, clear_bw
, clear_bw_size
);
882 /** Write VCR register
884 * \param arm11 Target state variable.
885 * \param value Value to be written
887 void arm11_sc7_set_vcr(struct arm11_common
* arm11
, uint32_t value
)
889 struct arm11_sc7_action set_vcr
;
891 set_vcr
.write
= true;
892 set_vcr
.address
= ARM11_SC7_VCR
;
893 set_vcr
.value
= value
;
896 arm11_sc7_run(arm11
, &set_vcr
, 1);
901 /** Read word from address
903 * \param arm11 Target state variable.
904 * \param address Memory address to be read
905 * \param result Pointer where to store result
908 int arm11_read_memory_word(struct arm11_common
* arm11
, uint32_t address
, uint32_t * result
)
911 retval
= arm11_run_instr_data_prepare(arm11
);
912 if (retval
!= ERROR_OK
)
915 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
916 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
));
918 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
919 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1));
921 return arm11_run_instr_data_finish(arm11
);
925 /************************************************************************/
928 * ARM11 provider for the OpenOCD implementation of the standard
929 * architectural ARM v6/v7 "Debug Programmer's Model" (DPM).
932 static inline struct arm11_common
*dpm_to_arm11(struct arm_dpm
*dpm
)
934 return container_of(dpm
, struct arm11_common
, dpm
);
937 static int arm11_dpm_prepare(struct arm_dpm
*dpm
)
939 struct arm11_common
*arm11
= dpm_to_arm11(dpm
);
941 arm11
= container_of(dpm
->arm
, struct arm11_common
, arm
);
943 return arm11_run_instr_data_prepare(dpm_to_arm11(dpm
));
946 static int arm11_dpm_finish(struct arm_dpm
*dpm
)
948 return arm11_run_instr_data_finish(dpm_to_arm11(dpm
));
951 static int arm11_dpm_instr_write_data_dcc(struct arm_dpm
*dpm
,
952 uint32_t opcode
, uint32_t data
)
954 return arm11_run_instr_data_to_core(dpm_to_arm11(dpm
),
958 static int arm11_dpm_instr_write_data_r0(struct arm_dpm
*dpm
,
959 uint32_t opcode
, uint32_t data
)
961 return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm
),
965 static int arm11_dpm_instr_read_data_dcc(struct arm_dpm
*dpm
,
966 uint32_t opcode
, uint32_t *data
)
968 return arm11_run_instr_data_from_core(dpm_to_arm11(dpm
),
972 static int arm11_dpm_instr_read_data_r0(struct arm_dpm
*dpm
,
973 uint32_t opcode
, uint32_t *data
)
975 return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm
),
979 /** Set up high-level debug module utilities */
980 int arm11_dpm_init(struct arm11_common
*arm11
, uint32_t didr
)
982 struct arm_dpm
*dpm
= &arm11
->dpm
;
985 dpm
->arm
= &arm11
->arm
;
989 dpm
->prepare
= arm11_dpm_prepare
;
990 dpm
->finish
= arm11_dpm_finish
;
992 dpm
->instr_write_data_dcc
= arm11_dpm_instr_write_data_dcc
;
993 dpm
->instr_write_data_r0
= arm11_dpm_instr_write_data_r0
;
995 dpm
->instr_read_data_dcc
= arm11_dpm_instr_read_data_dcc
;
996 dpm
->instr_read_data_r0
= arm11_dpm_instr_read_data_r0
;
998 retval
= arm_dpm_setup(dpm
);
999 if (retval
!= ERROR_OK
)
1002 retval
= arm_dpm_initialize(dpm
);
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