1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
29 #include <helper/time_support.h>
30 #include "target_type.h"
32 #include "arm_opcodes.h"
36 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
37 * ARM DDI 0229C especially Chapter 9 about debug support.
41 #define _DEBUG_INSTRUCTION_EXECUTION_
44 static int arm720t_scan_cp15(struct target
*target
,
45 uint32_t out
, uint32_t *in
, int instruction
, int clock_arg
)
48 struct arm720t_common
*arm720t
= target_to_arm720(target
);
49 struct arm_jtag
*jtag_info
;
50 struct scan_field fields
[2];
52 uint8_t instruction_buf
= instruction
;
54 jtag_info
= &arm720t
->arm7_9_common
.jtag_info
;
56 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
58 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_DRPAUSE
);
59 if (retval
!= ERROR_OK
)
61 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_DRPAUSE
);
62 if (retval
!= ERROR_OK
)
65 fields
[0].num_bits
= 1;
66 fields
[0].out_value
= &instruction_buf
;
67 fields
[0].in_value
= NULL
;
69 fields
[1].num_bits
= 32;
70 fields
[1].out_value
= out_buf
;
71 fields
[1].in_value
= NULL
;
74 fields
[1].in_value
= (uint8_t *)in
;
75 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
76 jtag_add_callback(arm7flip32
, (jtag_callback_data_t
)in
);
78 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
81 jtag_add_runtest(0, TAP_DRPAUSE
);
83 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
84 retval
= jtag_execute_queue();
85 if (retval
!= ERROR_OK
)
89 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
91 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock_arg
);
93 LOG_DEBUG("out: %8.8" PRIx32
", instruction: %i, clock: %i", out
, instruction
, clock_arg
);
99 static int arm720t_read_cp15(struct target
*target
, uint32_t opcode
, uint32_t *value
)
101 /* fetch CP15 opcode */
102 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
104 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
105 /* "EXECUTE" stage (1) */
106 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
107 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
108 /* "EXECUTE" stage (2) */
109 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
110 /* "EXECUTE" stage (3), CDATA is read */
111 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
116 static int arm720t_write_cp15(struct target
*target
, uint32_t opcode
, uint32_t value
)
118 /* fetch CP15 opcode */
119 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
121 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
122 /* "EXECUTE" stage (1) */
123 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
124 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
125 /* "EXECUTE" stage (2) */
126 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
127 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
132 static int arm720t_get_ttb(struct target
*target
, uint32_t *result
)
138 retval
= arm720t_read_cp15(target
, 0xee120f10, &ttb
);
139 if (retval
!= ERROR_OK
)
141 retval
= jtag_execute_queue();
142 if (retval
!= ERROR_OK
)
152 static int arm720t_disable_mmu_caches(struct target
*target
,
153 int mmu
, int d_u_cache
, int i_cache
)
155 uint32_t cp15_control
;
158 /* read cp15 control register */
159 retval
= arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
160 if (retval
!= ERROR_OK
)
162 retval
= jtag_execute_queue();
163 if (retval
!= ERROR_OK
)
167 cp15_control
&= ~0x1U
;
169 if (d_u_cache
|| i_cache
)
170 cp15_control
&= ~0x4U
;
172 retval
= arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
176 static int arm720t_enable_mmu_caches(struct target
*target
,
177 int mmu
, int d_u_cache
, int i_cache
)
179 uint32_t cp15_control
;
182 /* read cp15 control register */
183 retval
= arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
184 if (retval
!= ERROR_OK
)
186 retval
= jtag_execute_queue();
187 if (retval
!= ERROR_OK
)
191 cp15_control
|= 0x1U
;
193 if (d_u_cache
|| i_cache
)
194 cp15_control
|= 0x4U
;
196 retval
= arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
200 static int arm720t_post_debug_entry(struct target
*target
)
202 struct arm720t_common
*arm720t
= target_to_arm720(target
);
205 /* examine cp15 control reg */
206 retval
= arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
207 if (retval
!= ERROR_OK
)
209 retval
= jtag_execute_queue();
210 if (retval
!= ERROR_OK
)
212 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm720t
->cp15_control_reg
);
214 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
215 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
216 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
218 /* save i/d fault status and address register */
219 retval
= arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
220 if (retval
!= ERROR_OK
)
222 retval
= arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
223 if (retval
!= ERROR_OK
)
225 retval
= jtag_execute_queue();
229 static void arm720t_pre_restore_context(struct target
*target
)
231 struct arm720t_common
*arm720t
= target_to_arm720(target
);
233 /* restore i/d fault status and address register */
234 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
235 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
238 static int arm720t_verify_pointer(struct command_context
*cmd_ctx
,
239 struct arm720t_common
*arm720t
)
241 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
) {
242 command_print(cmd_ctx
, "target is not an ARM720");
243 return ERROR_TARGET_INVALID
;
248 static int arm720t_arch_state(struct target
*target
)
250 struct arm720t_common
*arm720t
= target_to_arm720(target
);
252 static const char *state
[] = {
253 "disabled", "enabled"
256 arm_arch_state(target
);
257 LOG_USER("MMU: %s, Cache: %s",
258 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
259 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
264 static int arm720_mmu(struct target
*target
, int *enabled
)
266 if (target
->state
!= TARGET_HALTED
) {
267 LOG_ERROR("%s: target not halted", __func__
);
268 return ERROR_TARGET_INVALID
;
271 *enabled
= target_to_arm720(target
)->armv4_5_mmu
.mmu_enabled
;
275 static int arm720_virt2phys(struct target
*target
,
276 uint32_t virtual, uint32_t *physical
)
279 struct arm720t_common
*arm720t
= target_to_arm720(target
);
282 int retval
= armv4_5_mmu_translate_va(target
,
283 &arm720t
->armv4_5_mmu
, virtual, &cb
, &ret
);
284 if (retval
!= ERROR_OK
)
290 static int arm720t_read_memory(struct target
*target
,
291 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
294 struct arm720t_common
*arm720t
= target_to_arm720(target
);
296 /* disable cache, but leave MMU enabled */
297 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
298 retval
= arm720t_disable_mmu_caches(target
, 0, 1, 0);
299 if (retval
!= ERROR_OK
)
302 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
304 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
305 retval
= arm720t_enable_mmu_caches(target
, 0, 1, 0);
306 if (retval
!= ERROR_OK
)
313 static int arm720t_read_phys_memory(struct target
*target
,
314 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
316 struct arm720t_common
*arm720t
= target_to_arm720(target
);
318 return armv4_5_mmu_read_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
321 static int arm720t_write_phys_memory(struct target
*target
,
322 uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t *buffer
)
324 struct arm720t_common
*arm720t
= target_to_arm720(target
);
326 return armv4_5_mmu_write_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
329 static int arm720t_soft_reset_halt(struct target
*target
)
331 int retval
= ERROR_OK
;
332 struct arm720t_common
*arm720t
= target_to_arm720(target
);
333 struct reg
*dbg_stat
= &arm720t
->arm7_9_common
334 .eice_cache
->reg_list
[EICE_DBG_STAT
];
335 struct arm
*arm
= &arm720t
->arm7_9_common
.arm
;
337 retval
= target_halt(target
);
338 if (retval
!= ERROR_OK
)
341 long long then
= timeval_ms();
343 while (!(timeout
= ((timeval_ms()-then
) > 1000))) {
344 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0) {
345 embeddedice_read_reg(dbg_stat
);
346 retval
= jtag_execute_queue();
347 if (retval
!= ERROR_OK
)
351 if (debug_level
>= 3)
357 LOG_ERROR("Failed to halt CPU after 1 sec");
358 return ERROR_TARGET_TIMEOUT
;
361 target
->state
= TARGET_HALTED
;
363 /* SVC, ARM state, IRQ and FIQ disabled */
366 cpsr
= buf_get_u32(arm
->cpsr
->value
, 0, 32);
369 arm_set_cpsr(arm
, cpsr
);
370 arm
->cpsr
->dirty
= 1;
372 /* start fetching from 0x0 */
373 buf_set_u32(arm
->pc
->value
, 0, 32, 0x0);
377 retval
= arm720t_disable_mmu_caches(target
, 1, 1, 1);
378 if (retval
!= ERROR_OK
)
380 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
381 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
382 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
384 retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
385 if (retval
!= ERROR_OK
)
391 static int arm720t_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
393 return arm7tdmi_init_target(cmd_ctx
, target
);
396 /* FIXME remove forward decls */
397 static int arm720t_mrc(struct target
*target
, int cpnum
,
398 uint32_t op1
, uint32_t op2
,
399 uint32_t CRn
, uint32_t CRm
,
401 static int arm720t_mcr(struct target
*target
, int cpnum
,
402 uint32_t op1
, uint32_t op2
,
403 uint32_t CRn
, uint32_t CRm
,
406 static int arm720t_init_arch_info(struct target
*target
,
407 struct arm720t_common
*arm720t
, struct jtag_tap
*tap
)
409 struct arm7_9_common
*arm7_9
= &arm720t
->arm7_9_common
;
411 arm7_9
->arm
.mrc
= arm720t_mrc
;
412 arm7_9
->arm
.mcr
= arm720t_mcr
;
414 arm7tdmi_init_arch_info(target
, arm7_9
, tap
);
416 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
418 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
419 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
421 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
422 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
423 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
424 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
425 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
426 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
427 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
428 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
433 static int arm720t_target_create(struct target
*target
, Jim_Interp
*interp
)
435 struct arm720t_common
*arm720t
= calloc(1, sizeof(*arm720t
));
437 arm720t
->arm7_9_common
.arm
.is_armv4
= true;
438 return arm720t_init_arch_info(target
, arm720t
, target
->tap
);
441 COMMAND_HANDLER(arm720t_handle_cp15_command
)
444 struct target
*target
= get_current_target(CMD_CTX
);
445 struct arm720t_common
*arm720t
= target_to_arm720(target
);
447 retval
= arm720t_verify_pointer(CMD_CTX
, arm720t
);
448 if (retval
!= ERROR_OK
)
451 if (target
->state
!= TARGET_HALTED
) {
452 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
456 /* one or more argument, access a single register (write if second argument is given */
459 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], opcode
);
463 retval
= arm720t_read_cp15(target
, opcode
, &value
);
464 if (retval
!= ERROR_OK
) {
465 command_print(CMD_CTX
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
469 retval
= jtag_execute_queue();
470 if (retval
!= ERROR_OK
)
473 command_print(CMD_CTX
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
474 } else if (CMD_ARGC
== 2) {
476 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
478 retval
= arm720t_write_cp15(target
, opcode
, value
);
479 if (retval
!= ERROR_OK
) {
480 command_print(CMD_CTX
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
483 command_print(CMD_CTX
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
490 static int arm720t_mrc(struct target
*target
, int cpnum
,
491 uint32_t op1
, uint32_t op2
,
492 uint32_t CRn
, uint32_t CRm
,
496 LOG_ERROR("Only cp15 is supported");
501 return arm720t_read_cp15(target
,
502 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
507 static int arm720t_mcr(struct target
*target
, int cpnum
,
508 uint32_t op1
, uint32_t op2
,
509 uint32_t CRn
, uint32_t CRm
,
513 LOG_ERROR("Only cp15 is supported");
517 /* write "from" r0 */
518 return arm720t_write_cp15(target
,
519 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
523 static const struct command_registration arm720t_exec_command_handlers
[] = {
526 .handler
= arm720t_handle_cp15_command
,
527 .mode
= COMMAND_EXEC
,
528 /* prefer using less error-prone "arm mcr" or "arm mrc" */
529 .help
= "display/modify cp15 register using ARM opcode"
531 .usage
= "instruction [value]",
533 COMMAND_REGISTRATION_DONE
536 static const struct command_registration arm720t_command_handlers
[] = {
538 .chain
= arm7_9_command_handlers
,
543 .help
= "arm720t command group",
545 .chain
= arm720t_exec_command_handlers
,
547 COMMAND_REGISTRATION_DONE
550 /** Holds methods for ARM720 targets. */
551 struct target_type arm720t_target
= {
555 .arch_state
= arm720t_arch_state
,
558 .resume
= arm7_9_resume
,
561 .assert_reset
= arm7_9_assert_reset
,
562 .deassert_reset
= arm7_9_deassert_reset
,
563 .soft_reset_halt
= arm720t_soft_reset_halt
,
565 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
567 .read_memory
= arm720t_read_memory
,
568 .write_memory
= arm7_9_write_memory_opt
,
569 .read_phys_memory
= arm720t_read_phys_memory
,
570 .write_phys_memory
= arm720t_write_phys_memory
,
572 .virt2phys
= arm720_virt2phys
,
574 .checksum_memory
= arm_checksum_memory
,
575 .blank_check_memory
= arm_blank_check_memory
,
577 .run_algorithm
= armv4_5_run_algorithm
,
579 .add_breakpoint
= arm7_9_add_breakpoint
,
580 .remove_breakpoint
= arm7_9_remove_breakpoint
,
581 .add_watchpoint
= arm7_9_add_watchpoint
,
582 .remove_watchpoint
= arm7_9_remove_watchpoint
,
584 .commands
= arm720t_command_handlers
,
585 .target_create
= arm720t_target_create
,
586 .init_target
= arm720t_init_target
,
587 .examine
= arm7_9_examine
,
588 .check_reset
= arm7_9_check_reset
,
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