1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include <helper/time_support.h>
29 #include "target_type.h"
31 #include "arm_opcodes.h"
35 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
36 * ARM DDI 0229C especially Chapter 9 about debug support.
40 #define _DEBUG_INSTRUCTION_EXECUTION_
43 static int arm720t_scan_cp15(struct target
*target
,
44 uint32_t out
, uint32_t *in
, int instruction
, int clock
)
47 struct arm720t_common
*arm720t
= target_to_arm720(target
);
48 struct arm_jtag
*jtag_info
;
49 struct scan_field fields
[2];
51 uint8_t instruction_buf
= instruction
;
53 jtag_info
= &arm720t
->arm7_9_common
.jtag_info
;
55 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
57 jtag_set_end_state(TAP_DRPAUSE
);
58 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
62 if ((retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
)) != ERROR_OK
)
67 fields
[0].num_bits
= 1;
68 fields
[0].out_value
= &instruction_buf
;
69 fields
[0].in_value
= NULL
;
71 fields
[1].num_bits
= 32;
72 fields
[1].out_value
= out_buf
;
73 fields
[1].in_value
= NULL
;
77 fields
[1].in_value
= (uint8_t *)in
;
78 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
79 jtag_add_callback(arm7flip32
, (jtag_callback_data_t
)in
);
82 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
86 jtag_add_runtest(0, TAP_DRPAUSE
);
88 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
89 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
95 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
97 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
99 LOG_DEBUG("out: %8.8" PRIx32
", instruction: %i, clock: %i", out
, instruction
, clock
);
105 static int arm720t_read_cp15(struct target
*target
, uint32_t opcode
, uint32_t *value
)
107 /* fetch CP15 opcode */
108 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
110 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
111 /* "EXECUTE" stage (1) */
112 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
113 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
114 /* "EXECUTE" stage (2) */
115 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
116 /* "EXECUTE" stage (3), CDATA is read */
117 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
122 static int arm720t_write_cp15(struct target
*target
, uint32_t opcode
, uint32_t value
)
124 /* fetch CP15 opcode */
125 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
127 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
128 /* "EXECUTE" stage (1) */
129 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
130 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
131 /* "EXECUTE" stage (2) */
132 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
133 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
138 static uint32_t arm720t_get_ttb(struct target
*target
)
142 arm720t_read_cp15(target
, 0xee120f10, &ttb
);
143 jtag_execute_queue();
150 static void arm720t_disable_mmu_caches(struct target
*target
,
151 int mmu
, int d_u_cache
, int i_cache
)
153 uint32_t cp15_control
;
155 /* read cp15 control register */
156 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
157 jtag_execute_queue();
160 cp15_control
&= ~0x1U
;
162 if (d_u_cache
|| i_cache
)
163 cp15_control
&= ~0x4U
;
165 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
168 static void arm720t_enable_mmu_caches(struct target
*target
,
169 int mmu
, int d_u_cache
, int i_cache
)
171 uint32_t cp15_control
;
173 /* read cp15 control register */
174 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
175 jtag_execute_queue();
178 cp15_control
|= 0x1U
;
180 if (d_u_cache
|| i_cache
)
181 cp15_control
|= 0x4U
;
183 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
186 static void arm720t_post_debug_entry(struct target
*target
)
188 struct arm720t_common
*arm720t
= target_to_arm720(target
);
190 /* examine cp15 control reg */
191 arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
192 jtag_execute_queue();
193 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm720t
->cp15_control_reg
);
195 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
196 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
197 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
199 /* save i/d fault status and address register */
200 arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
201 arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
202 jtag_execute_queue();
205 static void arm720t_pre_restore_context(struct target
*target
)
207 struct arm720t_common
*arm720t
= target_to_arm720(target
);
209 /* restore i/d fault status and address register */
210 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
211 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
214 static int arm720t_verify_pointer(struct command_context
*cmd_ctx
,
215 struct arm720t_common
*arm720t
)
217 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
) {
218 command_print(cmd_ctx
, "target is not an ARM720");
219 return ERROR_TARGET_INVALID
;
224 static int arm720t_arch_state(struct target
*target
)
226 struct arm720t_common
*arm720t
= target_to_arm720(target
);
229 static const char *state
[] =
231 "disabled", "enabled"
234 armv4_5
= &arm720t
->arm7_9_common
.armv4_5_common
;
236 arm_arch_state(target
);
237 LOG_USER("MMU: %s, Cache: %s",
238 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
239 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
244 static int arm720_mmu(struct target
*target
, int *enabled
)
246 if (target
->state
!= TARGET_HALTED
) {
247 LOG_ERROR("%s: target not halted", __func__
);
248 return ERROR_TARGET_INVALID
;
251 *enabled
= target_to_arm720(target
)->armv4_5_mmu
.mmu_enabled
;
255 static int arm720_virt2phys(struct target
*target
,
256 uint32_t virtual, uint32_t *physical
)
262 struct arm720t_common
*arm720t
= target_to_arm720(target
);
264 uint32_t ret
= armv4_5_mmu_translate_va(target
, &arm720t
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
273 static int arm720t_read_memory(struct target
*target
,
274 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
277 struct arm720t_common
*arm720t
= target_to_arm720(target
);
279 /* disable cache, but leave MMU enabled */
280 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
281 arm720t_disable_mmu_caches(target
, 0, 1, 0);
283 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
285 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
286 arm720t_enable_mmu_caches(target
, 0, 1, 0);
291 static int arm720t_read_phys_memory(struct target
*target
,
292 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
294 struct arm720t_common
*arm720t
= target_to_arm720(target
);
296 return armv4_5_mmu_read_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
299 static int arm720t_write_phys_memory(struct target
*target
,
300 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
302 struct arm720t_common
*arm720t
= target_to_arm720(target
);
304 return armv4_5_mmu_write_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
307 static int arm720t_soft_reset_halt(struct target
*target
)
309 int retval
= ERROR_OK
;
310 struct arm720t_common
*arm720t
= target_to_arm720(target
);
311 struct reg
*dbg_stat
= &arm720t
->arm7_9_common
312 .eice_cache
->reg_list
[EICE_DBG_STAT
];
313 struct arm
*armv4_5
= &arm720t
->arm7_9_common
316 if ((retval
= target_halt(target
)) != ERROR_OK
)
321 long long then
= timeval_ms();
323 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
325 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
327 embeddedice_read_reg(dbg_stat
);
328 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
336 if (debug_level
>= 3)
346 LOG_ERROR("Failed to halt CPU after 1 sec");
347 return ERROR_TARGET_TIMEOUT
;
350 target
->state
= TARGET_HALTED
;
352 /* SVC, ARM state, IRQ and FIQ disabled */
355 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
358 arm_set_cpsr(armv4_5
, cpsr
);
359 armv4_5
->cpsr
->dirty
= 1;
361 /* start fetching from 0x0 */
362 buf_set_u32(armv4_5
->pc
->value
, 0, 32, 0x0);
363 armv4_5
->pc
->dirty
= 1;
364 armv4_5
->pc
->valid
= 1;
366 arm720t_disable_mmu_caches(target
, 1, 1, 1);
367 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
368 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
369 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
371 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
379 static int arm720t_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
381 return arm7tdmi_init_target(cmd_ctx
, target
);
384 /* FIXME remove forward decls */
385 static int arm720t_mrc(struct target
*target
, int cpnum
,
386 uint32_t op1
, uint32_t op2
,
387 uint32_t CRn
, uint32_t CRm
,
389 static int arm720t_mcr(struct target
*target
, int cpnum
,
390 uint32_t op1
, uint32_t op2
,
391 uint32_t CRn
, uint32_t CRm
,
394 static int arm720t_init_arch_info(struct target
*target
,
395 struct arm720t_common
*arm720t
, struct jtag_tap
*tap
)
397 struct arm7_9_common
*arm7_9
= &arm720t
->arm7_9_common
;
399 arm7_9
->armv4_5_common
.mrc
= arm720t_mrc
;
400 arm7_9
->armv4_5_common
.mcr
= arm720t_mcr
;
402 arm7tdmi_init_arch_info(target
, arm7_9
, tap
);
404 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
406 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
407 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
409 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
410 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
411 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
412 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
413 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
414 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
415 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
416 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
421 static int arm720t_target_create(struct target
*target
, Jim_Interp
*interp
)
423 struct arm720t_common
*arm720t
= calloc(1, sizeof(*arm720t
));
425 arm720t
->arm7_9_common
.armv4_5_common
.is_armv4
= true;
426 return arm720t_init_arch_info(target
, arm720t
, target
->tap
);
429 COMMAND_HANDLER(arm720t_handle_cp15_command
)
432 struct target
*target
= get_current_target(CMD_CTX
);
433 struct arm720t_common
*arm720t
= target_to_arm720(target
);
434 struct arm_jtag
*jtag_info
;
436 retval
= arm720t_verify_pointer(CMD_CTX
, arm720t
);
437 if (retval
!= ERROR_OK
)
440 jtag_info
= &arm720t
->arm7_9_common
.jtag_info
;
442 if (target
->state
!= TARGET_HALTED
)
444 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
448 /* one or more argument, access a single register (write if second argument is given */
452 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], opcode
);
457 if ((retval
= arm720t_read_cp15(target
, opcode
, &value
)) != ERROR_OK
)
459 command_print(CMD_CTX
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
463 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
468 command_print(CMD_CTX
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
470 else if (CMD_ARGC
== 2)
473 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
475 if ((retval
= arm720t_write_cp15(target
, opcode
, value
)) != ERROR_OK
)
477 command_print(CMD_CTX
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
480 command_print(CMD_CTX
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
487 static int arm720t_mrc(struct target
*target
, int cpnum
,
488 uint32_t op1
, uint32_t op2
,
489 uint32_t CRn
, uint32_t CRm
,
494 LOG_ERROR("Only cp15 is supported");
499 return arm720t_read_cp15(target
,
500 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
505 static int arm720t_mcr(struct target
*target
, int cpnum
,
506 uint32_t op1
, uint32_t op2
,
507 uint32_t CRn
, uint32_t CRm
,
512 LOG_ERROR("Only cp15 is supported");
516 /* write "from" r0 */
517 return arm720t_write_cp15(target
,
518 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
522 static const struct command_registration arm720t_exec_command_handlers
[] = {
525 .handler
= arm720t_handle_cp15_command
,
526 .mode
= COMMAND_EXEC
,
527 /* prefer using less error-prone "arm mcr" or "arm mrc" */
528 .help
= "display/modify cp15 register using ARM opcode"
530 .usage
= "instruction [value]",
532 COMMAND_REGISTRATION_DONE
535 static const struct command_registration arm720t_command_handlers
[] = {
537 .chain
= arm7_9_command_handlers
,
542 .help
= "arm720t command group",
543 .chain
= arm720t_exec_command_handlers
,
545 COMMAND_REGISTRATION_DONE
548 /** Holds methods for ARM720 targets. */
549 struct target_type arm720t_target
=
554 .arch_state
= arm720t_arch_state
,
557 .resume
= arm7_9_resume
,
560 .assert_reset
= arm7_9_assert_reset
,
561 .deassert_reset
= arm7_9_deassert_reset
,
562 .soft_reset_halt
= arm720t_soft_reset_halt
,
564 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
566 .read_memory
= arm720t_read_memory
,
567 .write_memory
= arm7_9_write_memory
,
568 .read_phys_memory
= arm720t_read_phys_memory
,
569 .write_phys_memory
= arm720t_write_phys_memory
,
571 .virt2phys
= arm720_virt2phys
,
573 .bulk_write_memory
= arm7_9_bulk_write_memory
,
575 .checksum_memory
= arm_checksum_memory
,
576 .blank_check_memory
= arm_blank_check_memory
,
578 .run_algorithm
= armv4_5_run_algorithm
,
580 .add_breakpoint
= arm7_9_add_breakpoint
,
581 .remove_breakpoint
= arm7_9_remove_breakpoint
,
582 .add_watchpoint
= arm7_9_add_watchpoint
,
583 .remove_watchpoint
= arm7_9_remove_watchpoint
,
585 .commands
= arm720t_command_handlers
,
586 .target_create
= arm720t_target_create
,
587 .init_target
= arm720t_init_target
,
588 .examine
= arm7_9_examine
,
589 .check_reset
= arm7_9_check_reset
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)