1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/time_support.h>
28 #include "target_type.h"
30 #include "arm_opcodes.h"
34 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
35 * ARM DDI 0229C especially Chapter 9 about debug support.
39 #define _DEBUG_INSTRUCTION_EXECUTION_
42 static int arm720t_scan_cp15(struct target
*target
,
43 uint32_t out
, uint32_t *in
, int instruction
, int clock_arg
)
46 struct arm720t_common
*arm720t
= target_to_arm720(target
);
47 struct arm_jtag
*jtag_info
;
48 struct scan_field fields
[2];
50 uint8_t instruction_buf
= instruction
;
52 jtag_info
= &arm720t
->arm7_9_common
.jtag_info
;
54 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
56 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_DRPAUSE
);
57 if (retval
!= ERROR_OK
)
59 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_DRPAUSE
);
60 if (retval
!= ERROR_OK
)
63 fields
[0].num_bits
= 1;
64 fields
[0].out_value
= &instruction_buf
;
65 fields
[0].in_value
= NULL
;
67 fields
[1].num_bits
= 32;
68 fields
[1].out_value
= out_buf
;
69 fields
[1].in_value
= NULL
;
72 fields
[1].in_value
= (uint8_t *)in
;
73 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
74 jtag_add_callback(arm7flip32
, (jtag_callback_data_t
)in
);
76 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
79 jtag_add_runtest(0, TAP_DRPAUSE
);
81 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
82 retval
= jtag_execute_queue();
83 if (retval
!= ERROR_OK
)
87 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
89 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock_arg
);
91 LOG_DEBUG("out: %8.8" PRIx32
", instruction: %i, clock: %i", out
, instruction
, clock_arg
);
97 static int arm720t_read_cp15(struct target
*target
, uint32_t opcode
, uint32_t *value
)
99 /* fetch CP15 opcode */
100 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
102 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
103 /* "EXECUTE" stage (1) */
104 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
105 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
106 /* "EXECUTE" stage (2) */
107 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
108 /* "EXECUTE" stage (3), CDATA is read */
109 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
114 static int arm720t_write_cp15(struct target
*target
, uint32_t opcode
, uint32_t value
)
116 /* fetch CP15 opcode */
117 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
119 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
120 /* "EXECUTE" stage (1) */
121 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
122 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
123 /* "EXECUTE" stage (2) */
124 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
125 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
130 static int arm720t_get_ttb(struct target
*target
, uint32_t *result
)
136 retval
= arm720t_read_cp15(target
, 0xee120f10, &ttb
);
137 if (retval
!= ERROR_OK
)
139 retval
= jtag_execute_queue();
140 if (retval
!= ERROR_OK
)
150 static int arm720t_disable_mmu_caches(struct target
*target
,
151 int mmu
, int d_u_cache
, int i_cache
)
153 uint32_t cp15_control
;
156 /* read cp15 control register */
157 retval
= arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
158 if (retval
!= ERROR_OK
)
160 retval
= jtag_execute_queue();
161 if (retval
!= ERROR_OK
)
165 cp15_control
&= ~0x1U
;
167 if (d_u_cache
|| i_cache
)
168 cp15_control
&= ~0x4U
;
170 retval
= arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
174 static int arm720t_enable_mmu_caches(struct target
*target
,
175 int mmu
, int d_u_cache
, int i_cache
)
177 uint32_t cp15_control
;
180 /* read cp15 control register */
181 retval
= arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
182 if (retval
!= ERROR_OK
)
184 retval
= jtag_execute_queue();
185 if (retval
!= ERROR_OK
)
189 cp15_control
|= 0x1U
;
191 if (d_u_cache
|| i_cache
)
192 cp15_control
|= 0x4U
;
194 retval
= arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
198 static int arm720t_post_debug_entry(struct target
*target
)
200 struct arm720t_common
*arm720t
= target_to_arm720(target
);
203 /* examine cp15 control reg */
204 retval
= arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
205 if (retval
!= ERROR_OK
)
207 retval
= jtag_execute_queue();
208 if (retval
!= ERROR_OK
)
210 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm720t
->cp15_control_reg
);
212 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
213 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
214 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
216 /* save i/d fault status and address register */
217 retval
= arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
218 if (retval
!= ERROR_OK
)
220 retval
= arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
221 if (retval
!= ERROR_OK
)
223 retval
= jtag_execute_queue();
227 static void arm720t_pre_restore_context(struct target
*target
)
229 struct arm720t_common
*arm720t
= target_to_arm720(target
);
231 /* restore i/d fault status and address register */
232 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
233 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
236 static int arm720t_arch_state(struct target
*target
)
238 struct arm720t_common
*arm720t
= target_to_arm720(target
);
240 static const char *state
[] = {
241 "disabled", "enabled"
244 arm_arch_state(target
);
245 LOG_USER("MMU: %s, Cache: %s",
246 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
247 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
252 static int arm720_mmu(struct target
*target
, int *enabled
)
254 if (target
->state
!= TARGET_HALTED
) {
255 LOG_ERROR("%s: target not halted", __func__
);
256 return ERROR_TARGET_INVALID
;
259 *enabled
= target_to_arm720(target
)->armv4_5_mmu
.mmu_enabled
;
263 static int arm720_virt2phys(struct target
*target
,
264 target_addr_t
virtual, target_addr_t
*physical
)
267 struct arm720t_common
*arm720t
= target_to_arm720(target
);
270 int retval
= armv4_5_mmu_translate_va(target
,
271 &arm720t
->armv4_5_mmu
, virtual, &cb
, &ret
);
272 if (retval
!= ERROR_OK
)
278 static int arm720t_read_memory(struct target
*target
,
279 target_addr_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
282 struct arm720t_common
*arm720t
= target_to_arm720(target
);
284 /* disable cache, but leave MMU enabled */
285 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
286 retval
= arm720t_disable_mmu_caches(target
, 0, 1, 0);
287 if (retval
!= ERROR_OK
)
290 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
292 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
293 retval
= arm720t_enable_mmu_caches(target
, 0, 1, 0);
294 if (retval
!= ERROR_OK
)
301 static int arm720t_read_phys_memory(struct target
*target
,
302 target_addr_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
304 struct arm720t_common
*arm720t
= target_to_arm720(target
);
306 return armv4_5_mmu_read_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
309 static int arm720t_write_phys_memory(struct target
*target
,
310 target_addr_t address
, uint32_t size
, uint32_t count
, const uint8_t *buffer
)
312 struct arm720t_common
*arm720t
= target_to_arm720(target
);
314 return armv4_5_mmu_write_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
317 static int arm720t_soft_reset_halt(struct target
*target
)
319 int retval
= ERROR_OK
;
320 struct arm720t_common
*arm720t
= target_to_arm720(target
);
321 struct reg
*dbg_stat
= &arm720t
->arm7_9_common
322 .eice_cache
->reg_list
[EICE_DBG_STAT
];
323 struct arm
*arm
= &arm720t
->arm7_9_common
.arm
;
325 retval
= target_halt(target
);
326 if (retval
!= ERROR_OK
)
329 int64_t then
= timeval_ms();
331 while (!(timeout
= ((timeval_ms()-then
) > 1000))) {
332 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0) {
333 embeddedice_read_reg(dbg_stat
);
334 retval
= jtag_execute_queue();
335 if (retval
!= ERROR_OK
)
339 if (debug_level
>= 3)
345 LOG_ERROR("Failed to halt CPU after 1 sec");
346 return ERROR_TARGET_TIMEOUT
;
349 target
->state
= TARGET_HALTED
;
351 /* SVC, ARM state, IRQ and FIQ disabled */
354 cpsr
= buf_get_u32(arm
->cpsr
->value
, 0, 32);
357 arm_set_cpsr(arm
, cpsr
);
358 arm
->cpsr
->dirty
= true;
360 /* start fetching from 0x0 */
361 buf_set_u32(arm
->pc
->value
, 0, 32, 0x0);
362 arm
->pc
->dirty
= true;
363 arm
->pc
->valid
= true;
365 retval
= arm720t_disable_mmu_caches(target
, 1, 1, 1);
366 if (retval
!= ERROR_OK
)
368 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
369 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
370 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
372 retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
373 if (retval
!= ERROR_OK
)
379 static int arm720t_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
381 return arm7tdmi_init_target(cmd_ctx
, target
);
384 static void arm720t_deinit_target(struct target
*target
)
386 arm7tdmi_deinit_target(target
);
389 /* FIXME remove forward decls */
390 static int arm720t_mrc(struct target
*target
, int cpnum
,
391 uint32_t op1
, uint32_t op2
,
392 uint32_t crn
, uint32_t crm
,
394 static int arm720t_mcr(struct target
*target
, int cpnum
,
395 uint32_t op1
, uint32_t op2
,
396 uint32_t crn
, uint32_t crm
,
399 static int arm720t_init_arch_info(struct target
*target
,
400 struct arm720t_common
*arm720t
, struct jtag_tap
*tap
)
402 struct arm7_9_common
*arm7_9
= &arm720t
->arm7_9_common
;
404 arm7_9
->arm
.mrc
= arm720t_mrc
;
405 arm7_9
->arm
.mcr
= arm720t_mcr
;
407 arm7tdmi_init_arch_info(target
, arm7_9
, tap
);
409 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
411 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
412 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
414 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
415 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
416 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
417 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
418 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
419 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
420 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
421 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
426 static int arm720t_target_create(struct target
*target
, Jim_Interp
*interp
)
428 struct arm720t_common
*arm720t
= calloc(1, sizeof(*arm720t
));
430 arm720t
->arm7_9_common
.arm
.arch
= ARM_ARCH_V4
;
431 return arm720t_init_arch_info(target
, arm720t
, target
->tap
);
434 static int arm720t_mrc(struct target
*target
, int cpnum
,
435 uint32_t op1
, uint32_t op2
,
436 uint32_t crn
, uint32_t crm
,
440 LOG_ERROR("Only cp15 is supported");
445 return arm720t_read_cp15(target
,
446 ARMV4_5_MRC(cpnum
, op1
, 0, crn
, crm
, op2
),
451 static int arm720t_mcr(struct target
*target
, int cpnum
,
452 uint32_t op1
, uint32_t op2
,
453 uint32_t crn
, uint32_t crm
,
457 LOG_ERROR("Only cp15 is supported");
461 /* write "from" r0 */
462 return arm720t_write_cp15(target
,
463 ARMV4_5_MCR(cpnum
, op1
, 0, crn
, crm
, op2
),
467 static const struct command_registration arm720t_command_handlers
[] = {
469 .chain
= arm7_9_command_handlers
,
471 COMMAND_REGISTRATION_DONE
474 /** Holds methods for ARM720 targets. */
475 struct target_type arm720t_target
= {
479 .arch_state
= arm720t_arch_state
,
482 .resume
= arm7_9_resume
,
485 .assert_reset
= arm7_9_assert_reset
,
486 .deassert_reset
= arm7_9_deassert_reset
,
487 .soft_reset_halt
= arm720t_soft_reset_halt
,
489 .get_gdb_arch
= arm_get_gdb_arch
,
490 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
492 .read_memory
= arm720t_read_memory
,
493 .write_memory
= arm7_9_write_memory_opt
,
494 .read_phys_memory
= arm720t_read_phys_memory
,
495 .write_phys_memory
= arm720t_write_phys_memory
,
497 .virt2phys
= arm720_virt2phys
,
499 .checksum_memory
= arm_checksum_memory
,
500 .blank_check_memory
= arm_blank_check_memory
,
502 .run_algorithm
= armv4_5_run_algorithm
,
504 .add_breakpoint
= arm7_9_add_breakpoint
,
505 .remove_breakpoint
= arm7_9_remove_breakpoint
,
506 .add_watchpoint
= arm7_9_add_watchpoint
,
507 .remove_watchpoint
= arm7_9_remove_watchpoint
,
509 .commands
= arm720t_command_handlers
,
510 .target_create
= arm720t_target_create
,
511 .init_target
= arm720t_init_target
,
512 .deinit_target
= arm720t_deinit_target
,
513 .examine
= arm7_9_examine
,
514 .check_reset
= arm7_9_check_reset
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)