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[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "armv4_5.h"
29 #include "arm_jtag.h"
30 #include "jtag.h"
31 #include "log.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
34
35 #include <stdlib.h>
36 #include <string.h>
37 #include <unistd.h>
38
39 #include <sys/types.h>
40 #include <sys/stat.h>
41 #include <sys/time.h>
42 #include <errno.h>
43
44 int arm7_9_debug_entry(target_t *target);
45 int arm7_9_enable_sw_bkpts(struct target_s *target);
46
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etb_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60 int arm7_9_reinit_embeddedice(target_t *target)
61 {
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64
65 breakpoint_t *breakpoint = target->breakpoints;
66
67 arm7_9->wp_available = 2;
68 arm7_9->wp0_used = 0;
69 arm7_9->wp1_used = 0;
70
71 /* mark all hardware breakpoints as unset */
72 while (breakpoint)
73 {
74 if (breakpoint->type == BKPT_HARD)
75 {
76 breakpoint->set = 0;
77 }
78 breakpoint = breakpoint->next;
79 }
80
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 {
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
85 }
86
87 arm7_9->reinit_embeddedice = 0;
88
89 return ERROR_OK;
90 }
91
92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
93 {
94 target_t *target = priv;
95 armv4_5_common_t *armv4_5 = target->arch_info;
96 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
101 */
102 if (event == JTAG_TRST_ASSERTED)
103 {
104 arm7_9->reinit_embeddedice = 1;
105 }
106
107 return ERROR_OK;
108 }
109
110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
111 {
112 armv4_5_common_t *armv4_5 = target->arch_info;
113 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
114
115 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
116 {
117 return -1;
118 }
119
120 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
121 {
122 return -1;
123 }
124
125 *armv4_5_p = armv4_5;
126 *arm7_9_p = arm7_9;
127
128 return ERROR_OK;
129 }
130
131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
132 {
133 armv4_5_common_t *armv4_5 = target->arch_info;
134 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
135
136 if (target->state != TARGET_HALTED)
137 {
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED;
140 }
141
142 if (arm7_9->force_hw_bkpts)
143 breakpoint->type = BKPT_HARD;
144
145 if (breakpoint->set)
146 {
147 WARNING("breakpoint already set");
148 return ERROR_OK;
149 }
150
151 if (breakpoint->type == BKPT_HARD)
152 {
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
155 if (!arm7_9->wp0_used)
156 {
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
162
163 jtag_execute_queue();
164 arm7_9->wp0_used = 1;
165 breakpoint->set = 1;
166 }
167 else if (!arm7_9->wp1_used)
168 {
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
173 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
174
175 jtag_execute_queue();
176 arm7_9->wp1_used = 1;
177 breakpoint->set = 2;
178 }
179 else
180 {
181 ERROR("BUG: no hardware comparator available");
182 return ERROR_OK;
183 }
184 }
185 else if (breakpoint->type == BKPT_SOFT)
186 {
187 if (breakpoint->length == 4)
188 {
189 /* keep the original instruction in target endianness */
190 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
191 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
192 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
193 }
194 else
195 {
196 /* keep the original instruction in target endianness */
197 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
198 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
199 target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
200 }
201 breakpoint->set = 1;
202 }
203
204 return ERROR_OK;
205
206 }
207
208 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
209 {
210 armv4_5_common_t *armv4_5 = target->arch_info;
211 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
212
213 if (target->state != TARGET_HALTED)
214 {
215 WARNING("target not halted");
216 return ERROR_TARGET_NOT_HALTED;
217 }
218
219 if (!breakpoint->set)
220 {
221 WARNING("breakpoint not set");
222 return ERROR_OK;
223 }
224
225 if (breakpoint->type == BKPT_HARD)
226 {
227 if (breakpoint->set == 1)
228 {
229 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
230 jtag_execute_queue();
231 arm7_9->wp0_used = 0;
232 }
233 else if (breakpoint->set == 2)
234 {
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
236 jtag_execute_queue();
237 arm7_9->wp1_used = 0;
238 }
239 breakpoint->set = 0;
240 }
241 else
242 {
243 /* restore original instruction (kept in target endianness) */
244 if (breakpoint->length == 4)
245 {
246 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
247 }
248 else
249 {
250 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
251 }
252 breakpoint->set = 0;
253 }
254
255 return ERROR_OK;
256 }
257
258 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
259 {
260 armv4_5_common_t *armv4_5 = target->arch_info;
261 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
262
263 if (target->state != TARGET_HALTED)
264 {
265 WARNING("target not halted");
266 return ERROR_TARGET_NOT_HALTED;
267 }
268
269 if (arm7_9->force_hw_bkpts)
270 {
271 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
272 breakpoint->type = BKPT_HARD;
273 }
274
275 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
276 {
277 INFO("sw breakpoint requested, but software breakpoints not enabled");
278 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
279 }
280
281 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
282 {
283 INFO("no watchpoint unit available for hardware breakpoint");
284 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
285 }
286
287 if ((breakpoint->length != 2) && (breakpoint->length != 4))
288 {
289 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
290 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
291 }
292
293 if (breakpoint->type == BKPT_HARD)
294 arm7_9->wp_available--;
295
296 return ERROR_OK;
297 }
298
299 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
300 {
301 armv4_5_common_t *armv4_5 = target->arch_info;
302 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
303
304 if (target->state != TARGET_HALTED)
305 {
306 WARNING("target not halted");
307 return ERROR_TARGET_NOT_HALTED;
308 }
309
310 if (breakpoint->set)
311 {
312 arm7_9_unset_breakpoint(target, breakpoint);
313 }
314
315 if (breakpoint->type == BKPT_HARD)
316 arm7_9->wp_available++;
317
318 return ERROR_OK;
319 }
320
321 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
322 {
323 armv4_5_common_t *armv4_5 = target->arch_info;
324 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
325 int rw_mask = 1;
326 u32 mask;
327
328 mask = watchpoint->length - 1;
329
330 if (target->state != TARGET_HALTED)
331 {
332 WARNING("target not halted");
333 return ERROR_TARGET_NOT_HALTED;
334 }
335
336 if (watchpoint->rw == WPT_ACCESS)
337 rw_mask = 0;
338 else
339 rw_mask = 1;
340
341 if (!arm7_9->wp0_used)
342 {
343 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
344 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
345 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
346 if( watchpoint->mask != 0xffffffffu )
347 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
348 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
349 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
350
351 jtag_execute_queue();
352 watchpoint->set = 1;
353 arm7_9->wp0_used = 2;
354 }
355 else if (!arm7_9->wp1_used)
356 {
357 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
359 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
360 if( watchpoint->mask != 0xffffffffu )
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
363 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
364
365 jtag_execute_queue();
366 watchpoint->set = 2;
367 arm7_9->wp1_used = 2;
368 }
369 else
370 {
371 ERROR("BUG: no hardware comparator available");
372 return ERROR_OK;
373 }
374
375 return ERROR_OK;
376 }
377
378 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
379 {
380 armv4_5_common_t *armv4_5 = target->arch_info;
381 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
382
383 if (target->state != TARGET_HALTED)
384 {
385 WARNING("target not halted");
386 return ERROR_TARGET_NOT_HALTED;
387 }
388
389 if (!watchpoint->set)
390 {
391 WARNING("breakpoint not set");
392 return ERROR_OK;
393 }
394
395 if (watchpoint->set == 1)
396 {
397 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
398 jtag_execute_queue();
399 arm7_9->wp0_used = 0;
400 }
401 else if (watchpoint->set == 2)
402 {
403 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
404 jtag_execute_queue();
405 arm7_9->wp1_used = 0;
406 }
407 watchpoint->set = 0;
408
409 return ERROR_OK;
410 }
411
412 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
413 {
414 armv4_5_common_t *armv4_5 = target->arch_info;
415 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
416
417 if (target->state != TARGET_HALTED)
418 {
419 WARNING("target not halted");
420 return ERROR_TARGET_NOT_HALTED;
421 }
422
423 if (arm7_9->wp_available < 1)
424 {
425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
426 }
427
428 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
429 {
430 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
431 }
432
433 arm7_9->wp_available--;
434
435 return ERROR_OK;
436 }
437
438 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
439 {
440 armv4_5_common_t *armv4_5 = target->arch_info;
441 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
442
443 if (target->state != TARGET_HALTED)
444 {
445 WARNING("target not halted");
446 return ERROR_TARGET_NOT_HALTED;
447 }
448
449 if (watchpoint->set)
450 {
451 arm7_9_unset_watchpoint(target, watchpoint);
452 }
453
454 arm7_9->wp_available++;
455
456 return ERROR_OK;
457 }
458
459 int arm7_9_enable_sw_bkpts(struct target_s *target)
460 {
461 armv4_5_common_t *armv4_5 = target->arch_info;
462 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
463 int retval;
464
465 if (arm7_9->sw_bkpts_enabled)
466 return ERROR_OK;
467
468 if (arm7_9->wp_available < 1)
469 {
470 WARNING("can't enable sw breakpoints with no watchpoint unit available");
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
472 }
473 arm7_9->wp_available--;
474
475 if (!arm7_9->wp0_used)
476 {
477 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
478 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
479 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
480 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
481 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
482 arm7_9->sw_bkpts_enabled = 1;
483 arm7_9->wp0_used = 3;
484 }
485 else if (!arm7_9->wp1_used)
486 {
487 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
488 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
489 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
490 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
491 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
492 arm7_9->sw_bkpts_enabled = 2;
493 arm7_9->wp1_used = 3;
494 }
495 else
496 {
497 ERROR("BUG: both watchpoints used, but wp_available >= 1");
498 exit(-1);
499 }
500
501 if ((retval = jtag_execute_queue()) != ERROR_OK)
502 {
503 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
504 exit(-1);
505 };
506
507 return ERROR_OK;
508 }
509
510 int arm7_9_disable_sw_bkpts(struct target_s *target)
511 {
512 armv4_5_common_t *armv4_5 = target->arch_info;
513 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
514
515 if (!arm7_9->sw_bkpts_enabled)
516 return ERROR_OK;
517
518 if (arm7_9->sw_bkpts_enabled == 1)
519 {
520 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
521 arm7_9->sw_bkpts_enabled = 0;
522 arm7_9->wp0_used = 0;
523 arm7_9->wp_available++;
524 }
525 else if (arm7_9->sw_bkpts_enabled == 2)
526 {
527 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
528 arm7_9->sw_bkpts_enabled = 0;
529 arm7_9->wp1_used = 0;
530 arm7_9->wp_available++;
531 }
532
533 return ERROR_OK;
534 }
535
536 int arm7_9_execute_sys_speed(struct target_s *target)
537 {
538 int timeout;
539 int retval;
540
541 armv4_5_common_t *armv4_5 = target->arch_info;
542 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
543 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
544 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
545
546 /* set RESTART instruction */
547 jtag_add_end_state(TAP_RTI);
548 arm_jtag_set_instr(jtag_info, 0x4);
549
550 for (timeout=0; timeout<50; timeout++)
551 {
552 /* read debug status register */
553 embeddedice_read_reg(dbg_stat);
554 if ((retval = jtag_execute_queue()) != ERROR_OK)
555 return retval;
556 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
557 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
558 break;
559 usleep(100000);
560 }
561 if (timeout == 50)
562 {
563 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
564 return ERROR_TARGET_TIMEOUT;
565 }
566
567 return ERROR_OK;
568 }
569
570 int arm7_9_execute_fast_sys_speed(struct target_s *target)
571 {
572 u8 check_value[4], check_mask[4];
573
574 armv4_5_common_t *armv4_5 = target->arch_info;
575 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
576 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
577 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
578
579 /* set RESTART instruction */
580 jtag_add_end_state(TAP_RTI);
581 arm_jtag_set_instr(jtag_info, 0x4);
582
583 /* check for DBGACK and SYSCOMP set (others don't care) */
584 buf_set_u32(check_value, 0, 32, 0x9);
585 buf_set_u32(check_mask, 0, 32, 0x9);
586
587 /* read debug status register */
588 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
589
590 return ERROR_OK;
591 }
592
593 enum target_state arm7_9_poll(target_t *target)
594 {
595 int retval;
596 armv4_5_common_t *armv4_5 = target->arch_info;
597 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
598 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
599
600 if (arm7_9->reinit_embeddedice)
601 {
602 arm7_9_reinit_embeddedice(target);
603 }
604
605 /* read debug status register */
606 embeddedice_read_reg(dbg_stat);
607 if ((retval = jtag_execute_queue()) != ERROR_OK)
608 {
609 switch (retval)
610 {
611 case ERROR_JTAG_QUEUE_FAILED:
612 ERROR("JTAG queue failed while reading EmbeddedICE status register");
613 exit(-1);
614 break;
615 default:
616 break;
617 }
618 }
619
620 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
621 {
622 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
623 if ((target->state == TARGET_UNKNOWN))
624 {
625 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
626 target->state = TARGET_RUNNING;
627 }
628 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
629 {
630 target->state = TARGET_HALTED;
631 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
632 return retval;
633
634 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
635 }
636 if (target->state == TARGET_DEBUG_RUNNING)
637 {
638 target->state = TARGET_HALTED;
639 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
640 return retval;
641
642 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
643 }
644 }
645 else
646 {
647 if (target->state != TARGET_DEBUG_RUNNING)
648 target->state = TARGET_RUNNING;
649 }
650
651 return target->state;
652 }
653
654 int arm7_9_assert_reset(target_t *target)
655 {
656 int retval;
657
658 DEBUG("target->state: %s", target_state_strings[target->state]);
659
660 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
661 {
662 /* if the target wasn't running, there might be working areas allocated */
663 target_free_all_working_areas(target);
664
665 /* assert SRST and TRST */
666 /* system would get ouf sync if we didn't reset test-logic, too */
667 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
668 {
669 if (retval == ERROR_JTAG_RESET_CANT_SRST)
670 {
671 WARNING("can't assert srst");
672 return retval;
673 }
674 else
675 {
676 ERROR("unknown error");
677 exit(-1);
678 }
679 }
680 jtag_add_sleep(5000);
681 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
682 {
683 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
684 {
685 WARNING("srst resets test logic, too");
686 retval = jtag_add_reset(1, 1);
687 }
688 }
689 }
690 else
691 {
692 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
693 {
694 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
695 {
696 WARNING("srst resets test logic, too");
697 retval = jtag_add_reset(1, 1);
698 }
699
700 if (retval == ERROR_JTAG_RESET_CANT_SRST)
701 {
702 WARNING("can't assert srst");
703 return retval;
704 }
705 else if (retval != ERROR_OK)
706 {
707 ERROR("unknown error");
708 exit(-1);
709 }
710 }
711 }
712
713 target->state = TARGET_RESET;
714 jtag_add_sleep(50000);
715
716 armv4_5_invalidate_core_regs(target);
717
718 return ERROR_OK;
719
720 }
721
722 int arm7_9_deassert_reset(target_t *target)
723 {
724 DEBUG("target->state: %s", target_state_strings[target->state]);
725
726 /* deassert reset lines */
727 jtag_add_reset(0, 0);
728
729 return ERROR_OK;
730 }
731
732 int arm7_9_clear_halt(target_t *target)
733 {
734 armv4_5_common_t *armv4_5 = target->arch_info;
735 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
736 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
737
738 /* we used DBGRQ only if we didn't come out of reset */
739 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
740 {
741 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
742 */
743 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
744 embeddedice_store_reg(dbg_ctrl);
745 }
746 else
747 {
748 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
749 {
750 /* if we came out of reset, and vector catch is supported, we used
751 * vector catch to enter debug state
752 * restore the register in that case
753 */
754 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
755 }
756 else
757 {
758 /* restore registers if watchpoint unit 0 was in use
759 */
760 if (arm7_9->wp0_used)
761 {
762 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
763 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
764 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
765 }
766 /* control value always has to be restored, as it was either disabled,
767 * or enabled with possibly different bits
768 */
769 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
770 }
771 }
772
773 return ERROR_OK;
774 }
775
776 int arm7_9_soft_reset_halt(struct target_s *target)
777 {
778 armv4_5_common_t *armv4_5 = target->arch_info;
779 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
780 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
781 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
782 int i;
783
784 if (target->state == TARGET_RUNNING)
785 {
786 target->type->halt(target);
787 }
788
789 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
790 {
791 embeddedice_read_reg(dbg_stat);
792 jtag_execute_queue();
793 }
794 target->state = TARGET_HALTED;
795
796 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
797 * ensure that DBGRQ is cleared
798 */
799 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
800 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
801 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
802 embeddedice_store_reg(dbg_ctrl);
803
804 arm7_9_clear_halt(target);
805
806 /* if the target is in Thumb state, change to ARM state */
807 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
808 {
809 u32 r0_thumb, pc_thumb;
810 DEBUG("target entered debug from Thumb state, changing to ARM");
811 /* Entered debug from Thumb mode */
812 armv4_5->core_state = ARMV4_5_STATE_THUMB;
813 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
814 }
815
816 /* all register content is now invalid */
817 armv4_5_invalidate_core_regs(target);
818
819 /* SVC, ARM state, IRQ and FIQ disabled */
820 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
821 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
822 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
823
824 /* start fetching from 0x0 */
825 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
826 armv4_5->core_cache->reg_list[15].dirty = 1;
827 armv4_5->core_cache->reg_list[15].valid = 1;
828
829 armv4_5->core_mode = ARMV4_5_MODE_SVC;
830 armv4_5->core_state = ARMV4_5_STATE_ARM;
831
832 /* reset registers */
833 for (i = 0; i <= 14; i++)
834 {
835 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
836 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
837 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
838 }
839
840 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
841
842 return ERROR_OK;
843 }
844
845 int arm7_9_prepare_reset_halt(target_t *target)
846 {
847 armv4_5_common_t *armv4_5 = target->arch_info;
848 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
849
850 if (arm7_9->has_vector_catch)
851 {
852 /* program vector catch register to catch reset vector */
853 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
854 }
855 else
856 {
857 /* program watchpoint unit to match on reset vector address */
858 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
859 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
860 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
861 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
862 }
863
864 return ERROR_OK;
865 }
866
867 int arm7_9_halt(target_t *target)
868 {
869 armv4_5_common_t *armv4_5 = target->arch_info;
870 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
871 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
872
873 DEBUG("target->state: %s", target_state_strings[target->state]);
874
875 if (target->state == TARGET_HALTED)
876 {
877 WARNING("target was already halted");
878 return ERROR_TARGET_ALREADY_HALTED;
879 }
880
881 if (target->state == TARGET_UNKNOWN)
882 {
883 WARNING("target was in unknown state when halt was requested");
884 }
885
886 if (target->state == TARGET_RESET)
887 {
888 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
889 {
890 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
891 return ERROR_TARGET_FAILURE;
892 }
893 else
894 {
895 /* we came here in a reset_halt or reset_init sequence
896 * debug entry was already prepared in arm7_9_prepare_reset_halt()
897 */
898 target->debug_reason = DBG_REASON_DBGRQ;
899
900 return ERROR_OK;
901 }
902 }
903
904 if (arm7_9->use_dbgrq)
905 {
906 /* program EmbeddedICE Debug Control Register to assert DBGRQ
907 */
908 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
909 embeddedice_store_reg(dbg_ctrl);
910 }
911 else
912 {
913 /* program watchpoint unit to match on any address
914 */
915 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
916 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
917 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
918 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
919 }
920
921 target->debug_reason = DBG_REASON_DBGRQ;
922
923 return ERROR_OK;
924 }
925
926 int arm7_9_debug_entry(target_t *target)
927 {
928 int i;
929 u32 context[16];
930 u32* context_p[16];
931 u32 r0_thumb, pc_thumb;
932 u32 cpsr;
933 int retval;
934 /* get pointers to arch-specific information */
935 armv4_5_common_t *armv4_5 = target->arch_info;
936 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
937 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
938 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
939
940 #ifdef _DEBUG_ARM7_9_
941 DEBUG("-");
942 #endif
943
944 if (arm7_9->pre_debug_entry)
945 arm7_9->pre_debug_entry(target);
946
947 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
948 * ensure that DBGRQ is cleared
949 */
950 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
951 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
952 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
953 embeddedice_store_reg(dbg_ctrl);
954
955 arm7_9_clear_halt(target);
956
957 if ((retval = jtag_execute_queue()) != ERROR_OK)
958 {
959 switch (retval)
960 {
961 case ERROR_JTAG_QUEUE_FAILED:
962 ERROR("JTAG queue failed while writing EmbeddedICE control register");
963 exit(-1);
964 break;
965 default:
966 break;
967 }
968 }
969
970 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
971 return retval;
972
973
974 if (target->state != TARGET_HALTED)
975 {
976 WARNING("target not halted");
977 return ERROR_TARGET_NOT_HALTED;
978 }
979
980 /* if the target is in Thumb state, change to ARM state */
981 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
982 {
983 DEBUG("target entered debug from Thumb state");
984 /* Entered debug from Thumb mode */
985 armv4_5->core_state = ARMV4_5_STATE_THUMB;
986 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
987 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
988 }
989 else
990 {
991 DEBUG("target entered debug from ARM state");
992 /* Entered debug from ARM mode */
993 armv4_5->core_state = ARMV4_5_STATE_ARM;
994 }
995
996 for (i = 0; i < 16; i++)
997 context_p[i] = &context[i];
998 /* save core registers (r0 - r15 of current core mode) */
999 arm7_9->read_core_regs(target, 0xffff, context_p);
1000
1001 arm7_9->read_xpsr(target, &cpsr, 0);
1002
1003 if ((retval = jtag_execute_queue()) != ERROR_OK)
1004 return retval;
1005
1006 /* if the core has been executing in Thumb state, set the T bit */
1007 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1008 cpsr |= 0x20;
1009
1010 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1011 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1012 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1013
1014 armv4_5->core_mode = cpsr & 0x1f;
1015
1016 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1017 {
1018 target->state = TARGET_UNKNOWN;
1019 ERROR("cpsr contains invalid mode value - communication failure");
1020 return ERROR_TARGET_FAILURE;
1021 }
1022
1023 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1024
1025 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1026 {
1027 DEBUG("thumb state, applying fixups");
1028 context[0] = r0_thumb;
1029 context[15] = pc_thumb;
1030 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1031 {
1032 /* adjust value stored by STM */
1033 context[15] -= 3 * 4;
1034 }
1035
1036 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1037 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1038 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1039 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1040 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1041 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1042 else if (target->debug_reason == DBG_REASON_DBGRQ)
1043 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1044 else
1045 {
1046 ERROR("unknown debug reason: %i", target->debug_reason);
1047 }
1048
1049
1050 for (i=0; i<=15; i++)
1051 {
1052 DEBUG("r%i: 0x%8.8x", i, context[i]);
1053 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1054 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1055 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1056 }
1057
1058 DEBUG("entered debug state at PC 0x%x", context[15]);
1059
1060 /* exceptions other than USR & SYS have a saved program status register */
1061 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1062 {
1063 u32 spsr;
1064 arm7_9->read_xpsr(target, &spsr, 1);
1065 jtag_execute_queue();
1066 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1067 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1068 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1069 }
1070
1071 /* r0 and r15 (pc) have to be restored later */
1072 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1073 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1074
1075 if ((retval = jtag->execute_queue()) != ERROR_OK)
1076 return retval;
1077
1078 if (arm7_9->post_debug_entry)
1079 arm7_9->post_debug_entry(target);
1080
1081 return ERROR_OK;
1082 }
1083
1084 int arm7_9_full_context(target_t *target)
1085 {
1086 int i;
1087 int retval;
1088 armv4_5_common_t *armv4_5 = target->arch_info;
1089 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1090
1091 DEBUG("-");
1092
1093 if (target->state != TARGET_HALTED)
1094 {
1095 WARNING("target not halted");
1096 return ERROR_TARGET_NOT_HALTED;
1097 }
1098
1099 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1100 * SYS shares registers with User, so we don't touch SYS
1101 */
1102 for(i = 0; i < 6; i++)
1103 {
1104 u32 mask = 0;
1105 u32* reg_p[16];
1106 int j;
1107 int valid = 1;
1108
1109 /* check if there are invalid registers in the current mode
1110 */
1111 for (j = 0; j <= 16; j++)
1112 {
1113 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1114 valid = 0;
1115 }
1116
1117 if (!valid)
1118 {
1119 u32 tmp_cpsr;
1120
1121 /* change processor mode (and mask T bit) */
1122 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1123 tmp_cpsr |= armv4_5_number_to_mode(i);
1124 tmp_cpsr &= ~0x20;
1125 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1126
1127 for (j = 0; j < 15; j++)
1128 {
1129 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1130 {
1131 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1132 mask |= 1 << j;
1133 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1134 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1135 }
1136 }
1137
1138 /* if only the PSR is invalid, mask is all zeroes */
1139 if (mask)
1140 arm7_9->read_core_regs(target, mask, reg_p);
1141
1142 /* check if the PSR has to be read */
1143 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1144 {
1145 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1146 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1147 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1148 }
1149 }
1150 }
1151
1152 /* restore processor mode (mask T bit) */
1153 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1154
1155 if ((retval = jtag_execute_queue()) != ERROR_OK)
1156 {
1157 ERROR("JTAG failure");
1158 exit(-1);
1159 }
1160 return ERROR_OK;
1161 }
1162
1163 int arm7_9_restore_context(target_t *target)
1164 {
1165 armv4_5_common_t *armv4_5 = target->arch_info;
1166 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1167 reg_t *reg;
1168 armv4_5_core_reg_t *reg_arch_info;
1169 enum armv4_5_mode current_mode = armv4_5->core_mode;
1170 int i, j;
1171 int dirty;
1172 int mode_change;
1173
1174 DEBUG("-");
1175
1176 if (target->state != TARGET_HALTED)
1177 {
1178 WARNING("target not halted");
1179 return ERROR_TARGET_NOT_HALTED;
1180 }
1181
1182 if (arm7_9->pre_restore_context)
1183 arm7_9->pre_restore_context(target);
1184
1185 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1186 * SYS shares registers with User, so we don't touch SYS
1187 */
1188 for (i = 0; i < 6; i++)
1189 {
1190 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1191 dirty = 0;
1192 mode_change = 0;
1193 /* check if there are dirty registers in the current mode
1194 */
1195 for (j = 0; j <= 16; j++)
1196 {
1197 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1198 reg_arch_info = reg->arch_info;
1199 if (reg->dirty == 1)
1200 {
1201 if (reg->valid == 1)
1202 {
1203 dirty = 1;
1204 DEBUG("examining dirty reg: %s", reg->name);
1205 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1206 && (reg_arch_info->mode != current_mode)
1207 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1208 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1209 {
1210 mode_change = 1;
1211 DEBUG("require mode change");
1212 }
1213 }
1214 else
1215 {
1216 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1217 exit(-1);
1218 }
1219 }
1220 }
1221
1222 if (dirty)
1223 {
1224 u32 mask = 0x0;
1225 int num_regs = 0;
1226 u32 regs[16];
1227
1228 if (mode_change)
1229 {
1230 u32 tmp_cpsr;
1231
1232 /* change processor mode (mask T bit) */
1233 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1234 tmp_cpsr |= armv4_5_number_to_mode(i);
1235 tmp_cpsr &= ~0x20;
1236 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1237 current_mode = armv4_5_number_to_mode(i);
1238 }
1239
1240 for (j = 0; j <= 14; j++)
1241 {
1242 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1243 reg_arch_info = reg->arch_info;
1244
1245
1246 if (reg->dirty == 1)
1247 {
1248 regs[j] = buf_get_u32(reg->value, 0, 32);
1249 mask |= 1 << j;
1250 num_regs++;
1251 reg->dirty = 0;
1252 reg->valid = 1;
1253 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1254 }
1255 }
1256
1257 if (mask)
1258 {
1259 arm7_9->write_core_regs(target, mask, regs);
1260 }
1261
1262 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1263 reg_arch_info = reg->arch_info;
1264 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1265 {
1266 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1267 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1268 }
1269 }
1270 }
1271
1272 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1273 {
1274 /* restore processor mode (mask T bit) */
1275 u32 tmp_cpsr;
1276
1277 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1278 tmp_cpsr |= armv4_5_number_to_mode(i);
1279 tmp_cpsr &= ~0x20;
1280 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1281 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1282 }
1283 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1284 {
1285 /* CPSR has been changed, full restore necessary (mask T bit) */
1286 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1287 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1288 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1289 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1290 }
1291
1292 /* restore PC */
1293 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1294 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1295 armv4_5->core_cache->reg_list[15].dirty = 0;
1296
1297 if (arm7_9->post_restore_context)
1298 arm7_9->post_restore_context(target);
1299
1300 return ERROR_OK;
1301 }
1302
1303 int arm7_9_restart_core(struct target_s *target)
1304 {
1305 armv4_5_common_t *armv4_5 = target->arch_info;
1306 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1307 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1308
1309 /* set RESTART instruction */
1310 jtag_add_end_state(TAP_RTI);
1311 arm_jtag_set_instr(jtag_info, 0x4);
1312
1313 jtag_add_runtest(1, TAP_RTI);
1314 if ((jtag_execute_queue()) != ERROR_OK)
1315 {
1316 exit(-1);
1317 }
1318
1319 return ERROR_OK;
1320 }
1321
1322 void arm7_9_enable_watchpoints(struct target_s *target)
1323 {
1324 watchpoint_t *watchpoint = target->watchpoints;
1325
1326 while (watchpoint)
1327 {
1328 if (watchpoint->set == 0)
1329 arm7_9_set_watchpoint(target, watchpoint);
1330 watchpoint = watchpoint->next;
1331 }
1332 }
1333
1334 void arm7_9_enable_breakpoints(struct target_s *target)
1335 {
1336 breakpoint_t *breakpoint = target->breakpoints;
1337
1338 /* set any pending breakpoints */
1339 while (breakpoint)
1340 {
1341 if (breakpoint->set == 0)
1342 arm7_9_set_breakpoint(target, breakpoint);
1343 breakpoint = breakpoint->next;
1344 }
1345 }
1346
1347 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1348 {
1349 breakpoint_t *breakpoint = target->breakpoints;
1350 watchpoint_t *watchpoint = target->watchpoints;
1351
1352 /* set any pending breakpoints */
1353 while (breakpoint)
1354 {
1355 if (breakpoint->set != 0)
1356 arm7_9_unset_breakpoint(target, breakpoint);
1357 breakpoint = breakpoint->next;
1358 }
1359
1360 while (watchpoint)
1361 {
1362 if (watchpoint->set != 0)
1363 arm7_9_unset_watchpoint(target, watchpoint);
1364 watchpoint = watchpoint->next;
1365 }
1366 }
1367
1368 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1369 {
1370 armv4_5_common_t *armv4_5 = target->arch_info;
1371 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1372 breakpoint_t *breakpoint = target->breakpoints;
1373 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1374
1375 DEBUG("-");
1376
1377 if (target->state != TARGET_HALTED)
1378 {
1379 WARNING("target not halted");
1380 return ERROR_TARGET_NOT_HALTED;
1381 }
1382
1383 if (!debug_execution)
1384 {
1385 target_free_all_working_areas(target);
1386 }
1387
1388 /* current = 1: continue on current pc, otherwise continue at <address> */
1389 if (!current)
1390 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1391
1392 /* the front-end may request us not to handle breakpoints */
1393 if (handle_breakpoints)
1394 {
1395 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1396 {
1397 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1398 arm7_9_unset_breakpoint(target, breakpoint);
1399
1400 DEBUG("enable single-step");
1401 arm7_9->enable_single_step(target);
1402
1403 target->debug_reason = DBG_REASON_SINGLESTEP;
1404
1405 arm7_9_restore_context(target);
1406
1407 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1408 arm7_9->branch_resume(target);
1409 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1410 {
1411 arm7_9->branch_resume_thumb(target);
1412 }
1413 else
1414 {
1415 ERROR("unhandled core state");
1416 exit(-1);
1417 }
1418
1419 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1420 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1421 arm7_9_execute_sys_speed(target);
1422
1423 DEBUG("disable single-step");
1424 arm7_9->disable_single_step(target);
1425
1426 arm7_9_debug_entry(target);
1427 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1428
1429 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1430 arm7_9_set_breakpoint(target, breakpoint);
1431 }
1432 }
1433
1434 /* enable any pending breakpoints and watchpoints */
1435 arm7_9_enable_breakpoints(target);
1436 arm7_9_enable_watchpoints(target);
1437
1438 arm7_9_restore_context(target);
1439
1440 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1441 {
1442 arm7_9->branch_resume(target);
1443 }
1444 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1445 {
1446 arm7_9->branch_resume_thumb(target);
1447 }
1448 else
1449 {
1450 ERROR("unhandled core state");
1451 exit(-1);
1452 }
1453
1454 /* deassert DBGACK and INTDIS */
1455 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1456 /* INTDIS only when we really resume, not during debug execution */
1457 if (!debug_execution)
1458 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1459 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1460
1461 arm7_9_restart_core(target);
1462
1463 target->debug_reason = DBG_REASON_NOTHALTED;
1464
1465 if (!debug_execution)
1466 {
1467 /* registers are now invalid */
1468 armv4_5_invalidate_core_regs(target);
1469 target->state = TARGET_RUNNING;
1470 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1471 }
1472 else
1473 {
1474 target->state = TARGET_DEBUG_RUNNING;
1475 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1476 }
1477
1478 DEBUG("target resumed");
1479
1480 return ERROR_OK;
1481 }
1482
1483 void arm7_9_enable_eice_step(target_t *target)
1484 {
1485 armv4_5_common_t *armv4_5 = target->arch_info;
1486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1487
1488 /* setup an inverse breakpoint on the current PC
1489 * - comparator 1 matches the current address
1490 * - rangeout from comparator 1 is connected to comparator 0 rangein
1491 * - comparator 0 matches any address, as long as rangein is low */
1492 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1493 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1494 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1495 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1496 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1497 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1498 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1499 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1500 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1501 }
1502
1503 void arm7_9_disable_eice_step(target_t *target)
1504 {
1505 armv4_5_common_t *armv4_5 = target->arch_info;
1506 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1507
1508 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1509 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1510 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1511 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1512 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1513 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1514 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1515 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1516 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1517 }
1518
1519 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1520 {
1521 armv4_5_common_t *armv4_5 = target->arch_info;
1522 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1523 breakpoint_t *breakpoint = NULL;
1524
1525 if (target->state != TARGET_HALTED)
1526 {
1527 WARNING("target not halted");
1528 return ERROR_TARGET_NOT_HALTED;
1529 }
1530
1531 /* current = 1: continue on current pc, otherwise continue at <address> */
1532 if (!current)
1533 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1534
1535 /* the front-end may request us not to handle breakpoints */
1536 if (handle_breakpoints)
1537 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1538 arm7_9_unset_breakpoint(target, breakpoint);
1539
1540 target->debug_reason = DBG_REASON_SINGLESTEP;
1541
1542 arm7_9_restore_context(target);
1543
1544 arm7_9->enable_single_step(target);
1545
1546 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1547 {
1548 arm7_9->branch_resume(target);
1549 }
1550 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1551 {
1552 arm7_9->branch_resume_thumb(target);
1553 }
1554 else
1555 {
1556 ERROR("unhandled core state");
1557 exit(-1);
1558 }
1559
1560 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1561
1562 arm7_9_execute_sys_speed(target);
1563 arm7_9->disable_single_step(target);
1564
1565 /* registers are now invalid */
1566 armv4_5_invalidate_core_regs(target);
1567
1568 arm7_9_debug_entry(target);
1569
1570 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1571
1572 if (breakpoint)
1573 arm7_9_set_breakpoint(target, breakpoint);
1574
1575 DEBUG("target stepped");
1576
1577 return ERROR_OK;
1578
1579 }
1580
1581 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1582 {
1583 u32* reg_p[16];
1584 u32 value;
1585 int retval;
1586 armv4_5_common_t *armv4_5 = target->arch_info;
1587 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1588 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1589
1590 if ((num < 0) || (num > 16))
1591 return ERROR_INVALID_ARGUMENTS;
1592
1593 if ((mode != ARMV4_5_MODE_ANY)
1594 && (mode != armv4_5->core_mode)
1595 && (reg_mode != ARMV4_5_MODE_ANY))
1596 {
1597 u32 tmp_cpsr;
1598
1599 /* change processor mode (mask T bit) */
1600 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1601 tmp_cpsr |= mode;
1602 tmp_cpsr &= ~0x20;
1603 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1604 }
1605
1606 if ((num >= 0) && (num <= 15))
1607 {
1608 /* read a normal core register */
1609 reg_p[num] = &value;
1610
1611 arm7_9->read_core_regs(target, 1 << num, reg_p);
1612 }
1613 else
1614 {
1615 /* read a program status register
1616 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1617 */
1618 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1619 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1620
1621 arm7_9->read_xpsr(target, &value, spsr);
1622 }
1623
1624 if ((retval = jtag_execute_queue()) != ERROR_OK)
1625 {
1626 ERROR("JTAG failure");
1627 exit(-1);
1628 }
1629
1630 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1631 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1632 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1633
1634 if ((mode != ARMV4_5_MODE_ANY)
1635 && (mode != armv4_5->core_mode)
1636 && (reg_mode != ARMV4_5_MODE_ANY)) {
1637 /* restore processor mode (mask T bit) */
1638 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1639 }
1640
1641 return ERROR_OK;
1642
1643 }
1644
1645 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1646 {
1647 u32 reg[16];
1648 int retval;
1649 armv4_5_common_t *armv4_5 = target->arch_info;
1650 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1651 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1652
1653 if ((num < 0) || (num > 16))
1654 return ERROR_INVALID_ARGUMENTS;
1655
1656 if ((mode != ARMV4_5_MODE_ANY)
1657 && (mode != armv4_5->core_mode)
1658 && (reg_mode != ARMV4_5_MODE_ANY)) {
1659 u32 tmp_cpsr;
1660
1661 /* change processor mode (mask T bit) */
1662 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1663 tmp_cpsr |= mode;
1664 tmp_cpsr &= ~0x20;
1665 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1666 }
1667
1668 if ((num >= 0) && (num <= 15))
1669 {
1670 /* write a normal core register */
1671 reg[num] = value;
1672
1673 arm7_9->write_core_regs(target, 1 << num, reg);
1674 }
1675 else
1676 {
1677 /* write a program status register
1678 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1679 */
1680 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1681 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1682
1683 /* if we're writing the CPSR, mask the T bit */
1684 if (!spsr)
1685 value &= ~0x20;
1686
1687 arm7_9->write_xpsr(target, value, spsr);
1688 }
1689
1690 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1691 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1692
1693 if ((mode != ARMV4_5_MODE_ANY)
1694 && (mode != armv4_5->core_mode)
1695 && (reg_mode != ARMV4_5_MODE_ANY)) {
1696 /* restore processor mode (mask T bit) */
1697 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1698 }
1699
1700 if ((retval = jtag_execute_queue()) != ERROR_OK)
1701 {
1702 ERROR("JTAG failure");
1703 exit(-1);
1704 }
1705
1706 return ERROR_OK;
1707
1708 }
1709
1710 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1711 {
1712 armv4_5_common_t *armv4_5 = target->arch_info;
1713 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1714
1715 u32 reg[16];
1716 int num_accesses = 0;
1717 int thisrun_accesses;
1718 int i;
1719 u32 cpsr;
1720 int retval;
1721 int last_reg = 0;
1722
1723 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1724
1725 if (target->state != TARGET_HALTED)
1726 {
1727 WARNING("target not halted");
1728 return ERROR_TARGET_NOT_HALTED;
1729 }
1730
1731 /* sanitize arguments */
1732 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1733 return ERROR_INVALID_ARGUMENTS;
1734
1735 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1736 return ERROR_TARGET_UNALIGNED_ACCESS;
1737
1738 /* load the base register with the address of the first word */
1739 reg[0] = address;
1740 arm7_9->write_core_regs(target, 0x1, reg);
1741
1742 switch (size)
1743 {
1744 case 4:
1745 while (num_accesses < count)
1746 {
1747 u32 reg_list;
1748 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1749 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1750
1751 if (last_reg <= thisrun_accesses)
1752 last_reg = thisrun_accesses;
1753
1754 arm7_9->load_word_regs(target, reg_list);
1755
1756 /* fast memory reads are only safe when the target is running
1757 * from a sufficiently high clock (32 kHz is usually too slow)
1758 */
1759 if (arm7_9->fast_memory_access)
1760 arm7_9_execute_fast_sys_speed(target);
1761 else
1762 arm7_9_execute_sys_speed(target);
1763
1764 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1765
1766 /* advance buffer, count number of accesses */
1767 buffer += thisrun_accesses * 4;
1768 num_accesses += thisrun_accesses;
1769 }
1770 break;
1771 case 2:
1772 while (num_accesses < count)
1773 {
1774 u32 reg_list;
1775 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1776 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1777
1778 for (i = 1; i <= thisrun_accesses; i++)
1779 {
1780 if (i > last_reg)
1781 last_reg = i;
1782 arm7_9->load_hword_reg(target, i);
1783 /* fast memory reads are only safe when the target is running
1784 * from a sufficiently high clock (32 kHz is usually too slow)
1785 */
1786 if (arm7_9->fast_memory_access)
1787 arm7_9_execute_fast_sys_speed(target);
1788 else
1789 arm7_9_execute_sys_speed(target);
1790 }
1791
1792 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1793
1794 /* advance buffer, count number of accesses */
1795 buffer += thisrun_accesses * 2;
1796 num_accesses += thisrun_accesses;
1797 }
1798 break;
1799 case 1:
1800 while (num_accesses < count)
1801 {
1802 u32 reg_list;
1803 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1804 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1805
1806 for (i = 1; i <= thisrun_accesses; i++)
1807 {
1808 if (i > last_reg)
1809 last_reg = i;
1810 arm7_9->load_byte_reg(target, i);
1811 /* fast memory reads are only safe when the target is running
1812 * from a sufficiently high clock (32 kHz is usually too slow)
1813 */
1814 if (arm7_9->fast_memory_access)
1815 arm7_9_execute_fast_sys_speed(target);
1816 else
1817 arm7_9_execute_sys_speed(target);
1818 }
1819
1820 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1821
1822 /* advance buffer, count number of accesses */
1823 buffer += thisrun_accesses * 1;
1824 num_accesses += thisrun_accesses;
1825 }
1826 break;
1827 default:
1828 ERROR("BUG: we shouldn't get here");
1829 exit(-1);
1830 break;
1831 }
1832
1833 for (i=0; i<=last_reg; i++)
1834 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1835
1836 arm7_9->read_xpsr(target, &cpsr, 0);
1837 if ((retval = jtag_execute_queue()) != ERROR_OK)
1838 {
1839 ERROR("JTAG error while reading cpsr");
1840 exit(-1);
1841 }
1842
1843 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1844 {
1845 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1846
1847 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1848
1849 return ERROR_TARGET_DATA_ABORT;
1850 }
1851
1852 return ERROR_OK;
1853 }
1854
1855 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1856 {
1857 armv4_5_common_t *armv4_5 = target->arch_info;
1858 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1859 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1860
1861 u32 reg[16];
1862 int num_accesses = 0;
1863 int thisrun_accesses;
1864 int i;
1865 u32 cpsr;
1866 int retval;
1867 int last_reg = 0;
1868
1869 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1870
1871 if (target->state != TARGET_HALTED)
1872 {
1873 WARNING("target not halted");
1874 return ERROR_TARGET_NOT_HALTED;
1875 }
1876
1877 /* sanitize arguments */
1878 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1879 return ERROR_INVALID_ARGUMENTS;
1880
1881 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1882 return ERROR_TARGET_UNALIGNED_ACCESS;
1883
1884 /* load the base register with the address of the first word */
1885 reg[0] = address;
1886 arm7_9->write_core_regs(target, 0x1, reg);
1887
1888 /* Clear DBGACK, to make sure memory fetches work as expected */
1889 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1890 embeddedice_store_reg(dbg_ctrl);
1891
1892 switch (size)
1893 {
1894 case 4:
1895 while (num_accesses < count)
1896 {
1897 u32 reg_list;
1898 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1899 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1900
1901 for (i = 1; i <= thisrun_accesses; i++)
1902 {
1903 if (i > last_reg)
1904 last_reg = i;
1905 reg[i] = target_buffer_get_u32(target, buffer);
1906 buffer += 4;
1907 }
1908
1909 arm7_9->write_core_regs(target, reg_list, reg);
1910
1911 arm7_9->store_word_regs(target, reg_list);
1912
1913 /* fast memory writes are only safe when the target is running
1914 * from a sufficiently high clock (32 kHz is usually too slow)
1915 */
1916 if (arm7_9->fast_memory_access)
1917 arm7_9_execute_fast_sys_speed(target);
1918 else
1919 arm7_9_execute_sys_speed(target);
1920
1921 num_accesses += thisrun_accesses;
1922 }
1923 break;
1924 case 2:
1925 while (num_accesses < count)
1926 {
1927 u32 reg_list;
1928 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1929 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1930
1931 for (i = 1; i <= thisrun_accesses; i++)
1932 {
1933 if (i > last_reg)
1934 last_reg = i;
1935 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1936 buffer += 2;
1937 }
1938
1939 arm7_9->write_core_regs(target, reg_list, reg);
1940
1941 for (i = 1; i <= thisrun_accesses; i++)
1942 {
1943 arm7_9->store_hword_reg(target, i);
1944
1945 /* fast memory writes are only safe when the target is running
1946 * from a sufficiently high clock (32 kHz is usually too slow)
1947 */
1948 if (arm7_9->fast_memory_access)
1949 arm7_9_execute_fast_sys_speed(target);
1950 else
1951 arm7_9_execute_sys_speed(target);
1952 }
1953
1954 num_accesses += thisrun_accesses;
1955 }
1956 break;
1957 case 1:
1958 while (num_accesses < count)
1959 {
1960 u32 reg_list;
1961 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1962 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1963
1964 for (i = 1; i <= thisrun_accesses; i++)
1965 {
1966 if (i > last_reg)
1967 last_reg = i;
1968 reg[i] = *buffer++ & 0xff;
1969 }
1970
1971 arm7_9->write_core_regs(target, reg_list, reg);
1972
1973 for (i = 1; i <= thisrun_accesses; i++)
1974 {
1975 arm7_9->store_byte_reg(target, i);
1976 /* fast memory writes are only safe when the target is running
1977 * from a sufficiently high clock (32 kHz is usually too slow)
1978 */
1979 if (arm7_9->fast_memory_access)
1980 arm7_9_execute_fast_sys_speed(target);
1981 else
1982 arm7_9_execute_sys_speed(target);
1983 }
1984
1985 num_accesses += thisrun_accesses;
1986 }
1987 break;
1988 default:
1989 ERROR("BUG: we shouldn't get here");
1990 exit(-1);
1991 break;
1992 }
1993
1994 /* Re-Set DBGACK */
1995 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1996 embeddedice_store_reg(dbg_ctrl);
1997
1998 for (i=0; i<=last_reg; i++)
1999 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
2000
2001 arm7_9->read_xpsr(target, &cpsr, 0);
2002 if ((retval = jtag_execute_queue()) != ERROR_OK)
2003 {
2004 ERROR("JTAG error while reading cpsr");
2005 exit(-1);
2006 }
2007
2008 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2009 {
2010 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2011
2012 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2013
2014 return ERROR_TARGET_DATA_ABORT;
2015 }
2016
2017 return ERROR_OK;
2018 }
2019
2020 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2021 {
2022 armv4_5_common_t *armv4_5 = target->arch_info;
2023 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2024 enum armv4_5_state core_state = armv4_5->core_state;
2025 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2026 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2027 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2028 int i;
2029
2030 u32 dcc_code[] =
2031 {
2032 /* MRC TST BNE MRC STR B */
2033 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2034 };
2035
2036 if (!arm7_9->dcc_downloads)
2037 return target->type->write_memory(target, address, 4, count, buffer);
2038
2039 /* regrab previously allocated working_area, or allocate a new one */
2040 if (!arm7_9->dcc_working_area)
2041 {
2042 u8 dcc_code_buf[6 * 4];
2043
2044 /* make sure we have a working area */
2045 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2046 {
2047 INFO("no working area available, falling back to memory writes");
2048 return target->type->write_memory(target, address, 4, count, buffer);
2049 }
2050
2051 /* copy target instructions to target endianness */
2052 for (i = 0; i < 6; i++)
2053 {
2054 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2055 }
2056
2057 /* write DCC code to working area */
2058 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2059 }
2060
2061 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2062 armv4_5->core_cache->reg_list[0].valid = 1;
2063 armv4_5->core_cache->reg_list[0].dirty = 1;
2064 armv4_5->core_state = ARMV4_5_STATE_ARM;
2065
2066 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2067
2068 for (i = 0; i < count; i++)
2069 {
2070 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2071 buffer += 4;
2072 }
2073
2074 target->type->halt(target);
2075
2076 while (target->state != TARGET_HALTED)
2077 target->type->poll(target);
2078
2079 /* restore target state */
2080 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2081 armv4_5->core_cache->reg_list[0].valid = 1;
2082 armv4_5->core_cache->reg_list[0].dirty = 1;
2083 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2084 armv4_5->core_cache->reg_list[1].valid = 1;
2085 armv4_5->core_cache->reg_list[1].dirty = 1;
2086 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2087 armv4_5->core_cache->reg_list[15].valid = 1;
2088 armv4_5->core_cache->reg_list[15].dirty = 1;
2089 armv4_5->core_state = core_state;
2090
2091 return ERROR_OK;
2092 }
2093
2094 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2095 {
2096 command_t *arm7_9_cmd;
2097
2098 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2099
2100 register_command(cmd_ctx, arm7_9_cmd, "etm", handle_arm7_9_etm_command, COMMAND_CONFIG, NULL);
2101 register_command(cmd_ctx, arm7_9_cmd, "etb", handle_arm7_9_etb_command, COMMAND_CONFIG, NULL);
2102
2103 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2104 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2105
2106 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2107
2108 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2109 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2110 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2111 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2112 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2113 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2114 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2115 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2116 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2117 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2118
2119 armv4_5_register_commands(cmd_ctx);
2120
2121 return ERROR_OK;
2122 }
2123
2124 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2125 {
2126 u32 value;
2127 int spsr;
2128 int retval;
2129 target_t *target = get_current_target(cmd_ctx);
2130 armv4_5_common_t *armv4_5;
2131 arm7_9_common_t *arm7_9;
2132
2133 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2134 {
2135 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2136 return ERROR_OK;
2137 }
2138
2139 if (target->state != TARGET_HALTED)
2140 {
2141 command_print(cmd_ctx, "can't write registers while running");
2142 return ERROR_OK;
2143 }
2144
2145 if (argc < 2)
2146 {
2147 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2148 return ERROR_OK;
2149 }
2150
2151 value = strtoul(args[0], NULL, 0);
2152 spsr = strtol(args[1], NULL, 0);
2153
2154 /* if we're writing the CPSR, mask the T bit */
2155 if (!spsr)
2156 value &= ~0x20;
2157
2158 arm7_9->write_xpsr(target, value, spsr);
2159 if ((retval = jtag_execute_queue()) != ERROR_OK)
2160 {
2161 ERROR("JTAG error while writing to xpsr");
2162 exit(-1);
2163 }
2164
2165 return ERROR_OK;
2166 }
2167
2168 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2169 {
2170 u32 value;
2171 int rotate;
2172 int spsr;
2173 int retval;
2174 target_t *target = get_current_target(cmd_ctx);
2175 armv4_5_common_t *armv4_5;
2176 arm7_9_common_t *arm7_9;
2177
2178 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2179 {
2180 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2181 return ERROR_OK;
2182 }
2183
2184 if (target->state != TARGET_HALTED)
2185 {
2186 command_print(cmd_ctx, "can't write registers while running");
2187 return ERROR_OK;
2188 }
2189
2190 if (argc < 3)
2191 {
2192 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2193 return ERROR_OK;
2194 }
2195
2196 value = strtoul(args[0], NULL, 0);
2197 rotate = strtol(args[1], NULL, 0);
2198 spsr = strtol(args[2], NULL, 0);
2199
2200 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2201 if ((retval = jtag_execute_queue()) != ERROR_OK)
2202 {
2203 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2204 exit(-1);
2205 }
2206
2207 return ERROR_OK;
2208 }
2209
2210 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2211 {
2212 u32 value;
2213 u32 mode;
2214 int num;
2215 target_t *target = get_current_target(cmd_ctx);
2216 armv4_5_common_t *armv4_5;
2217 arm7_9_common_t *arm7_9;
2218
2219 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2220 {
2221 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2222 return ERROR_OK;
2223 }
2224
2225 if (target->state != TARGET_HALTED)
2226 {
2227 command_print(cmd_ctx, "can't write registers while running");
2228 return ERROR_OK;
2229 }
2230
2231 if (argc < 3)
2232 {
2233 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2234 return ERROR_OK;
2235 }
2236
2237 num = strtol(args[0], NULL, 0);
2238 mode = strtoul(args[1], NULL, 0);
2239 value = strtoul(args[2], NULL, 0);
2240
2241 arm7_9_write_core_reg(target, num, mode, value);
2242
2243 return ERROR_OK;
2244 }
2245
2246 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2247 {
2248 target_t *target = get_current_target(cmd_ctx);
2249 armv4_5_common_t *armv4_5;
2250 arm7_9_common_t *arm7_9;
2251
2252 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2253 {
2254 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2255 return ERROR_OK;
2256 }
2257
2258 if (argc == 0)
2259 {
2260 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2261 return ERROR_OK;
2262 }
2263
2264 if (strcmp("enable", args[0]) == 0)
2265 {
2266 if (arm7_9->sw_bkpts_use_wp)
2267 {
2268 arm7_9_enable_sw_bkpts(target);
2269 }
2270 else
2271 {
2272 arm7_9->sw_bkpts_enabled = 1;
2273 }
2274 }
2275 else if (strcmp("disable", args[0]) == 0)
2276 {
2277 if (arm7_9->sw_bkpts_use_wp)
2278 {
2279 arm7_9_disable_sw_bkpts(target);
2280 }
2281 else
2282 {
2283 arm7_9->sw_bkpts_enabled = 0;
2284 }
2285 }
2286 else
2287 {
2288 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2289 }
2290
2291 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2292
2293 return ERROR_OK;
2294 }
2295
2296 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2297 {
2298 target_t *target = get_current_target(cmd_ctx);
2299 armv4_5_common_t *armv4_5;
2300 arm7_9_common_t *arm7_9;
2301
2302 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2303 {
2304 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2305 return ERROR_OK;
2306 }
2307
2308 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2309 {
2310 arm7_9->force_hw_bkpts = 1;
2311 if (arm7_9->sw_bkpts_use_wp)
2312 {
2313 arm7_9_disable_sw_bkpts(target);
2314 }
2315 }
2316 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2317 {
2318 arm7_9->force_hw_bkpts = 0;
2319 }
2320 else
2321 {
2322 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2323 }
2324
2325 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2326
2327 return ERROR_OK;
2328 }
2329
2330 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2331 {
2332 target_t *target = get_current_target(cmd_ctx);
2333 armv4_5_common_t *armv4_5;
2334 arm7_9_common_t *arm7_9;
2335
2336 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2337 {
2338 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2339 return ERROR_OK;
2340 }
2341
2342 if (argc > 0)
2343 {
2344 if (strcmp("enable", args[0]) == 0)
2345 {
2346 arm7_9->use_dbgrq = 1;
2347 }
2348 else if (strcmp("disable", args[0]) == 0)
2349 {
2350 arm7_9->use_dbgrq = 0;
2351 }
2352 else
2353 {
2354 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2355 }
2356 }
2357
2358 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2359
2360 return ERROR_OK;
2361 }
2362
2363 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2364 {
2365 target_t *target = get_current_target(cmd_ctx);
2366 armv4_5_common_t *armv4_5;
2367 arm7_9_common_t *arm7_9;
2368
2369 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2370 {
2371 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2372 return ERROR_OK;
2373 }
2374
2375 if (argc > 0)
2376 {
2377 if (strcmp("enable", args[0]) == 0)
2378 {
2379 arm7_9->fast_memory_access = 1;
2380 }
2381 else if (strcmp("disable", args[0]) == 0)
2382 {
2383 arm7_9->fast_memory_access = 0;
2384 }
2385 else
2386 {
2387 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2388 }
2389 }
2390
2391 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2392
2393 return ERROR_OK;
2394 }
2395
2396 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2397 {
2398 target_t *target = get_current_target(cmd_ctx);
2399 armv4_5_common_t *armv4_5;
2400 arm7_9_common_t *arm7_9;
2401
2402 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2403 {
2404 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2405 return ERROR_OK;
2406 }
2407
2408 if (argc > 0)
2409 {
2410 if (strcmp("enable", args[0]) == 0)
2411 {
2412 arm7_9->dcc_downloads = 1;
2413 }
2414 else if (strcmp("disable", args[0]) == 0)
2415 {
2416 arm7_9->dcc_downloads = 0;
2417 }
2418 else
2419 {
2420 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2421 }
2422 }
2423
2424 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2425
2426 return ERROR_OK;
2427 }
2428
2429 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2430 {
2431 target_t *target;
2432 armv4_5_common_t *armv4_5;
2433 arm7_9_common_t *arm7_9;
2434
2435 if (argc != 1)
2436 {
2437 ERROR("incomplete 'arm7_9 etm <target>' command");
2438 exit(-1);
2439 }
2440
2441 target = get_target_by_num(strtoul(args[0], NULL, 0));
2442
2443 if (!target)
2444 {
2445 ERROR("target number '%s' not defined", args[0]);
2446 exit(-1);
2447 }
2448
2449 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2450 {
2451 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2452 return ERROR_OK;
2453 }
2454
2455 arm7_9->has_etm = 1;
2456
2457 return ERROR_OK;
2458 }
2459
2460 int handle_arm7_9_etb_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2461 {
2462 target_t *target;
2463 jtag_device_t *jtag_device;
2464 armv4_5_common_t *armv4_5;
2465 arm7_9_common_t *arm7_9;
2466
2467 if (argc != 2)
2468 {
2469 ERROR("incomplete 'arm7_9 etb <target> <chain_pos>' command");
2470 exit(-1);
2471 }
2472
2473 target = get_target_by_num(strtoul(args[0], NULL, 0));
2474
2475 if (!target)
2476 {
2477 ERROR("target number '%s' not defined", args[0]);
2478 exit(-1);
2479 }
2480
2481 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2482 {
2483 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2484 return ERROR_OK;
2485 }
2486
2487 jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
2488
2489 if (!jtag_device)
2490 {
2491 ERROR("jtag device number '%s' not defined", args[1]);
2492 exit(-1);
2493 }
2494
2495 arm7_9->etb = malloc(sizeof(etb_t));
2496
2497 arm7_9->etb->chain_pos = strtoul(args[1], NULL, 0);
2498 arm7_9->etb->cur_scan_chain = -1;
2499 arm7_9->etb->reg_cache = NULL;
2500
2501 return ERROR_OK;
2502 }
2503
2504 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2505 {
2506 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2507
2508 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2509
2510 arm_jtag_setup_connection(&arm7_9->jtag_info);
2511 arm7_9->wp_available = 2;
2512 arm7_9->wp0_used = 0;
2513 arm7_9->wp1_used = 0;
2514 arm7_9->force_hw_bkpts = 0;
2515 arm7_9->use_dbgrq = 0;
2516
2517 arm7_9->has_etm = 0;
2518 arm7_9->etb = NULL;
2519 arm7_9->has_single_step = 0;
2520 arm7_9->has_monitor_mode = 0;
2521 arm7_9->has_vector_catch = 0;
2522
2523 arm7_9->reinit_embeddedice = 0;
2524
2525 arm7_9->debug_entry_from_reset = 0;
2526
2527 arm7_9->dcc_working_area = NULL;
2528
2529 arm7_9->fast_memory_access = 0;
2530 arm7_9->dcc_downloads = 0;
2531
2532 jtag_register_event_callback(arm7_9_jtag_callback, target);
2533
2534 armv4_5->arch_info = arm7_9;
2535 armv4_5->read_core_reg = arm7_9_read_core_reg;
2536 armv4_5->write_core_reg = arm7_9_write_core_reg;
2537 armv4_5->full_context = arm7_9_full_context;
2538
2539 armv4_5_init_arch_info(target, armv4_5);
2540
2541 return ERROR_OK;
2542 }
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