target: don't implicitly include "breakpoint.h"
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifdef HAVE_CONFIG_H
30 #include "config.h"
31 #endif
32
33 #include "breakpoints.h"
34 #include "embeddedice.h"
35 #include "target_request.h"
36 #include "arm7_9_common.h"
37 #include "time_support.h"
38 #include "arm_simulator.h"
39
40
41 /**
42 * @file
43 * Hold common code supporting the ARM7 and ARM9 core generations.
44 *
45 * While the ARM core implementations evolved substantially during these
46 * two generations, they look quite similar from the JTAG perspective.
47 * Both have similar debug facilities, based on the same two scan chains
48 * providing access to the core and to an EmbeddedICE module. Both can
49 * support similar ETM and ETB modules, for tracing. And both expose
50 * what could be viewed as "ARM Classic", with multiple processor modes,
51 * shadowed registers, and support for the Thumb instruction set.
52 *
53 * Processor differences include things like presence or absence of MMU
54 * and cache, pipeline sizes, use of a modified Harvard Architecure
55 * (with separate instruction and data busses from the CPU), support
56 * for cpu clock gating during idle, and more.
57 */
58
59 static int arm7_9_debug_entry(struct target *target);
60
61 /**
62 * Clear watchpoints for an ARM7/9 target.
63 *
64 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
65 * @return JTAG error status after executing queue
66 */
67 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
68 {
69 LOG_DEBUG("-");
70 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
71 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
72 arm7_9->sw_breakpoint_count = 0;
73 arm7_9->sw_breakpoints_added = 0;
74 arm7_9->wp0_used = 0;
75 arm7_9->wp1_used = arm7_9->wp1_used_default;
76 arm7_9->wp_available = arm7_9->wp_available_max;
77
78 return jtag_execute_queue();
79 }
80
81 /**
82 * Assign a watchpoint to one of the two available hardware comparators in an
83 * ARM7 or ARM9 target.
84 *
85 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
86 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
87 */
88 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
89 {
90 if (!arm7_9->wp0_used)
91 {
92 arm7_9->wp0_used = 1;
93 breakpoint->set = 1;
94 arm7_9->wp_available--;
95 }
96 else if (!arm7_9->wp1_used)
97 {
98 arm7_9->wp1_used = 1;
99 breakpoint->set = 2;
100 arm7_9->wp_available--;
101 }
102 else
103 {
104 LOG_ERROR("BUG: no hardware comparator available");
105 }
106 LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
107 breakpoint->unique_id,
108 breakpoint->address,
109 breakpoint->set );
110 }
111
112 /**
113 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
114 *
115 * @param arm7_9 Pointer to common struct for ARM7/9 targets
116 * @return Error codes if there is a problem finding a watchpoint or the result
117 * of executing the JTAG queue
118 */
119 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
120 {
121 if (arm7_9->sw_breakpoints_added)
122 {
123 return ERROR_OK;
124 }
125 if (arm7_9->wp_available < 1)
126 {
127 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
128 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
129 }
130 arm7_9->wp_available--;
131
132 /* pick a breakpoint unit */
133 if (!arm7_9->wp0_used)
134 {
135 arm7_9->sw_breakpoints_added = 1;
136 arm7_9->wp0_used = 3;
137 } else if (!arm7_9->wp1_used)
138 {
139 arm7_9->sw_breakpoints_added = 2;
140 arm7_9->wp1_used = 3;
141 }
142 else
143 {
144 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
145 return ERROR_FAIL;
146 }
147
148 if (arm7_9->sw_breakpoints_added == 1)
149 {
150 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
151 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
152 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
153 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
154 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
155 }
156 else if (arm7_9->sw_breakpoints_added == 2)
157 {
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
163 }
164 else
165 {
166 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
167 return ERROR_FAIL;
168 }
169 LOG_DEBUG("SW BP using hw wp: %d",
170 arm7_9->sw_breakpoints_added );
171
172 return jtag_execute_queue();
173 }
174
175 /**
176 * Setup the common pieces for an ARM7/9 target after reset or on startup.
177 *
178 * @param target Pointer to an ARM7/9 target to setup
179 * @return Result of clearing the watchpoints on the target
180 */
181 int arm7_9_setup(struct target *target)
182 {
183 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
184
185 return arm7_9_clear_watchpoints(arm7_9);
186 }
187
188 /**
189 * Set either a hardware or software breakpoint on an ARM7/9 target. The
190 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
191 * might have erased the values in Embedded ICE.
192 *
193 * @param target Pointer to the target device to set the breakpoints on
194 * @param breakpoint Pointer to the breakpoint to be set
195 * @return For hardware breakpoints, this is the result of executing the JTAG
196 * queue. For software breakpoints, this will be the status of the
197 * required memory reads and writes
198 */
199 int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
200 {
201 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
202 int retval = ERROR_OK;
203
204 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
205 breakpoint->unique_id,
206 breakpoint->address,
207 breakpoint->type);
208
209 if (target->state != TARGET_HALTED)
210 {
211 LOG_WARNING("target not halted");
212 return ERROR_TARGET_NOT_HALTED;
213 }
214
215 if (breakpoint->type == BKPT_HARD)
216 {
217 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
218 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
219
220 /* reassign a hw breakpoint */
221 if (breakpoint->set == 0)
222 {
223 arm7_9_assign_wp(arm7_9, breakpoint);
224 }
225
226 if (breakpoint->set == 1)
227 {
228 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
229 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
230 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
231 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
232 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
233 }
234 else if (breakpoint->set == 2)
235 {
236 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
237 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
239 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
240 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
241 }
242 else
243 {
244 LOG_ERROR("BUG: no hardware comparator available");
245 return ERROR_OK;
246 }
247
248 retval = jtag_execute_queue();
249 }
250 else if (breakpoint->type == BKPT_SOFT)
251 {
252 /* did we already set this breakpoint? */
253 if (breakpoint->set)
254 return ERROR_OK;
255
256 if (breakpoint->length == 4)
257 {
258 uint32_t verify = 0xffffffff;
259 /* keep the original instruction in target endianness */
260 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
261 {
262 return retval;
263 }
264 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
265 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
266 {
267 return retval;
268 }
269
270 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
271 {
272 return retval;
273 }
274 if (verify != arm7_9->arm_bkpt)
275 {
276 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
277 return ERROR_OK;
278 }
279 }
280 else
281 {
282 uint16_t verify = 0xffff;
283 /* keep the original instruction in target endianness */
284 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
285 {
286 return retval;
287 }
288 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
289 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
290 {
291 return retval;
292 }
293
294 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
295 {
296 return retval;
297 }
298 if (verify != arm7_9->thumb_bkpt)
299 {
300 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
301 return ERROR_OK;
302 }
303 }
304
305 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
306 return retval;
307
308 arm7_9->sw_breakpoint_count++;
309
310 breakpoint->set = 1;
311 }
312
313 return retval;
314 }
315
316 /**
317 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
318 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
319 * will be updated. Otherwise, the software breakpoint will be restored to its
320 * original instruction if it hasn't already been modified.
321 *
322 * @param target Pointer to ARM7/9 target to unset the breakpoint from
323 * @param breakpoint Pointer to breakpoint to be unset
324 * @return For hardware breakpoints, this is the result of executing the JTAG
325 * queue. For software breakpoints, this will be the status of the
326 * required memory reads and writes
327 */
328 int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
329 {
330 int retval = ERROR_OK;
331 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
332
333 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
334 breakpoint->unique_id,
335 breakpoint->address );
336
337 if (!breakpoint->set)
338 {
339 LOG_WARNING("breakpoint not set");
340 return ERROR_OK;
341 }
342
343 if (breakpoint->type == BKPT_HARD)
344 {
345 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
346 breakpoint->unique_id,
347 breakpoint->set );
348 if (breakpoint->set == 1)
349 {
350 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
351 arm7_9->wp0_used = 0;
352 arm7_9->wp_available++;
353 }
354 else if (breakpoint->set == 2)
355 {
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
357 arm7_9->wp1_used = 0;
358 arm7_9->wp_available++;
359 }
360 retval = jtag_execute_queue();
361 breakpoint->set = 0;
362 }
363 else
364 {
365 /* restore original instruction (kept in target endianness) */
366 if (breakpoint->length == 4)
367 {
368 uint32_t current_instr;
369 /* check that user program as not modified breakpoint instruction */
370 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
371 {
372 return retval;
373 }
374 if (current_instr == arm7_9->arm_bkpt)
375 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
376 {
377 return retval;
378 }
379 }
380 else
381 {
382 uint16_t current_instr;
383 /* check that user program as not modified breakpoint instruction */
384 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
385 {
386 return retval;
387 }
388 if (current_instr == arm7_9->thumb_bkpt)
389 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
390 {
391 return retval;
392 }
393 }
394
395 if (--arm7_9->sw_breakpoint_count==0)
396 {
397 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
398 if (arm7_9->sw_breakpoints_added == 1)
399 {
400 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
401 }
402 else if (arm7_9->sw_breakpoints_added == 2)
403 {
404 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
405 }
406 }
407
408 breakpoint->set = 0;
409 }
410
411 return retval;
412 }
413
414 /**
415 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
416 * dangling breakpoints and that the desired breakpoint can be added.
417 *
418 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
419 * @param breakpoint Pointer to the breakpoint to be added
420 * @return An error status if there is a problem adding the breakpoint or the
421 * result of setting the breakpoint
422 */
423 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
424 {
425 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
426
427 if (target->state != TARGET_HALTED)
428 {
429 LOG_WARNING("target not halted");
430 return ERROR_TARGET_NOT_HALTED;
431 }
432
433 if (arm7_9->breakpoint_count == 0)
434 {
435 /* make sure we don't have any dangling breakpoints. This is vital upon
436 * GDB connect/disconnect
437 */
438 arm7_9_clear_watchpoints(arm7_9);
439 }
440
441 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
442 {
443 LOG_INFO("no watchpoint unit available for hardware breakpoint");
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
445 }
446
447 if ((breakpoint->length != 2) && (breakpoint->length != 4))
448 {
449 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
450 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
451 }
452
453 if (breakpoint->type == BKPT_HARD)
454 {
455 arm7_9_assign_wp(arm7_9, breakpoint);
456 }
457
458 arm7_9->breakpoint_count++;
459
460 return arm7_9_set_breakpoint(target, breakpoint);
461 }
462
463 /**
464 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
465 * dangling breakpoints and updates available watchpoints if it is a hardware
466 * breakpoint.
467 *
468 * @param target Pointer to the target to have a breakpoint removed
469 * @param breakpoint Pointer to the breakpoint to be removed
470 * @return Error status if there was a problem unsetting the breakpoint or the
471 * watchpoints could not be cleared
472 */
473 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
474 {
475 int retval = ERROR_OK;
476 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
477
478 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
479 {
480 return retval;
481 }
482
483 if (breakpoint->type == BKPT_HARD)
484 arm7_9->wp_available++;
485
486 arm7_9->breakpoint_count--;
487 if (arm7_9->breakpoint_count == 0)
488 {
489 /* make sure we don't have any dangling breakpoints */
490 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
491 {
492 return retval;
493 }
494 }
495
496 return ERROR_OK;
497 }
498
499 /**
500 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
501 * considered a bug to call this function when there are no available watchpoint
502 * units.
503 *
504 * @param target Pointer to an ARM7/9 target to set a watchpoint on
505 * @param watchpoint Pointer to the watchpoint to be set
506 * @return Error status if watchpoint set fails or the result of executing the
507 * JTAG queue
508 */
509 int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
510 {
511 int retval = ERROR_OK;
512 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
513 int rw_mask = 1;
514 uint32_t mask;
515
516 mask = watchpoint->length - 1;
517
518 if (target->state != TARGET_HALTED)
519 {
520 LOG_WARNING("target not halted");
521 return ERROR_TARGET_NOT_HALTED;
522 }
523
524 if (watchpoint->rw == WPT_ACCESS)
525 rw_mask = 0;
526 else
527 rw_mask = 1;
528
529 if (!arm7_9->wp0_used)
530 {
531 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
532 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
533 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
534 if (watchpoint->mask != 0xffffffffu)
535 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
536 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
537 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
538
539 if ((retval = jtag_execute_queue()) != ERROR_OK)
540 {
541 return retval;
542 }
543 watchpoint->set = 1;
544 arm7_9->wp0_used = 2;
545 }
546 else if (!arm7_9->wp1_used)
547 {
548 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
549 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
550 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
551 if (watchpoint->mask != 0xffffffffu)
552 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
553 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
554 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
555
556 if ((retval = jtag_execute_queue()) != ERROR_OK)
557 {
558 return retval;
559 }
560 watchpoint->set = 2;
561 arm7_9->wp1_used = 2;
562 }
563 else
564 {
565 LOG_ERROR("BUG: no hardware comparator available");
566 return ERROR_OK;
567 }
568
569 return ERROR_OK;
570 }
571
572 /**
573 * Unset an existing watchpoint and clear the used watchpoint unit.
574 *
575 * @param target Pointer to the target to have the watchpoint removed
576 * @param watchpoint Pointer to the watchpoint to be removed
577 * @return Error status while trying to unset the watchpoint or the result of
578 * executing the JTAG queue
579 */
580 int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
581 {
582 int retval = ERROR_OK;
583 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
584
585 if (target->state != TARGET_HALTED)
586 {
587 LOG_WARNING("target not halted");
588 return ERROR_TARGET_NOT_HALTED;
589 }
590
591 if (!watchpoint->set)
592 {
593 LOG_WARNING("breakpoint not set");
594 return ERROR_OK;
595 }
596
597 if (watchpoint->set == 1)
598 {
599 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
600 if ((retval = jtag_execute_queue()) != ERROR_OK)
601 {
602 return retval;
603 }
604 arm7_9->wp0_used = 0;
605 }
606 else if (watchpoint->set == 2)
607 {
608 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
609 if ((retval = jtag_execute_queue()) != ERROR_OK)
610 {
611 return retval;
612 }
613 arm7_9->wp1_used = 0;
614 }
615 watchpoint->set = 0;
616
617 return ERROR_OK;
618 }
619
620 /**
621 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
622 * available, an error response is returned.
623 *
624 * @param target Pointer to the ARM7/9 target to add a watchpoint to
625 * @param watchpoint Pointer to the watchpoint to be added
626 * @return Error status while trying to add the watchpoint
627 */
628 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
629 {
630 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
631
632 if (target->state != TARGET_HALTED)
633 {
634 LOG_WARNING("target not halted");
635 return ERROR_TARGET_NOT_HALTED;
636 }
637
638 if (arm7_9->wp_available < 1)
639 {
640 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
641 }
642
643 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
644 {
645 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
646 }
647
648 arm7_9->wp_available--;
649
650 return ERROR_OK;
651 }
652
653 /**
654 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
655 * the used watchpoint unit will be reopened.
656 *
657 * @param target Pointer to the target to remove a watchpoint from
658 * @param watchpoint Pointer to the watchpoint to be removed
659 * @return Result of trying to unset the watchpoint
660 */
661 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
662 {
663 int retval = ERROR_OK;
664 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
665
666 if (watchpoint->set)
667 {
668 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
669 {
670 return retval;
671 }
672 }
673
674 arm7_9->wp_available++;
675
676 return ERROR_OK;
677 }
678
679 /**
680 * Restarts the target by sending a RESTART instruction and moving the JTAG
681 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
682 * asserted by the processor.
683 *
684 * @param target Pointer to target to issue commands to
685 * @return Error status if there is a timeout or a problem while executing the
686 * JTAG queue
687 */
688 int arm7_9_execute_sys_speed(struct target *target)
689 {
690 int retval;
691 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
692 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
693 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
694
695 /* set RESTART instruction */
696 jtag_set_end_state(TAP_IDLE);
697 if (arm7_9->need_bypass_before_restart) {
698 arm7_9->need_bypass_before_restart = 0;
699 arm_jtag_set_instr(jtag_info, 0xf, NULL);
700 }
701 arm_jtag_set_instr(jtag_info, 0x4, NULL);
702
703 long long then = timeval_ms();
704 int timeout;
705 while (!(timeout = ((timeval_ms()-then) > 1000)))
706 {
707 /* read debug status register */
708 embeddedice_read_reg(dbg_stat);
709 if ((retval = jtag_execute_queue()) != ERROR_OK)
710 return retval;
711 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
712 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
713 break;
714 if (debug_level >= 3)
715 {
716 alive_sleep(100);
717 } else
718 {
719 keep_alive();
720 }
721 }
722 if (timeout)
723 {
724 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
725 return ERROR_TARGET_TIMEOUT;
726 }
727
728 return ERROR_OK;
729 }
730
731 /**
732 * Restarts the target by sending a RESTART instruction and moving the JTAG
733 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
734 * waiting until they are.
735 *
736 * @param target Pointer to the target to issue commands to
737 * @return Always ERROR_OK
738 */
739 int arm7_9_execute_fast_sys_speed(struct target *target)
740 {
741 static int set = 0;
742 static uint8_t check_value[4], check_mask[4];
743
744 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
745 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
746 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
747
748 /* set RESTART instruction */
749 jtag_set_end_state(TAP_IDLE);
750 if (arm7_9->need_bypass_before_restart) {
751 arm7_9->need_bypass_before_restart = 0;
752 arm_jtag_set_instr(jtag_info, 0xf, NULL);
753 }
754 arm_jtag_set_instr(jtag_info, 0x4, NULL);
755
756 if (!set)
757 {
758 /* check for DBGACK and SYSCOMP set (others don't care) */
759
760 /* NB! These are constants that must be available until after next jtag_execute() and
761 * we evaluate the values upon first execution in lieu of setting up these constants
762 * during early setup.
763 * */
764 buf_set_u32(check_value, 0, 32, 0x9);
765 buf_set_u32(check_mask, 0, 32, 0x9);
766 set = 1;
767 }
768
769 /* read debug status register */
770 embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
771
772 return ERROR_OK;
773 }
774
775 /**
776 * Get some data from the ARM7/9 target.
777 *
778 * @param target Pointer to the ARM7/9 target to read data from
779 * @param size The number of 32bit words to be read
780 * @param buffer Pointer to the buffer that will hold the data
781 * @return The result of receiving data from the Embedded ICE unit
782 */
783 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
784 {
785 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
786 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
787 uint32_t *data;
788 int retval = ERROR_OK;
789 uint32_t i;
790
791 data = malloc(size * (sizeof(uint32_t)));
792
793 retval = embeddedice_receive(jtag_info, data, size);
794
795 /* return the 32-bit ints in the 8-bit array */
796 for (i = 0; i < size; i++)
797 {
798 h_u32_to_le(buffer + (i * 4), data[i]);
799 }
800
801 free(data);
802
803 return retval;
804 }
805
806 /**
807 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
808 * target is running and the DCC control register has the W bit high, this will
809 * execute the request on the target.
810 *
811 * @param priv Void pointer expected to be a struct target pointer
812 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
813 * from the Embedded ICE unit
814 */
815 int arm7_9_handle_target_request(void *priv)
816 {
817 int retval = ERROR_OK;
818 struct target *target = priv;
819 if (!target_was_examined(target))
820 return ERROR_OK;
821 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
822 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
823 struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
824
825 if (!target->dbg_msg_enabled)
826 return ERROR_OK;
827
828 if (target->state == TARGET_RUNNING)
829 {
830 /* read DCC control register */
831 embeddedice_read_reg(dcc_control);
832 if ((retval = jtag_execute_queue()) != ERROR_OK)
833 {
834 return retval;
835 }
836
837 /* check W bit */
838 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
839 {
840 uint32_t request;
841
842 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
843 {
844 return retval;
845 }
846 if ((retval = target_request(target, request)) != ERROR_OK)
847 {
848 return retval;
849 }
850 }
851 }
852
853 return ERROR_OK;
854 }
855
856 /**
857 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
858 * is manipulated to the right halted state based on its current state. This is
859 * what happens:
860 *
861 * <table>
862 * <tr><th > State</th><th > Action</th></tr>
863 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
864 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
865 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
866 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
867 * </table>
868 *
869 * If the target does not end up in the halted state, a warning is produced. If
870 * DBGACK is cleared, then the target is expected to either be running or
871 * running in debug.
872 *
873 * @param target Pointer to the ARM7/9 target to poll
874 * @return ERROR_OK or an error status if a command fails
875 */
876 int arm7_9_poll(struct target *target)
877 {
878 int retval;
879 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
880 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
881
882 /* read debug status register */
883 embeddedice_read_reg(dbg_stat);
884 if ((retval = jtag_execute_queue()) != ERROR_OK)
885 {
886 return retval;
887 }
888
889 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
890 {
891 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
892 if (target->state == TARGET_UNKNOWN)
893 {
894 /* Starting OpenOCD with target in debug-halt */
895 target->state = TARGET_RUNNING;
896 LOG_DEBUG("DBGACK already set during server startup.");
897 }
898 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
899 {
900 int check_pc = 0;
901 if (target->state == TARGET_RESET)
902 {
903 if (target->reset_halt)
904 {
905 enum reset_types jtag_reset_config = jtag_get_reset_config();
906 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
907 {
908 check_pc = 1;
909 }
910 }
911 }
912
913 target->state = TARGET_HALTED;
914
915 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
916 return retval;
917
918 if (check_pc)
919 {
920 struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
921 uint32_t t=*((uint32_t *)reg->value);
922 if (t != 0)
923 {
924 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
925 }
926 }
927
928 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
929 {
930 return retval;
931 }
932 }
933 if (target->state == TARGET_DEBUG_RUNNING)
934 {
935 target->state = TARGET_HALTED;
936 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
937 return retval;
938
939 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
940 {
941 return retval;
942 }
943 }
944 if (target->state != TARGET_HALTED)
945 {
946 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
947 }
948 }
949 else
950 {
951 if (target->state != TARGET_DEBUG_RUNNING)
952 target->state = TARGET_RUNNING;
953 }
954
955 return ERROR_OK;
956 }
957
958 /**
959 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
960 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
961 * affected) completely stop the JTAG clock while the core is held in reset
962 * (SRST). It isn't possible to program the halt condition once reset is
963 * asserted, hence a hook that allows the target to set up its reset-halt
964 * condition is setup prior to asserting reset.
965 *
966 * @param target Pointer to an ARM7/9 target to assert reset on
967 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
968 */
969 int arm7_9_assert_reset(struct target *target)
970 {
971 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
972
973 LOG_DEBUG("target->state: %s",
974 target_state_name(target));
975
976 enum reset_types jtag_reset_config = jtag_get_reset_config();
977 if (!(jtag_reset_config & RESET_HAS_SRST))
978 {
979 LOG_ERROR("Can't assert SRST");
980 return ERROR_FAIL;
981 }
982
983 /* At this point trst has been asserted/deasserted once. We would
984 * like to program EmbeddedICE while SRST is asserted, instead of
985 * depending on SRST to leave that module alone. However, many CPUs
986 * gate the JTAG clock while SRST is asserted; or JTAG may need
987 * clock stability guarantees (adaptive clocking might help).
988 *
989 * So we assume JTAG access during SRST is off the menu unless it's
990 * been specifically enabled.
991 */
992 bool srst_asserted = false;
993
994 if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
995 && (jtag_reset_config & RESET_SRST_NO_GATING))
996 {
997 jtag_add_reset(0, 1);
998 srst_asserted = true;
999 }
1000
1001 if (target->reset_halt)
1002 {
1003 /*
1004 * Some targets do not support communication while SRST is asserted. We need to
1005 * set up the reset vector catch here.
1006 *
1007 * If TRST is asserted, then these settings will be reset anyway, so setting them
1008 * here is harmless.
1009 */
1010 if (arm7_9->has_vector_catch)
1011 {
1012 /* program vector catch register to catch reset vector */
1013 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
1014
1015 /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1016 jtag_add_runtest(1, jtag_get_end_state());
1017 }
1018 else
1019 {
1020 /* program watchpoint unit to match on reset vector address */
1021 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1022 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
1023 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1024 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1025 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1026 }
1027 }
1028
1029 /* here we should issue an SRST only, but we may have to assert TRST as well */
1030 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1031 {
1032 jtag_add_reset(1, 1);
1033 } else if (!srst_asserted)
1034 {
1035 jtag_add_reset(0, 1);
1036 }
1037
1038 target->state = TARGET_RESET;
1039 jtag_add_sleep(50000);
1040
1041 armv4_5_invalidate_core_regs(target);
1042
1043 if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
1044 {
1045 /* debug entry was already prepared in arm7_9_assert_reset() */
1046 target->debug_reason = DBG_REASON_DBGRQ;
1047 }
1048
1049 return ERROR_OK;
1050 }
1051
1052 /**
1053 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1054 * and the target is being reset into a halt, a warning will be triggered
1055 * because it is not possible to reset into a halted mode in this case. The
1056 * target is halted using the target's functions.
1057 *
1058 * @param target Pointer to the target to have the reset deasserted
1059 * @return ERROR_OK or an error from polling or halting the target
1060 */
1061 int arm7_9_deassert_reset(struct target *target)
1062 {
1063 int retval = ERROR_OK;
1064 LOG_DEBUG("target->state: %s",
1065 target_state_name(target));
1066
1067 /* deassert reset lines */
1068 jtag_add_reset(0, 0);
1069
1070 enum reset_types jtag_reset_config = jtag_get_reset_config();
1071 if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1072 {
1073 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1074 /* set up embedded ice registers again */
1075 if ((retval = target_examine_one(target)) != ERROR_OK)
1076 return retval;
1077
1078 if ((retval = target_poll(target)) != ERROR_OK)
1079 {
1080 return retval;
1081 }
1082
1083 if ((retval = target_halt(target)) != ERROR_OK)
1084 {
1085 return retval;
1086 }
1087
1088 }
1089 return retval;
1090 }
1091
1092 /**
1093 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1094 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1095 * vector catch was used, it is restored. Otherwise, the control value is
1096 * restored and the watchpoint unit is restored if it was in use.
1097 *
1098 * @param target Pointer to the ARM7/9 target to have halt cleared
1099 * @return Always ERROR_OK
1100 */
1101 int arm7_9_clear_halt(struct target *target)
1102 {
1103 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1104 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1105
1106 /* we used DBGRQ only if we didn't come out of reset */
1107 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1108 {
1109 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1110 */
1111 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1112 embeddedice_store_reg(dbg_ctrl);
1113 }
1114 else
1115 {
1116 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1117 {
1118 /* if we came out of reset, and vector catch is supported, we used
1119 * vector catch to enter debug state
1120 * restore the register in that case
1121 */
1122 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1123 }
1124 else
1125 {
1126 /* restore registers if watchpoint unit 0 was in use
1127 */
1128 if (arm7_9->wp0_used)
1129 {
1130 if (arm7_9->debug_entry_from_reset)
1131 {
1132 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1133 }
1134 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1135 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1136 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1137 }
1138 /* control value always has to be restored, as it was either disabled,
1139 * or enabled with possibly different bits
1140 */
1141 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1142 }
1143 }
1144
1145 return ERROR_OK;
1146 }
1147
1148 /**
1149 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1150 * and then there is a wait until the processor shows the halt. This wait can
1151 * timeout and results in an error being returned. The software reset involves
1152 * clearing the halt, updating the debug control register, changing to ARM mode,
1153 * reset of the program counter, and reset of all of the registers.
1154 *
1155 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1156 * @return Error status if any of the commands fail, otherwise ERROR_OK
1157 */
1158 int arm7_9_soft_reset_halt(struct target *target)
1159 {
1160 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1161 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1162 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1163 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1164 int i;
1165 int retval;
1166
1167 /* FIX!!! replace some of this code with tcl commands
1168 *
1169 * halt # the halt command is synchronous
1170 * armv4_5 core_state arm
1171 *
1172 */
1173
1174 if ((retval = target_halt(target)) != ERROR_OK)
1175 return retval;
1176
1177 long long then = timeval_ms();
1178 int timeout;
1179 while (!(timeout = ((timeval_ms()-then) > 1000)))
1180 {
1181 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1182 break;
1183 embeddedice_read_reg(dbg_stat);
1184 if ((retval = jtag_execute_queue()) != ERROR_OK)
1185 return retval;
1186 if (debug_level >= 3)
1187 {
1188 alive_sleep(100);
1189 } else
1190 {
1191 keep_alive();
1192 }
1193 }
1194 if (timeout)
1195 {
1196 LOG_ERROR("Failed to halt CPU after 1 sec");
1197 return ERROR_TARGET_TIMEOUT;
1198 }
1199 target->state = TARGET_HALTED;
1200
1201 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1202 * ensure that DBGRQ is cleared
1203 */
1204 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1205 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1206 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1207 embeddedice_store_reg(dbg_ctrl);
1208
1209 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1210 {
1211 return retval;
1212 }
1213
1214 /* if the target is in Thumb state, change to ARM state */
1215 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1216 {
1217 uint32_t r0_thumb, pc_thumb;
1218 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1219 /* Entered debug from Thumb mode */
1220 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1221 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1222 }
1223
1224 /* all register content is now invalid */
1225 if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
1226 {
1227 return retval;
1228 }
1229
1230 /* SVC, ARM state, IRQ and FIQ disabled */
1231 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
1232 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1233 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1234
1235 /* start fetching from 0x0 */
1236 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1237 armv4_5->core_cache->reg_list[15].dirty = 1;
1238 armv4_5->core_cache->reg_list[15].valid = 1;
1239
1240 armv4_5->core_mode = ARMV4_5_MODE_SVC;
1241 armv4_5->core_state = ARMV4_5_STATE_ARM;
1242
1243 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1244 return ERROR_FAIL;
1245
1246 /* reset registers */
1247 for (i = 0; i <= 14; i++)
1248 {
1249 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
1250 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1251 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1252 }
1253
1254 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1255 {
1256 return retval;
1257 }
1258
1259 return ERROR_OK;
1260 }
1261
1262 /**
1263 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1264 * line or by programming a watchpoint to trigger on any address. It is
1265 * considered a bug to call this function while the target is in the
1266 * TARGET_RESET state.
1267 *
1268 * @param target Pointer to the ARM7/9 target to be halted
1269 * @return Always ERROR_OK
1270 */
1271 int arm7_9_halt(struct target *target)
1272 {
1273 if (target->state == TARGET_RESET)
1274 {
1275 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1276 return ERROR_OK;
1277 }
1278
1279 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1280 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1281
1282 LOG_DEBUG("target->state: %s",
1283 target_state_name(target));
1284
1285 if (target->state == TARGET_HALTED)
1286 {
1287 LOG_DEBUG("target was already halted");
1288 return ERROR_OK;
1289 }
1290
1291 if (target->state == TARGET_UNKNOWN)
1292 {
1293 LOG_WARNING("target was in unknown state when halt was requested");
1294 }
1295
1296 if (arm7_9->use_dbgrq)
1297 {
1298 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1299 */
1300 if (arm7_9->set_special_dbgrq) {
1301 arm7_9->set_special_dbgrq(target);
1302 } else {
1303 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1304 embeddedice_store_reg(dbg_ctrl);
1305 }
1306 }
1307 else
1308 {
1309 /* program watchpoint unit to match on any address
1310 */
1311 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1312 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1313 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1314 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1315 }
1316
1317 target->debug_reason = DBG_REASON_DBGRQ;
1318
1319 return ERROR_OK;
1320 }
1321
1322 /**
1323 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1324 * ARM. The JTAG queue is then executed and the reason for debug entry is
1325 * examined. Once done, the target is verified to be halted and the processor
1326 * is forced into ARM mode. The core registers are saved for the current core
1327 * mode and the program counter (register 15) is updated as needed. The core
1328 * registers and CPSR and SPSR are saved for restoration later.
1329 *
1330 * @param target Pointer to target that is entering debug mode
1331 * @return Error code if anything fails, otherwise ERROR_OK
1332 */
1333 static int arm7_9_debug_entry(struct target *target)
1334 {
1335 int i;
1336 uint32_t context[16];
1337 uint32_t* context_p[16];
1338 uint32_t r0_thumb, pc_thumb;
1339 uint32_t cpsr;
1340 int retval;
1341 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1342 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1343 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1344 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1345
1346 #ifdef _DEBUG_ARM7_9_
1347 LOG_DEBUG("-");
1348 #endif
1349
1350 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1351 * ensure that DBGRQ is cleared
1352 */
1353 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1354 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1355 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1356 embeddedice_store_reg(dbg_ctrl);
1357
1358 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1359 {
1360 return retval;
1361 }
1362
1363 if ((retval = jtag_execute_queue()) != ERROR_OK)
1364 {
1365 return retval;
1366 }
1367
1368 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1369 return retval;
1370
1371
1372 if (target->state != TARGET_HALTED)
1373 {
1374 LOG_WARNING("target not halted");
1375 return ERROR_TARGET_NOT_HALTED;
1376 }
1377
1378 /* if the target is in Thumb state, change to ARM state */
1379 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1380 {
1381 LOG_DEBUG("target entered debug from Thumb state");
1382 /* Entered debug from Thumb mode */
1383 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1384 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1385 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
1386 }
1387 else
1388 {
1389 LOG_DEBUG("target entered debug from ARM state");
1390 /* Entered debug from ARM mode */
1391 armv4_5->core_state = ARMV4_5_STATE_ARM;
1392 }
1393
1394 for (i = 0; i < 16; i++)
1395 context_p[i] = &context[i];
1396 /* save core registers (r0 - r15 of current core mode) */
1397 arm7_9->read_core_regs(target, 0xffff, context_p);
1398
1399 arm7_9->read_xpsr(target, &cpsr, 0);
1400
1401 if ((retval = jtag_execute_queue()) != ERROR_OK)
1402 return retval;
1403
1404 /* if the core has been executing in Thumb state, set the T bit */
1405 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1406 cpsr |= 0x20;
1407
1408 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1409 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1410 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1411
1412 armv4_5->core_mode = cpsr & 0x1f;
1413
1414 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1415 {
1416 target->state = TARGET_UNKNOWN;
1417 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1418 return ERROR_TARGET_FAILURE;
1419 }
1420
1421 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1422
1423 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1424 {
1425 LOG_DEBUG("thumb state, applying fixups");
1426 context[0] = r0_thumb;
1427 context[15] = pc_thumb;
1428 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1429 {
1430 /* adjust value stored by STM */
1431 context[15] -= 3 * 4;
1432 }
1433
1434 if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1435 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1436 else
1437 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1438
1439 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1440 return ERROR_FAIL;
1441
1442 for (i = 0; i <= 15; i++)
1443 {
1444 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1445 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1446 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1447 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1448 }
1449
1450 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1451
1452 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1453 return ERROR_FAIL;
1454
1455 /* exceptions other than USR & SYS have a saved program status register */
1456 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1457 {
1458 uint32_t spsr;
1459 arm7_9->read_xpsr(target, &spsr, 1);
1460 if ((retval = jtag_execute_queue()) != ERROR_OK)
1461 {
1462 return retval;
1463 }
1464 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1465 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1466 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1467 }
1468
1469 /* r0 and r15 (pc) have to be restored later */
1470 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1471 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1472
1473 if ((retval = jtag_execute_queue()) != ERROR_OK)
1474 return retval;
1475
1476 if (arm7_9->post_debug_entry)
1477 arm7_9->post_debug_entry(target);
1478
1479 return ERROR_OK;
1480 }
1481
1482 /**
1483 * Validate the full context for an ARM7/9 target in all processor modes. If
1484 * there are any invalid registers for the target, they will all be read. This
1485 * includes the PSR.
1486 *
1487 * @param target Pointer to the ARM7/9 target to capture the full context from
1488 * @return Error if the target is not halted, has an invalid core mode, or if
1489 * the JTAG queue fails to execute
1490 */
1491 int arm7_9_full_context(struct target *target)
1492 {
1493 int i;
1494 int retval;
1495 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1496 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1497
1498 LOG_DEBUG("-");
1499
1500 if (target->state != TARGET_HALTED)
1501 {
1502 LOG_WARNING("target not halted");
1503 return ERROR_TARGET_NOT_HALTED;
1504 }
1505
1506 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1507 return ERROR_FAIL;
1508
1509 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1510 * SYS shares registers with User, so we don't touch SYS
1511 */
1512 for (i = 0; i < 6; i++)
1513 {
1514 uint32_t mask = 0;
1515 uint32_t* reg_p[16];
1516 int j;
1517 int valid = 1;
1518
1519 /* check if there are invalid registers in the current mode
1520 */
1521 for (j = 0; j <= 16; j++)
1522 {
1523 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1524 valid = 0;
1525 }
1526
1527 if (!valid)
1528 {
1529 uint32_t tmp_cpsr;
1530
1531 /* change processor mode (and mask T bit) */
1532 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1533 tmp_cpsr |= armv4_5_number_to_mode(i);
1534 tmp_cpsr &= ~0x20;
1535 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1536
1537 for (j = 0; j < 15; j++)
1538 {
1539 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1540 {
1541 reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1542 mask |= 1 << j;
1543 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1544 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1545 }
1546 }
1547
1548 /* if only the PSR is invalid, mask is all zeroes */
1549 if (mask)
1550 arm7_9->read_core_regs(target, mask, reg_p);
1551
1552 /* check if the PSR has to be read */
1553 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1554 {
1555 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1556 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1557 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1558 }
1559 }
1560 }
1561
1562 /* restore processor mode (mask T bit) */
1563 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1564
1565 if ((retval = jtag_execute_queue()) != ERROR_OK)
1566 {
1567 return retval;
1568 }
1569 return ERROR_OK;
1570 }
1571
1572 /**
1573 * Restore the processor context on an ARM7/9 target. The full processor
1574 * context is analyzed to see if any of the registers are dirty on this end, but
1575 * have a valid new value. If this is the case, the processor is changed to the
1576 * appropriate mode and the new register values are written out to the
1577 * processor. If there happens to be a dirty register with an invalid value, an
1578 * error will be logged.
1579 *
1580 * @param target Pointer to the ARM7/9 target to have its context restored
1581 * @return Error status if the target is not halted or the core mode in the
1582 * armv4_5 struct is invalid.
1583 */
1584 int arm7_9_restore_context(struct target *target)
1585 {
1586 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1587 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1588 struct reg *reg;
1589 struct armv4_5_core_reg *reg_arch_info;
1590 enum armv4_5_mode current_mode = armv4_5->core_mode;
1591 int i, j;
1592 int dirty;
1593 int mode_change;
1594
1595 LOG_DEBUG("-");
1596
1597 if (target->state != TARGET_HALTED)
1598 {
1599 LOG_WARNING("target not halted");
1600 return ERROR_TARGET_NOT_HALTED;
1601 }
1602
1603 if (arm7_9->pre_restore_context)
1604 arm7_9->pre_restore_context(target);
1605
1606 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1607 return ERROR_FAIL;
1608
1609 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1610 * SYS shares registers with User, so we don't touch SYS
1611 */
1612 for (i = 0; i < 6; i++)
1613 {
1614 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1615 dirty = 0;
1616 mode_change = 0;
1617 /* check if there are dirty registers in the current mode
1618 */
1619 for (j = 0; j <= 16; j++)
1620 {
1621 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1622 reg_arch_info = reg->arch_info;
1623 if (reg->dirty == 1)
1624 {
1625 if (reg->valid == 1)
1626 {
1627 dirty = 1;
1628 LOG_DEBUG("examining dirty reg: %s", reg->name);
1629 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1630 && (reg_arch_info->mode != current_mode)
1631 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1632 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1633 {
1634 mode_change = 1;
1635 LOG_DEBUG("require mode change");
1636 }
1637 }
1638 else
1639 {
1640 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1641 }
1642 }
1643 }
1644
1645 if (dirty)
1646 {
1647 uint32_t mask = 0x0;
1648 int num_regs = 0;
1649 uint32_t regs[16];
1650
1651 if (mode_change)
1652 {
1653 uint32_t tmp_cpsr;
1654
1655 /* change processor mode (mask T bit) */
1656 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1657 tmp_cpsr |= armv4_5_number_to_mode(i);
1658 tmp_cpsr &= ~0x20;
1659 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1660 current_mode = armv4_5_number_to_mode(i);
1661 }
1662
1663 for (j = 0; j <= 14; j++)
1664 {
1665 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1666 reg_arch_info = reg->arch_info;
1667
1668
1669 if (reg->dirty == 1)
1670 {
1671 regs[j] = buf_get_u32(reg->value, 0, 32);
1672 mask |= 1 << j;
1673 num_regs++;
1674 reg->dirty = 0;
1675 reg->valid = 1;
1676 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]);
1677 }
1678 }
1679
1680 if (mask)
1681 {
1682 arm7_9->write_core_regs(target, mask, regs);
1683 }
1684
1685 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1686 reg_arch_info = reg->arch_info;
1687 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1688 {
1689 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1690 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1691 }
1692 }
1693 }
1694
1695 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1696 {
1697 /* restore processor mode (mask T bit) */
1698 uint32_t tmp_cpsr;
1699
1700 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1701 tmp_cpsr |= armv4_5_number_to_mode(i);
1702 tmp_cpsr &= ~0x20;
1703 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1704 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1705 }
1706 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1707 {
1708 /* CPSR has been changed, full restore necessary (mask T bit) */
1709 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1710 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1711 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1712 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1713 }
1714
1715 /* restore PC */
1716 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1717 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1718 armv4_5->core_cache->reg_list[15].dirty = 0;
1719
1720 if (arm7_9->post_restore_context)
1721 arm7_9->post_restore_context(target);
1722
1723 return ERROR_OK;
1724 }
1725
1726 /**
1727 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1728 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1729 * restart.
1730 *
1731 * @param target Pointer to the ARM7/9 target to be restarted
1732 * @return Result of executing the JTAG queue
1733 */
1734 int arm7_9_restart_core(struct target *target)
1735 {
1736 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1737 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1738
1739 /* set RESTART instruction */
1740 jtag_set_end_state(TAP_IDLE);
1741 if (arm7_9->need_bypass_before_restart) {
1742 arm7_9->need_bypass_before_restart = 0;
1743 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1744 }
1745 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1746
1747 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
1748 return jtag_execute_queue();
1749 }
1750
1751 /**
1752 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1753 * iterated through and are set on the target if they aren't already set.
1754 *
1755 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1756 */
1757 void arm7_9_enable_watchpoints(struct target *target)
1758 {
1759 struct watchpoint *watchpoint = target->watchpoints;
1760
1761 while (watchpoint)
1762 {
1763 if (watchpoint->set == 0)
1764 arm7_9_set_watchpoint(target, watchpoint);
1765 watchpoint = watchpoint->next;
1766 }
1767 }
1768
1769 /**
1770 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1771 * iterated through and are set on the target.
1772 *
1773 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1774 */
1775 void arm7_9_enable_breakpoints(struct target *target)
1776 {
1777 struct breakpoint *breakpoint = target->breakpoints;
1778
1779 /* set any pending breakpoints */
1780 while (breakpoint)
1781 {
1782 arm7_9_set_breakpoint(target, breakpoint);
1783 breakpoint = breakpoint->next;
1784 }
1785 }
1786
1787 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1788 {
1789 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1790 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1791 struct breakpoint *breakpoint = target->breakpoints;
1792 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1793 int err, retval = ERROR_OK;
1794
1795 LOG_DEBUG("-");
1796
1797 if (target->state != TARGET_HALTED)
1798 {
1799 LOG_WARNING("target not halted");
1800 return ERROR_TARGET_NOT_HALTED;
1801 }
1802
1803 if (!debug_execution)
1804 {
1805 target_free_all_working_areas(target);
1806 }
1807
1808 /* current = 1: continue on current pc, otherwise continue at <address> */
1809 if (!current)
1810 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1811
1812 uint32_t current_pc;
1813 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1814
1815 /* the front-end may request us not to handle breakpoints */
1816 if (handle_breakpoints)
1817 {
1818 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1819 {
1820 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1821 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1822 {
1823 return retval;
1824 }
1825
1826 /* calculate PC of next instruction */
1827 uint32_t next_pc;
1828 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1829 {
1830 uint32_t current_opcode;
1831 target_read_u32(target, current_pc, &current_opcode);
1832 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1833 return retval;
1834 }
1835
1836 LOG_DEBUG("enable single-step");
1837 arm7_9->enable_single_step(target, next_pc);
1838
1839 target->debug_reason = DBG_REASON_SINGLESTEP;
1840
1841 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1842 {
1843 return retval;
1844 }
1845
1846 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1847 arm7_9->branch_resume(target);
1848 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1849 {
1850 arm7_9->branch_resume_thumb(target);
1851 }
1852 else
1853 {
1854 LOG_ERROR("unhandled core state");
1855 return ERROR_FAIL;
1856 }
1857
1858 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1859 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1860 err = arm7_9_execute_sys_speed(target);
1861
1862 LOG_DEBUG("disable single-step");
1863 arm7_9->disable_single_step(target);
1864
1865 if (err != ERROR_OK)
1866 {
1867 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1868 {
1869 return retval;
1870 }
1871 target->state = TARGET_UNKNOWN;
1872 return err;
1873 }
1874
1875 arm7_9_debug_entry(target);
1876 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1877
1878 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1879 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1880 {
1881 return retval;
1882 }
1883 }
1884 }
1885
1886 /* enable any pending breakpoints and watchpoints */
1887 arm7_9_enable_breakpoints(target);
1888 arm7_9_enable_watchpoints(target);
1889
1890 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1891 {
1892 return retval;
1893 }
1894
1895 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1896 {
1897 arm7_9->branch_resume(target);
1898 }
1899 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1900 {
1901 arm7_9->branch_resume_thumb(target);
1902 }
1903 else
1904 {
1905 LOG_ERROR("unhandled core state");
1906 return ERROR_FAIL;
1907 }
1908
1909 /* deassert DBGACK and INTDIS */
1910 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1911 /* INTDIS only when we really resume, not during debug execution */
1912 if (!debug_execution)
1913 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1914 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1915
1916 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1917 {
1918 return retval;
1919 }
1920
1921 target->debug_reason = DBG_REASON_NOTHALTED;
1922
1923 if (!debug_execution)
1924 {
1925 /* registers are now invalid */
1926 armv4_5_invalidate_core_regs(target);
1927 target->state = TARGET_RUNNING;
1928 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1929 {
1930 return retval;
1931 }
1932 }
1933 else
1934 {
1935 target->state = TARGET_DEBUG_RUNNING;
1936 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1937 {
1938 return retval;
1939 }
1940 }
1941
1942 LOG_DEBUG("target resumed");
1943
1944 return ERROR_OK;
1945 }
1946
1947 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1948 {
1949 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1950 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1951 uint32_t current_pc;
1952 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1953
1954 if (next_pc != current_pc)
1955 {
1956 /* setup an inverse breakpoint on the current PC
1957 * - comparator 1 matches the current address
1958 * - rangeout from comparator 1 is connected to comparator 0 rangein
1959 * - comparator 0 matches any address, as long as rangein is low */
1960 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1961 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1962 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1963 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1964 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1965 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1966 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1967 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1968 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1969 }
1970 else
1971 {
1972 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1974 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1975 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1976 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1977 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1978 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1979 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1980 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1981 }
1982 }
1983
1984 void arm7_9_disable_eice_step(struct target *target)
1985 {
1986 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1987
1988 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1989 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1990 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1991 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1992 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1993 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1994 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1995 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1996 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1997 }
1998
1999 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2000 {
2001 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2002 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2003 struct breakpoint *breakpoint = NULL;
2004 int err, retval;
2005
2006 if (target->state != TARGET_HALTED)
2007 {
2008 LOG_WARNING("target not halted");
2009 return ERROR_TARGET_NOT_HALTED;
2010 }
2011
2012 /* current = 1: continue on current pc, otherwise continue at <address> */
2013 if (!current)
2014 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
2015
2016 uint32_t current_pc;
2017 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2018
2019 /* the front-end may request us not to handle breakpoints */
2020 if (handle_breakpoints)
2021 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
2022 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
2023 {
2024 return retval;
2025 }
2026
2027 target->debug_reason = DBG_REASON_SINGLESTEP;
2028
2029 /* calculate PC of next instruction */
2030 uint32_t next_pc;
2031 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2032 {
2033 uint32_t current_opcode;
2034 target_read_u32(target, current_pc, &current_opcode);
2035 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2036 return retval;
2037 }
2038
2039 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2040 {
2041 return retval;
2042 }
2043
2044 arm7_9->enable_single_step(target, next_pc);
2045
2046 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
2047 {
2048 arm7_9->branch_resume(target);
2049 }
2050 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
2051 {
2052 arm7_9->branch_resume_thumb(target);
2053 }
2054 else
2055 {
2056 LOG_ERROR("unhandled core state");
2057 return ERROR_FAIL;
2058 }
2059
2060 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2061 {
2062 return retval;
2063 }
2064
2065 err = arm7_9_execute_sys_speed(target);
2066 arm7_9->disable_single_step(target);
2067
2068 /* registers are now invalid */
2069 armv4_5_invalidate_core_regs(target);
2070
2071 if (err != ERROR_OK)
2072 {
2073 target->state = TARGET_UNKNOWN;
2074 } else {
2075 arm7_9_debug_entry(target);
2076 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2077 {
2078 return retval;
2079 }
2080 LOG_DEBUG("target stepped");
2081 }
2082
2083 if (breakpoint)
2084 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2085 {
2086 return retval;
2087 }
2088
2089 return err;
2090 }
2091
2092 int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
2093 {
2094 uint32_t* reg_p[16];
2095 uint32_t value;
2096 int retval;
2097 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2098 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2099
2100 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2101 return ERROR_FAIL;
2102
2103 enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
2104
2105 if ((num < 0) || (num > 16))
2106 return ERROR_INVALID_ARGUMENTS;
2107
2108 if ((mode != ARMV4_5_MODE_ANY)
2109 && (mode != armv4_5->core_mode)
2110 && (reg_mode != ARMV4_5_MODE_ANY))
2111 {
2112 uint32_t tmp_cpsr;
2113
2114 /* change processor mode (mask T bit) */
2115 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
2116 tmp_cpsr |= mode;
2117 tmp_cpsr &= ~0x20;
2118 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2119 }
2120
2121 if ((num >= 0) && (num <= 15))
2122 {
2123 /* read a normal core register */
2124 reg_p[num] = &value;
2125
2126 arm7_9->read_core_regs(target, 1 << num, reg_p);
2127 }
2128 else
2129 {
2130 /* read a program status register
2131 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2132 */
2133 struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
2134 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
2135
2136 arm7_9->read_xpsr(target, &value, spsr);
2137 }
2138
2139 if ((retval = jtag_execute_queue()) != ERROR_OK)
2140 {
2141 return retval;
2142 }
2143
2144 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
2145 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
2146 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
2147
2148 if ((mode != ARMV4_5_MODE_ANY)
2149 && (mode != armv4_5->core_mode)
2150 && (reg_mode != ARMV4_5_MODE_ANY)) {
2151 /* restore processor mode (mask T bit) */
2152 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2153 }
2154
2155 return ERROR_OK;
2156 }
2157
2158 int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value)
2159 {
2160 uint32_t reg[16];
2161 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2162 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2163
2164 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2165 return ERROR_FAIL;
2166
2167 enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
2168
2169 if ((num < 0) || (num > 16))
2170 return ERROR_INVALID_ARGUMENTS;
2171
2172 if ((mode != ARMV4_5_MODE_ANY)
2173 && (mode != armv4_5->core_mode)
2174 && (reg_mode != ARMV4_5_MODE_ANY)) {
2175 uint32_t tmp_cpsr;
2176
2177 /* change processor mode (mask T bit) */
2178 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
2179 tmp_cpsr |= mode;
2180 tmp_cpsr &= ~0x20;
2181 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2182 }
2183
2184 if ((num >= 0) && (num <= 15))
2185 {
2186 /* write a normal core register */
2187 reg[num] = value;
2188
2189 arm7_9->write_core_regs(target, 1 << num, reg);
2190 }
2191 else
2192 {
2193 /* write a program status register
2194 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2195 */
2196 struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
2197 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
2198
2199 /* if we're writing the CPSR, mask the T bit */
2200 if (!spsr)
2201 value &= ~0x20;
2202
2203 arm7_9->write_xpsr(target, value, spsr);
2204 }
2205
2206 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
2207 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
2208
2209 if ((mode != ARMV4_5_MODE_ANY)
2210 && (mode != armv4_5->core_mode)
2211 && (reg_mode != ARMV4_5_MODE_ANY)) {
2212 /* restore processor mode (mask T bit) */
2213 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2214 }
2215
2216 return jtag_execute_queue();
2217 }
2218
2219 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2220 {
2221 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2222 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2223 uint32_t reg[16];
2224 uint32_t num_accesses = 0;
2225 int thisrun_accesses;
2226 int i;
2227 uint32_t cpsr;
2228 int retval;
2229 int last_reg = 0;
2230
2231 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2232
2233 if (target->state != TARGET_HALTED)
2234 {
2235 LOG_WARNING("target not halted");
2236 return ERROR_TARGET_NOT_HALTED;
2237 }
2238
2239 /* sanitize arguments */
2240 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2241 return ERROR_INVALID_ARGUMENTS;
2242
2243 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2244 return ERROR_TARGET_UNALIGNED_ACCESS;
2245
2246 /* load the base register with the address of the first word */
2247 reg[0] = address;
2248 arm7_9->write_core_regs(target, 0x1, reg);
2249
2250 int j = 0;
2251
2252 switch (size)
2253 {
2254 case 4:
2255 while (num_accesses < count)
2256 {
2257 uint32_t reg_list;
2258 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2259 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2260
2261 if (last_reg <= thisrun_accesses)
2262 last_reg = thisrun_accesses;
2263
2264 arm7_9->load_word_regs(target, reg_list);
2265
2266 /* fast memory reads are only safe when the target is running
2267 * from a sufficiently high clock (32 kHz is usually too slow)
2268 */
2269 if (arm7_9->fast_memory_access)
2270 retval = arm7_9_execute_fast_sys_speed(target);
2271 else
2272 retval = arm7_9_execute_sys_speed(target);
2273 if (retval != ERROR_OK)
2274 return retval;
2275
2276 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2277
2278 /* advance buffer, count number of accesses */
2279 buffer += thisrun_accesses * 4;
2280 num_accesses += thisrun_accesses;
2281
2282 if ((j++%1024) == 0)
2283 {
2284 keep_alive();
2285 }
2286 }
2287 break;
2288 case 2:
2289 while (num_accesses < count)
2290 {
2291 uint32_t reg_list;
2292 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2293 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2294
2295 for (i = 1; i <= thisrun_accesses; i++)
2296 {
2297 if (i > last_reg)
2298 last_reg = i;
2299 arm7_9->load_hword_reg(target, i);
2300 /* fast memory reads are only safe when the target is running
2301 * from a sufficiently high clock (32 kHz is usually too slow)
2302 */
2303 if (arm7_9->fast_memory_access)
2304 retval = arm7_9_execute_fast_sys_speed(target);
2305 else
2306 retval = arm7_9_execute_sys_speed(target);
2307 if (retval != ERROR_OK)
2308 {
2309 return retval;
2310 }
2311
2312 }
2313
2314 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2315
2316 /* advance buffer, count number of accesses */
2317 buffer += thisrun_accesses * 2;
2318 num_accesses += thisrun_accesses;
2319
2320 if ((j++%1024) == 0)
2321 {
2322 keep_alive();
2323 }
2324 }
2325 break;
2326 case 1:
2327 while (num_accesses < count)
2328 {
2329 uint32_t reg_list;
2330 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2331 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2332
2333 for (i = 1; i <= thisrun_accesses; i++)
2334 {
2335 if (i > last_reg)
2336 last_reg = i;
2337 arm7_9->load_byte_reg(target, i);
2338 /* fast memory reads are only safe when the target is running
2339 * from a sufficiently high clock (32 kHz is usually too slow)
2340 */
2341 if (arm7_9->fast_memory_access)
2342 retval = arm7_9_execute_fast_sys_speed(target);
2343 else
2344 retval = arm7_9_execute_sys_speed(target);
2345 if (retval != ERROR_OK)
2346 {
2347 return retval;
2348 }
2349 }
2350
2351 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2352
2353 /* advance buffer, count number of accesses */
2354 buffer += thisrun_accesses * 1;
2355 num_accesses += thisrun_accesses;
2356
2357 if ((j++%1024) == 0)
2358 {
2359 keep_alive();
2360 }
2361 }
2362 break;
2363 default:
2364 LOG_ERROR("BUG: we shouldn't get here");
2365 exit(-1);
2366 break;
2367 }
2368
2369 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2370 return ERROR_FAIL;
2371
2372 for (i = 0; i <= last_reg; i++)
2373 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2374
2375 arm7_9->read_xpsr(target, &cpsr, 0);
2376 if ((retval = jtag_execute_queue()) != ERROR_OK)
2377 {
2378 LOG_ERROR("JTAG error while reading cpsr");
2379 return ERROR_TARGET_DATA_ABORT;
2380 }
2381
2382 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2383 {
2384 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2385
2386 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2387
2388 return ERROR_TARGET_DATA_ABORT;
2389 }
2390
2391 return ERROR_OK;
2392 }
2393
2394 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2395 {
2396 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2397 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2398 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2399
2400 uint32_t reg[16];
2401 uint32_t num_accesses = 0;
2402 int thisrun_accesses;
2403 int i;
2404 uint32_t cpsr;
2405 int retval;
2406 int last_reg = 0;
2407
2408 #ifdef _DEBUG_ARM7_9_
2409 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2410 #endif
2411
2412 if (target->state != TARGET_HALTED)
2413 {
2414 LOG_WARNING("target not halted");
2415 return ERROR_TARGET_NOT_HALTED;
2416 }
2417
2418 /* sanitize arguments */
2419 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2420 return ERROR_INVALID_ARGUMENTS;
2421
2422 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2423 return ERROR_TARGET_UNALIGNED_ACCESS;
2424
2425 /* load the base register with the address of the first word */
2426 reg[0] = address;
2427 arm7_9->write_core_regs(target, 0x1, reg);
2428
2429 /* Clear DBGACK, to make sure memory fetches work as expected */
2430 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2431 embeddedice_store_reg(dbg_ctrl);
2432
2433 switch (size)
2434 {
2435 case 4:
2436 while (num_accesses < count)
2437 {
2438 uint32_t reg_list;
2439 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2440 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2441
2442 for (i = 1; i <= thisrun_accesses; i++)
2443 {
2444 if (i > last_reg)
2445 last_reg = i;
2446 reg[i] = target_buffer_get_u32(target, buffer);
2447 buffer += 4;
2448 }
2449
2450 arm7_9->write_core_regs(target, reg_list, reg);
2451
2452 arm7_9->store_word_regs(target, reg_list);
2453
2454 /* fast memory writes are only safe when the target is running
2455 * from a sufficiently high clock (32 kHz is usually too slow)
2456 */
2457 if (arm7_9->fast_memory_access)
2458 retval = arm7_9_execute_fast_sys_speed(target);
2459 else
2460 retval = arm7_9_execute_sys_speed(target);
2461 if (retval != ERROR_OK)
2462 {
2463 return retval;
2464 }
2465
2466 num_accesses += thisrun_accesses;
2467 }
2468 break;
2469 case 2:
2470 while (num_accesses < count)
2471 {
2472 uint32_t reg_list;
2473 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2474 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2475
2476 for (i = 1; i <= thisrun_accesses; i++)
2477 {
2478 if (i > last_reg)
2479 last_reg = i;
2480 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2481 buffer += 2;
2482 }
2483
2484 arm7_9->write_core_regs(target, reg_list, reg);
2485
2486 for (i = 1; i <= thisrun_accesses; i++)
2487 {
2488 arm7_9->store_hword_reg(target, i);
2489
2490 /* fast memory writes are only safe when the target is running
2491 * from a sufficiently high clock (32 kHz is usually too slow)
2492 */
2493 if (arm7_9->fast_memory_access)
2494 retval = arm7_9_execute_fast_sys_speed(target);
2495 else
2496 retval = arm7_9_execute_sys_speed(target);
2497 if (retval != ERROR_OK)
2498 {
2499 return retval;
2500 }
2501 }
2502
2503 num_accesses += thisrun_accesses;
2504 }
2505 break;
2506 case 1:
2507 while (num_accesses < count)
2508 {
2509 uint32_t reg_list;
2510 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2511 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2512
2513 for (i = 1; i <= thisrun_accesses; i++)
2514 {
2515 if (i > last_reg)
2516 last_reg = i;
2517 reg[i] = *buffer++ & 0xff;
2518 }
2519
2520 arm7_9->write_core_regs(target, reg_list, reg);
2521
2522 for (i = 1; i <= thisrun_accesses; i++)
2523 {
2524 arm7_9->store_byte_reg(target, i);
2525 /* fast memory writes are only safe when the target is running
2526 * from a sufficiently high clock (32 kHz is usually too slow)
2527 */
2528 if (arm7_9->fast_memory_access)
2529 retval = arm7_9_execute_fast_sys_speed(target);
2530 else
2531 retval = arm7_9_execute_sys_speed(target);
2532 if (retval != ERROR_OK)
2533 {
2534 return retval;
2535 }
2536
2537 }
2538
2539 num_accesses += thisrun_accesses;
2540 }
2541 break;
2542 default:
2543 LOG_ERROR("BUG: we shouldn't get here");
2544 exit(-1);
2545 break;
2546 }
2547
2548 /* Re-Set DBGACK */
2549 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2550 embeddedice_store_reg(dbg_ctrl);
2551
2552 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2553 return ERROR_FAIL;
2554
2555 for (i = 0; i <= last_reg; i++)
2556 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2557
2558 arm7_9->read_xpsr(target, &cpsr, 0);
2559 if ((retval = jtag_execute_queue()) != ERROR_OK)
2560 {
2561 LOG_ERROR("JTAG error while reading cpsr");
2562 return ERROR_TARGET_DATA_ABORT;
2563 }
2564
2565 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2566 {
2567 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2568
2569 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2570
2571 return ERROR_TARGET_DATA_ABORT;
2572 }
2573
2574 return ERROR_OK;
2575 }
2576
2577 static int dcc_count;
2578 static uint8_t *dcc_buffer;
2579
2580 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2581 {
2582 int retval = ERROR_OK;
2583 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2584
2585 if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2586 return retval;
2587
2588 int little = target->endianness == TARGET_LITTLE_ENDIAN;
2589 int count = dcc_count;
2590 uint8_t *buffer = dcc_buffer;
2591 if (count > 2)
2592 {
2593 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2594 * core function repeated. */
2595 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2596 buffer += 4;
2597
2598 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2599 uint8_t reg_addr = ice_reg->addr & 0x1f;
2600 struct jtag_tap *tap;
2601 tap = ice_reg->jtag_info->tap;
2602
2603 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2604 buffer += (count-2)*4;
2605
2606 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2607 } else
2608 {
2609 int i;
2610 for (i = 0; i < count; i++)
2611 {
2612 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2613 buffer += 4;
2614 }
2615 }
2616
2617 if ((retval = target_halt(target))!= ERROR_OK)
2618 {
2619 return retval;
2620 }
2621 return target_wait_state(target, TARGET_HALTED, 500);
2622 }
2623
2624 static const uint32_t dcc_code[] =
2625 {
2626 /* r0 == input, points to memory buffer
2627 * r1 == scratch
2628 */
2629
2630 /* spin until DCC control (c0) reports data arrived */
2631 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2632 0xe3110001, /* tst r1, #1 */
2633 0x0afffffc, /* bne w */
2634
2635 /* read word from DCC (c1), write to memory */
2636 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2637 0xe4801004, /* str r1, [r0], #4 */
2638
2639 /* repeat */
2640 0xeafffff9 /* b w */
2641 };
2642
2643 int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
2644
2645 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
2646 {
2647 int retval;
2648 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2649 int i;
2650
2651 if (!arm7_9->dcc_downloads)
2652 return target_write_memory(target, address, 4, count, buffer);
2653
2654 /* regrab previously allocated working_area, or allocate a new one */
2655 if (!arm7_9->dcc_working_area)
2656 {
2657 uint8_t dcc_code_buf[6 * 4];
2658
2659 /* make sure we have a working area */
2660 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2661 {
2662 LOG_INFO("no working area available, falling back to memory writes");
2663 return target_write_memory(target, address, 4, count, buffer);
2664 }
2665
2666 /* copy target instructions to target endianness */
2667 for (i = 0; i < 6; i++)
2668 {
2669 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2670 }
2671
2672 /* write DCC code to working area */
2673 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2674 {
2675 return retval;
2676 }
2677 }
2678
2679 struct armv4_5_algorithm armv4_5_info;
2680 struct reg_param reg_params[1];
2681
2682 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2683 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2684 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2685
2686 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2687
2688 buf_set_u32(reg_params[0].value, 0, 32, address);
2689
2690 dcc_count = count;
2691 dcc_buffer = buffer;
2692 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2693 arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2694
2695 if (retval == ERROR_OK)
2696 {
2697 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2698 if (endaddress != (address + count*4))
2699 {
2700 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2701 retval = ERROR_FAIL;
2702 }
2703 }
2704
2705 destroy_reg_param(&reg_params[0]);
2706
2707 return retval;
2708 }
2709
2710 /**
2711 * Perform per-target setup that requires JTAG access.
2712 */
2713 int arm7_9_examine(struct target *target)
2714 {
2715 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2716 int retval;
2717
2718 if (!target_was_examined(target)) {
2719 struct reg_cache *t, **cache_p;
2720
2721 t = embeddedice_build_reg_cache(target, arm7_9);
2722 if (t == NULL)
2723 return ERROR_FAIL;
2724
2725 cache_p = register_get_last_cache_p(&target->reg_cache);
2726 (*cache_p) = t;
2727 arm7_9->eice_cache = (*cache_p);
2728
2729 if (arm7_9->armv4_5_common.etm)
2730 (*cache_p)->next = etm_build_reg_cache(target,
2731 &arm7_9->jtag_info,
2732 arm7_9->armv4_5_common.etm);
2733
2734 target_set_examined(target);
2735 }
2736
2737 retval = embeddedice_setup(target);
2738 if (retval == ERROR_OK)
2739 retval = arm7_9_setup(target);
2740 if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2741 retval = etm_setup(target);
2742 return retval;
2743 }
2744
2745
2746 COMMAND_HANDLER(handle_arm7_9_write_xpsr_command)
2747 {
2748 uint32_t value;
2749 int spsr;
2750 int retval;
2751 struct target *target = get_current_target(cmd_ctx);
2752 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2753
2754 if (!is_arm7_9(arm7_9))
2755 {
2756 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2757 return ERROR_TARGET_INVALID;
2758 }
2759
2760 if (target->state != TARGET_HALTED)
2761 {
2762 command_print(cmd_ctx, "can't write registers while running");
2763 return ERROR_FAIL;
2764 }
2765
2766 if (argc < 2)
2767 {
2768 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr | spsr>");
2769 return ERROR_FAIL;
2770 }
2771
2772 COMMAND_PARSE_NUMBER(u32, args[0], value);
2773 COMMAND_PARSE_NUMBER(int, args[1], spsr);
2774
2775 /* if we're writing the CPSR, mask the T bit */
2776 if (!spsr)
2777 value &= ~0x20;
2778
2779 arm7_9->write_xpsr(target, value, spsr);
2780 if ((retval = jtag_execute_queue()) != ERROR_OK)
2781 {
2782 LOG_ERROR("JTAG error while writing to xpsr");
2783 return retval;
2784 }
2785
2786 return ERROR_OK;
2787 }
2788
2789 COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command)
2790 {
2791 uint32_t value;
2792 int rotate;
2793 int spsr;
2794 int retval;
2795 struct target *target = get_current_target(cmd_ctx);
2796 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2797
2798 if (!is_arm7_9(arm7_9))
2799 {
2800 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2801 return ERROR_TARGET_INVALID;
2802 }
2803
2804 if (target->state != TARGET_HALTED)
2805 {
2806 command_print(cmd_ctx, "can't write registers while running");
2807 return ERROR_FAIL;
2808 }
2809
2810 if (argc < 3)
2811 {
2812 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
2813 return ERROR_FAIL;
2814 }
2815
2816 COMMAND_PARSE_NUMBER(u32, args[0], value);
2817 COMMAND_PARSE_NUMBER(int, args[1], rotate);
2818 COMMAND_PARSE_NUMBER(int, args[2], spsr);
2819
2820 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2821 if ((retval = jtag_execute_queue()) != ERROR_OK)
2822 {
2823 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2824 return retval;
2825 }
2826
2827 return ERROR_OK;
2828 }
2829
2830 COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
2831 {
2832 uint32_t value;
2833 uint32_t mode;
2834 int num;
2835 struct target *target = get_current_target(cmd_ctx);
2836 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2837
2838 if (!is_arm7_9(arm7_9))
2839 {
2840 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2841 return ERROR_TARGET_INVALID;
2842 }
2843
2844 if (target->state != TARGET_HALTED)
2845 {
2846 command_print(cmd_ctx, "can't write registers while running");
2847 return ERROR_FAIL;
2848 }
2849
2850 if (argc < 3)
2851 {
2852 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2853 return ERROR_FAIL;
2854 }
2855
2856 COMMAND_PARSE_NUMBER(int, args[0], num);
2857 COMMAND_PARSE_NUMBER(u32, args[1], mode);
2858 COMMAND_PARSE_NUMBER(u32, args[2], value);
2859
2860 return arm7_9_write_core_reg(target, num, mode, value);
2861 }
2862
2863 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2864 {
2865 struct target *target = get_current_target(cmd_ctx);
2866 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2867
2868 if (!is_arm7_9(arm7_9))
2869 {
2870 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2871 return ERROR_TARGET_INVALID;
2872 }
2873
2874 if (argc > 0)
2875 {
2876 if (strcmp("enable", args[0]) == 0)
2877 {
2878 arm7_9->use_dbgrq = 1;
2879 }
2880 else if (strcmp("disable", args[0]) == 0)
2881 {
2882 arm7_9->use_dbgrq = 0;
2883 }
2884 else
2885 {
2886 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable | disable>");
2887 }
2888 }
2889
2890 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2891
2892 return ERROR_OK;
2893 }
2894
2895 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2896 {
2897 struct target *target = get_current_target(cmd_ctx);
2898 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2899
2900 if (!is_arm7_9(arm7_9))
2901 {
2902 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2903 return ERROR_TARGET_INVALID;
2904 }
2905
2906 if (argc > 0)
2907 {
2908 if (strcmp("enable", args[0]) == 0)
2909 {
2910 arm7_9->fast_memory_access = 1;
2911 }
2912 else if (strcmp("disable", args[0]) == 0)
2913 {
2914 arm7_9->fast_memory_access = 0;
2915 }
2916 else
2917 {
2918 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable | disable>");
2919 }
2920 }
2921
2922 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2923
2924 return ERROR_OK;
2925 }
2926
2927 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2928 {
2929 struct target *target = get_current_target(cmd_ctx);
2930 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2931
2932 if (!is_arm7_9(arm7_9))
2933 {
2934 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2935 return ERROR_TARGET_INVALID;
2936 }
2937
2938 if (argc > 0)
2939 {
2940 if (strcmp("enable", args[0]) == 0)
2941 {
2942 arm7_9->dcc_downloads = 1;
2943 }
2944 else if (strcmp("disable", args[0]) == 0)
2945 {
2946 arm7_9->dcc_downloads = 0;
2947 }
2948 else
2949 {
2950 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable | disable>");
2951 }
2952 }
2953
2954 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2955
2956 return ERROR_OK;
2957 }
2958
2959 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2960 {
2961 int retval = ERROR_OK;
2962 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2963
2964 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2965
2966 if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2967 return retval;
2968
2969 /* caller must have allocated via calloc(), so everything's zeroed */
2970
2971 arm7_9->wp_available_max = 2;
2972
2973 arm7_9->fast_memory_access = fast_and_dangerous;
2974 arm7_9->dcc_downloads = fast_and_dangerous;
2975
2976 armv4_5->arch_info = arm7_9;
2977 armv4_5->read_core_reg = arm7_9_read_core_reg;
2978 armv4_5->write_core_reg = arm7_9_write_core_reg;
2979 armv4_5->full_context = arm7_9_full_context;
2980
2981 if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
2982 return retval;
2983
2984 return target_register_timer_callback(arm7_9_handle_target_request,
2985 1, 1, target);
2986 }
2987
2988 int arm7_9_register_commands(struct command_context *cmd_ctx)
2989 {
2990 struct command *arm7_9_cmd;
2991
2992 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
2993 NULL, COMMAND_ANY, "arm7/9 specific commands");
2994
2995 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr",
2996 handle_arm7_9_write_xpsr_command, COMMAND_EXEC,
2997 "write program status register <value> <not cpsr | spsr>");
2998 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8",
2999 handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC,
3000 "write program status register "
3001 "<8bit immediate> <rotate> <not cpsr | spsr>");
3002
3003 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg",
3004 handle_arm7_9_write_core_reg_command, COMMAND_EXEC,
3005 "write core register <num> <mode> <value>");
3006
3007 register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
3008 handle_arm7_9_dbgrq_command, COMMAND_ANY,
3009 "use EmbeddedICE dbgrq instead of breakpoint "
3010 "for target halt requests <enable | disable>");
3011 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access",
3012 handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
3013 "use fast memory accesses instead of slower "
3014 "but potentially safer accesses <enable | disable>");
3015 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads",
3016 handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
3017 "use DCC downloads for larger memory writes <enable | disable>");
3018
3019 armv4_5_register_commands(cmd_ctx);
3020
3021 etm_register_commands(cmd_ctx);
3022
3023 return ERROR_OK;
3024 }

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