1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm926ejs_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm926ejs_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm926ejs_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int arm926ejs_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm926ejs_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 int arm926ejs_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 /* forward declarations */
50 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
);
51 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm926ejs_quit(void);
53 int arm926ejs_arch_state(struct target_s
*target
);
54 int arm926ejs_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
56 int arm926ejs_soft_reset_halt(struct target_s
*target
);
57 static int arm926ejs_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
);
58 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
);
60 target_type_t arm926ejs_target
=
65 .arch_state
= arm926ejs_arch_state
,
67 .target_request_data
= arm7_9_target_request_data
,
70 .resume
= arm7_9_resume
,
73 .assert_reset
= arm7_9_assert_reset
,
74 .deassert_reset
= arm7_9_deassert_reset
,
75 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm7_9_read_memory
,
80 .write_memory
= arm926ejs_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
82 .checksum_memory
= arm7_9_checksum_memory
,
83 .blank_check_memory
= arm7_9_blank_check_memory
,
85 .run_algorithm
= armv4_5_run_algorithm
,
87 .add_breakpoint
= arm7_9_add_breakpoint
,
88 .remove_breakpoint
= arm7_9_remove_breakpoint
,
89 .add_watchpoint
= arm7_9_add_watchpoint
,
90 .remove_watchpoint
= arm7_9_remove_watchpoint
,
92 .register_commands
= arm926ejs_register_commands
,
93 .target_create
= arm926ejs_target_create
,
94 .init_target
= arm926ejs_init_target
,
95 .examine
= arm9tdmi_examine
,
96 .quit
= arm926ejs_quit
,
97 .virt2phys
= arm926ejs_virt2phys
,
101 int arm926ejs_catch_broken_irscan(u8
*captured
, void *priv
, scan_field_t
*field
)
103 /* The ARM926EJ-S' instruction register is 4 bits wide */
104 u8 t
= *captured
& 0xf;
105 u8 t2
= *field
->in_check_value
& 0xf;
110 else if ((t
== 0x0f) || (t
== 0x00))
112 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
115 return ERROR_JTAG_QUEUE_FAILED
;;
118 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
120 int arm926ejs_cp15_read(target_t
*target
, u32 op1
, u32 op2
, u32 CRn
, u32 CRm
, u32
*value
)
122 int retval
= ERROR_OK
;
123 armv4_5_common_t
*armv4_5
= target
->arch_info
;
124 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
125 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
126 u32 address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
127 scan_field_t fields
[4];
132 buf_set_u32(address_buf
, 0, 14, address
);
134 jtag_add_end_state(TAP_IDLE
);
135 if((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
139 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
141 fields
[0].tap
= jtag_info
->tap
;
142 fields
[0].num_bits
= 32;
143 fields
[0].out_value
= NULL
;
144 fields
[0].out_mask
= NULL
;
145 fields
[0].in_value
= NULL
;
146 fields
[0].in_check_value
= NULL
;
147 fields
[0].in_check_mask
= NULL
;
148 fields
[0].in_handler
= NULL
;
149 fields
[0].in_handler_priv
= NULL
;
151 fields
[1].tap
= jtag_info
->tap
;
152 fields
[1].num_bits
= 1;
153 fields
[1].out_value
= &access
;
154 fields
[1].out_mask
= NULL
;
155 fields
[1].in_value
= &access
;
156 fields
[1].in_check_value
= NULL
;
157 fields
[1].in_check_mask
= NULL
;
158 fields
[1].in_handler
= NULL
;
159 fields
[1].in_handler_priv
= NULL
;
161 fields
[2].tap
= jtag_info
->tap
;
162 fields
[2].num_bits
= 14;
163 fields
[2].out_value
= address_buf
;
164 fields
[2].out_mask
= NULL
;
165 fields
[2].in_value
= NULL
;
166 fields
[2].in_check_value
= NULL
;
167 fields
[2].in_check_mask
= NULL
;
168 fields
[2].in_handler
= NULL
;
169 fields
[2].in_handler_priv
= NULL
;
171 fields
[3].tap
= jtag_info
->tap
;
172 fields
[3].num_bits
= 1;
173 fields
[3].out_value
= &nr_w_buf
;
174 fields
[3].out_mask
= NULL
;
175 fields
[3].in_value
= NULL
;
176 fields
[3].in_check_value
= NULL
;
177 fields
[3].in_check_mask
= NULL
;
178 fields
[3].in_handler
= NULL
;
179 fields
[3].in_handler_priv
= NULL
;
181 jtag_add_dr_scan(4, fields
, -1);
183 fields
[0].in_handler_priv
= value
;
184 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
186 /*TODO: add timeout*/
189 /* rescan with NOP, to wait for the access to complete */
192 jtag_add_dr_scan(4, fields
, -1);
193 if((retval
= jtag_execute_queue()) != ERROR_OK
)
197 } while (buf_get_u32(&access
, 0, 1) != 1);
199 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
200 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
203 arm_jtag_set_instr(jtag_info
, 0xc, &arm926ejs_catch_broken_irscan
);
208 int arm926ejs_cp15_write(target_t
*target
, u32 op1
, u32 op2
, u32 CRn
, u32 CRm
, u32 value
)
210 int retval
= ERROR_OK
;
211 armv4_5_common_t
*armv4_5
= target
->arch_info
;
212 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
213 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
214 u32 address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
215 scan_field_t fields
[4];
221 buf_set_u32(address_buf
, 0, 14, address
);
222 buf_set_u32(value_buf
, 0, 32, value
);
224 jtag_add_end_state(TAP_IDLE
);
225 if((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
229 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
231 fields
[0].tap
= jtag_info
->tap
;
232 fields
[0].num_bits
= 32;
233 fields
[0].out_value
= value_buf
;
234 fields
[0].out_mask
= NULL
;
235 fields
[0].in_value
= NULL
;
236 fields
[0].in_check_value
= NULL
;
237 fields
[0].in_check_mask
= NULL
;
238 fields
[0].in_handler
= NULL
;
239 fields
[0].in_handler_priv
= NULL
;
241 fields
[1].tap
= jtag_info
->tap
;
242 fields
[1].num_bits
= 1;
243 fields
[1].out_value
= &access
;
244 fields
[1].out_mask
= NULL
;
245 fields
[1].in_value
= &access
;
246 fields
[1].in_check_value
= NULL
;
247 fields
[1].in_check_mask
= NULL
;
248 fields
[1].in_handler
= NULL
;
249 fields
[1].in_handler_priv
= NULL
;
251 fields
[2].tap
= jtag_info
->tap
;
252 fields
[2].num_bits
= 14;
253 fields
[2].out_value
= address_buf
;
254 fields
[2].out_mask
= NULL
;
255 fields
[2].in_value
= NULL
;
256 fields
[2].in_check_value
= NULL
;
257 fields
[2].in_check_mask
= NULL
;
258 fields
[2].in_handler
= NULL
;
259 fields
[2].in_handler_priv
= NULL
;
261 fields
[3].tap
= jtag_info
->tap
;
262 fields
[3].num_bits
= 1;
263 fields
[3].out_value
= &nr_w_buf
;
264 fields
[3].out_mask
= NULL
;
265 fields
[3].in_value
= NULL
;
266 fields
[3].in_check_value
= NULL
;
267 fields
[3].in_check_mask
= NULL
;
268 fields
[3].in_handler
= NULL
;
269 fields
[3].in_handler_priv
= NULL
;
271 jtag_add_dr_scan(4, fields
, -1);
272 /*TODO: add timeout*/
275 /* rescan with NOP, to wait for the access to complete */
278 jtag_add_dr_scan(4, fields
, -1);
279 if((retval
= jtag_execute_queue()) != ERROR_OK
)
283 } while (buf_get_u32(&access
, 0, 1) != 1);
285 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
286 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
289 arm_jtag_set_instr(jtag_info
, 0xf, &arm926ejs_catch_broken_irscan
);
294 int arm926ejs_examine_debug_reason(target_t
*target
)
296 armv4_5_common_t
*armv4_5
= target
->arch_info
;
297 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
298 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
302 embeddedice_read_reg(dbg_stat
);
303 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
306 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
308 switch (debug_reason
)
311 LOG_DEBUG("breakpoint from EICE unit 0");
312 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
315 LOG_DEBUG("breakpoint from EICE unit 1");
316 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
319 LOG_DEBUG("soft breakpoint (BKPT instruction)");
320 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
323 LOG_DEBUG("vector catch breakpoint");
324 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
327 LOG_DEBUG("external breakpoint");
328 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
331 LOG_DEBUG("watchpoint from EICE unit 0");
332 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
335 LOG_DEBUG("watchpoint from EICE unit 1");
336 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
339 LOG_DEBUG("external watchpoint");
340 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
343 LOG_DEBUG("internal debug request");
344 target
->debug_reason
= DBG_REASON_DBGRQ
;
347 LOG_DEBUG("external debug request");
348 target
->debug_reason
= DBG_REASON_DBGRQ
;
351 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
354 /* FIX!!!! here be dragons!!! We need to fail here so
355 * the target will interpreted as halted but we won't
356 * try to talk to it right now... a resume + halt seems
357 * to sync things up again. Please send an email to
358 * openocd development mailing list if you have hardware
359 * to donate to look into this problem....
361 LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
362 target
->debug_reason
= DBG_REASON_DBGRQ
;
363 retval
= ERROR_TARGET_FAILURE
;
366 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason
);
367 target
->debug_reason
= DBG_REASON_DBGRQ
;
368 /* if we fail here, we won't talk to the target and it will
369 * be reported to be in the halted state */
370 retval
= ERROR_TARGET_FAILURE
;
377 u32
arm926ejs_get_ttb(target_t
*target
)
379 armv4_5_common_t
*armv4_5
= target
->arch_info
;
380 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
381 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
382 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
386 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
392 void arm926ejs_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
394 armv4_5_common_t
*armv4_5
= target
->arch_info
;
395 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
396 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
397 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
400 /* read cp15 control register */
401 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
402 jtag_execute_queue();
407 arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
409 cp15_control
&= ~0x1U
;
415 /* read-modify-write CP15 debug override register
416 * to enable "test and clean all" */
417 arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
418 debug_override
|= 0x80000;
419 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
421 /* clean and invalidate DCache */
422 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
424 /* write CP15 debug override register
425 * to disable "test and clean all" */
426 debug_override
&= ~0x80000;
427 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
429 cp15_control
&= ~0x4U
;
434 /* invalidate ICache */
435 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
437 cp15_control
&= ~0x1000U
;
440 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
443 void arm926ejs_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
445 armv4_5_common_t
*armv4_5
= target
->arch_info
;
446 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
447 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
448 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
451 /* read cp15 control register */
452 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
453 jtag_execute_queue();
456 cp15_control
|= 0x1U
;
459 cp15_control
|= 0x4U
;
462 cp15_control
|= 0x1000U
;
464 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
467 void arm926ejs_post_debug_entry(target_t
*target
)
469 armv4_5_common_t
*armv4_5
= target
->arch_info
;
470 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
471 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
472 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
474 /* examine cp15 control reg */
475 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
476 jtag_execute_queue();
477 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs
->cp15_control_reg
);
479 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
482 /* identify caches */
483 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
484 jtag_execute_queue();
485 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
488 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
489 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
490 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
492 /* save i/d fault status and address register */
493 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
494 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
495 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
497 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
498 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
502 /* read-modify-write CP15 cache debug control register
503 * to disable I/D-cache linefills and force WT */
504 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
505 cache_dbg_ctrl
|= 0x7;
506 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
509 void arm926ejs_pre_restore_context(target_t
*target
)
511 armv4_5_common_t
*armv4_5
= target
->arch_info
;
512 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
513 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
514 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
516 /* restore i/d fault status and address register */
517 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
518 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
519 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
523 /* read-modify-write CP15 cache debug control register
524 * to reenable I/D-cache linefills and disable WT */
525 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
526 cache_dbg_ctrl
&= ~0x7;
527 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
530 int arm926ejs_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm926ejs_common_t
**arm926ejs_p
)
532 armv4_5_common_t
*armv4_5
= target
->arch_info
;
533 arm7_9_common_t
*arm7_9
;
534 arm9tdmi_common_t
*arm9tdmi
;
535 arm926ejs_common_t
*arm926ejs
;
537 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
542 arm7_9
= armv4_5
->arch_info
;
543 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
548 arm9tdmi
= arm7_9
->arch_info
;
549 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
554 arm926ejs
= arm9tdmi
->arch_info
;
555 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
560 *armv4_5_p
= armv4_5
;
562 *arm9tdmi_p
= arm9tdmi
;
563 *arm926ejs_p
= arm926ejs
;
568 int arm926ejs_arch_state(struct target_s
*target
)
570 armv4_5_common_t
*armv4_5
= target
->arch_info
;
571 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
572 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
573 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
577 "disabled", "enabled"
580 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
582 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
587 "target halted in %s state due to %s, current mode: %s\n"
588 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
589 "MMU: %s, D-Cache: %s, I-Cache: %s",
590 armv4_5_state_strings
[armv4_5
->core_state
],
591 Jim_Nvp_value2name_simple( nvp_target_debug_reason
,target
->debug_reason
)->name
,
592 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
593 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
594 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
595 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
596 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
597 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
602 int arm926ejs_soft_reset_halt(struct target_s
*target
)
604 int retval
= ERROR_OK
;
605 armv4_5_common_t
*armv4_5
= target
->arch_info
;
606 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
607 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
608 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
609 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
611 if((retval
= target_halt(target
)) != ERROR_OK
)
616 long long then
=timeval_ms();
618 while (!(timeout
=((timeval_ms()-then
)>1000)))
620 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
622 embeddedice_read_reg(dbg_stat
);
623 if((retval
= jtag_execute_queue()) != ERROR_OK
)
633 /* do not eat all CPU, time out after 1 se*/
642 LOG_ERROR("Failed to halt CPU after 1 sec");
643 return ERROR_TARGET_TIMEOUT
;
646 target
->state
= TARGET_HALTED
;
648 /* SVC, ARM state, IRQ and FIQ disabled */
649 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
650 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
651 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
653 /* start fetching from 0x0 */
654 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
655 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
656 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
658 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
659 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
661 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
662 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
663 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
664 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
666 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
669 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
672 armv4_5_common_t
*armv4_5
= target
->arch_info
;
673 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
674 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
675 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
677 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
680 /* If ICache is enabled, we have to invalidate affected ICache lines
681 * the DCache is forced to write-through, so we don't have to clean it here
683 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
687 /* invalidate ICache single entry with MVA */
688 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
692 /* invalidate ICache */
693 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
700 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
702 arm9tdmi_init_target(cmd_ctx
, target
);
707 int arm926ejs_quit(void)
712 int arm926ejs_init_arch_info(target_t
*target
, arm926ejs_common_t
*arm926ejs
, jtag_tap_t
*tap
)
714 arm9tdmi_common_t
*arm9tdmi
= &arm926ejs
->arm9tdmi_common
;
715 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
717 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
719 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
);
721 arm9tdmi
->arch_info
= arm926ejs
;
722 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
724 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
725 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
727 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
728 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
729 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
730 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
731 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
732 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
733 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
734 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
735 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
736 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
738 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
740 /* The ARM926EJ-S implements the ARMv5TE architecture which
741 * has the BKPT instruction, so we don't have to use a watchpoint comparator
743 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
744 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
749 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
)
751 arm926ejs_common_t
*arm926ejs
= calloc(1,sizeof(arm926ejs_common_t
));
753 arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
758 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
)
761 command_t
*arm926ejs_cmd
;
764 retval
= arm9tdmi_register_commands(cmd_ctx
);
766 arm926ejs_cmd
= register_command(cmd_ctx
, NULL
, "arm926ejs", NULL
, COMMAND_ANY
, "arm926ejs specific commands");
768 register_command(cmd_ctx
, arm926ejs_cmd
, "cp15", arm926ejs_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
770 register_command(cmd_ctx
, arm926ejs_cmd
, "cache_info", arm926ejs_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
771 register_command(cmd_ctx
, arm926ejs_cmd
, "virt2phys", arm926ejs_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
773 register_command(cmd_ctx
, arm926ejs_cmd
, "mdw_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
774 register_command(cmd_ctx
, arm926ejs_cmd
, "mdh_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
775 register_command(cmd_ctx
, arm926ejs_cmd
, "mdb_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
777 register_command(cmd_ctx
, arm926ejs_cmd
, "mww_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
778 register_command(cmd_ctx
, arm926ejs_cmd
, "mwh_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
779 register_command(cmd_ctx
, arm926ejs_cmd
, "mwb_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
784 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
787 target_t
*target
= get_current_target(cmd_ctx
);
788 armv4_5_common_t
*armv4_5
;
789 arm7_9_common_t
*arm7_9
;
790 arm9tdmi_common_t
*arm9tdmi
;
791 arm926ejs_common_t
*arm926ejs
;
797 if ((argc
< 4) || (argc
> 5))
799 command_print(cmd_ctx
, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
803 opcode_1
= strtoul(args
[0], NULL
, 0);
804 opcode_2
= strtoul(args
[1], NULL
, 0);
805 CRn
= strtoul(args
[2], NULL
, 0);
806 CRm
= strtoul(args
[3], NULL
, 0);
808 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
810 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
814 if (target
->state
!= TARGET_HALTED
)
816 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
823 if ((retval
= arm926ejs
->read_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, &value
)) != ERROR_OK
)
825 command_print(cmd_ctx
, "couldn't access register");
828 if((retval
= jtag_execute_queue()) != ERROR_OK
)
833 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
837 u32 value
= strtoul(args
[4], NULL
, 0);
838 if ((retval
= arm926ejs
->write_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, value
)) != ERROR_OK
)
840 command_print(cmd_ctx
, "couldn't access register");
843 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
849 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
851 target_t
*target
= get_current_target(cmd_ctx
);
852 armv4_5_common_t
*armv4_5
;
853 arm7_9_common_t
*arm7_9
;
854 arm9tdmi_common_t
*arm9tdmi
;
855 arm926ejs_common_t
*arm926ejs
;
857 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
859 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
863 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
866 int arm926ejs_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
868 target_t
*target
= get_current_target(cmd_ctx
);
869 armv4_5_common_t
*armv4_5
;
870 arm7_9_common_t
*arm7_9
;
871 arm9tdmi_common_t
*arm9tdmi
;
872 arm926ejs_common_t
*arm926ejs
;
873 arm_jtag_t
*jtag_info
;
875 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
877 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
881 jtag_info
= &arm7_9
->jtag_info
;
883 if (target
->state
!= TARGET_HALTED
)
885 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
889 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
892 int arm926ejs_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
894 target_t
*target
= get_current_target(cmd_ctx
);
895 armv4_5_common_t
*armv4_5
;
896 arm7_9_common_t
*arm7_9
;
897 arm9tdmi_common_t
*arm9tdmi
;
898 arm926ejs_common_t
*arm926ejs
;
899 arm_jtag_t
*jtag_info
;
901 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
903 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
907 jtag_info
= &arm7_9
->jtag_info
;
909 if (target
->state
!= TARGET_HALTED
)
911 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
915 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
918 int arm926ejs_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
920 target_t
*target
= get_current_target(cmd_ctx
);
921 armv4_5_common_t
*armv4_5
;
922 arm7_9_common_t
*arm7_9
;
923 arm9tdmi_common_t
*arm9tdmi
;
924 arm926ejs_common_t
*arm926ejs
;
925 arm_jtag_t
*jtag_info
;
927 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
929 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
933 jtag_info
= &arm7_9
->jtag_info
;
935 if (target
->state
!= TARGET_HALTED
)
937 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
941 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
944 static int arm926ejs_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
)
952 armv4_5_common_t
*armv4_5
;
953 arm7_9_common_t
*arm7_9
;
954 arm9tdmi_common_t
*arm9tdmi
;
955 arm926ejs_common_t
*arm926ejs
;
956 retval
= arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
);
957 if (retval
!= ERROR_OK
)
961 u32 ret
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
970 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
)
972 armv4_5_common_t
*armv4_5
= target
->arch_info
;
973 arm926ejs_common_t
*arm926ejs
= armv4_5
->arch_info
;
975 if (target
->state
!= TARGET_HALTED
)
977 LOG_ERROR("Target not halted");
978 return ERROR_TARGET_INVALID
;
980 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
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