1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm926ejs_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm926ejs_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm926ejs_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm926ejs_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int arm926ejs_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm926ejs_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm926ejs_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm926ejs_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
53 int arm926ejs_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
54 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm926ejs_soft_reset_halt(struct target_s
*target
);
57 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
59 target_type_t arm926ejs_target
=
64 .arch_state
= arm926ejs_arch_state
,
66 .target_request_data
= arm7_9_target_request_data
,
69 .resume
= arm7_9_resume
,
72 .assert_reset
= arm7_9_assert_reset
,
73 .deassert_reset
= arm7_9_deassert_reset
,
74 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
75 .prepare_reset_halt
= arm7_9_prepare_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm7_9_read_memory
,
80 .write_memory
= arm926ejs_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
82 .checksum_memory
= arm7_9_checksum_memory
,
84 .run_algorithm
= armv4_5_run_algorithm
,
86 .add_breakpoint
= arm7_9_add_breakpoint
,
87 .remove_breakpoint
= arm7_9_remove_breakpoint
,
88 .add_watchpoint
= arm7_9_add_watchpoint
,
89 .remove_watchpoint
= arm7_9_remove_watchpoint
,
91 .register_commands
= arm926ejs_register_commands
,
92 .target_command
= arm926ejs_target_command
,
93 .init_target
= arm926ejs_init_target
,
94 .quit
= arm926ejs_quit
98 int arm926ejs_catch_broken_irscan(u8
*captured
, void *priv
, scan_field_t
*field
)
100 u8
*in_value
=field
->in_check_value
;
102 /* The ARM926EJ-S' instruction register is 4 bits wide */
103 u8 t
=*in_value
& 0xf;
104 if ((t
== 0x0f) || (t
== 0x00))
106 DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
111 return ERROR_JTAG_QUEUE_FAILED
;
115 int arm926ejs_read_cp15(target_t
*target
, u32 address
, u32
*value
)
117 armv4_5_common_t
*armv4_5
= target
->arch_info
;
118 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
119 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
120 scan_field_t fields
[4];
125 buf_set_u32(address_buf
, 0, 14, address
);
127 jtag_add_end_state(TAP_RTI
);
128 arm_jtag_scann(jtag_info
, 0xf);
129 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
131 fields
[0].device
= jtag_info
->chain_pos
;
132 fields
[0].num_bits
= 32;
133 fields
[0].out_value
= NULL
;
134 fields
[0].out_mask
= NULL
;
135 fields
[0].in_value
= NULL
;
136 fields
[0].in_check_value
= NULL
;
137 fields
[0].in_check_mask
= NULL
;
138 fields
[0].in_handler
= NULL
;
139 fields
[0].in_handler_priv
= NULL
;
141 fields
[1].device
= jtag_info
->chain_pos
;
142 fields
[1].num_bits
= 1;
143 fields
[1].out_value
= &access
;
144 fields
[1].out_mask
= NULL
;
145 fields
[1].in_value
= &access
;
146 fields
[1].in_check_value
= NULL
;
147 fields
[1].in_check_mask
= NULL
;
148 fields
[1].in_handler
= NULL
;
149 fields
[1].in_handler_priv
= NULL
;
151 fields
[2].device
= jtag_info
->chain_pos
;
152 fields
[2].num_bits
= 14;
153 fields
[2].out_value
= address_buf
;
154 fields
[2].out_mask
= NULL
;
155 fields
[2].in_value
= NULL
;
156 fields
[2].in_check_value
= NULL
;
157 fields
[2].in_check_mask
= NULL
;
158 fields
[2].in_handler
= NULL
;
159 fields
[2].in_handler_priv
= NULL
;
161 fields
[3].device
= jtag_info
->chain_pos
;
162 fields
[3].num_bits
= 1;
163 fields
[3].out_value
= &nr_w_buf
;
164 fields
[3].out_mask
= NULL
;
165 fields
[3].in_value
= NULL
;
166 fields
[3].in_check_value
= NULL
;
167 fields
[3].in_check_mask
= NULL
;
168 fields
[3].in_handler
= NULL
;
169 fields
[3].in_handler_priv
= NULL
;
171 jtag_add_dr_scan(4, fields
, -1, NULL
);
173 fields
[0].in_handler_priv
= value
;
174 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
178 /* rescan with NOP, to wait for the access to complete */
181 jtag_add_dr_scan(4, fields
, -1, NULL
);
182 jtag_execute_queue();
183 } while (buf_get_u32(&access
, 0, 1) != 1);
185 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
186 DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
189 arm_jtag_set_instr(jtag_info
, 0xc, &arm926ejs_catch_broken_irscan
);
194 int arm926ejs_write_cp15(target_t
*target
, u32 address
, u32 value
)
196 armv4_5_common_t
*armv4_5
= target
->arch_info
;
197 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
198 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
199 scan_field_t fields
[4];
205 buf_set_u32(address_buf
, 0, 14, address
);
206 buf_set_u32(value_buf
, 0, 32, value
);
208 jtag_add_end_state(TAP_RTI
);
209 arm_jtag_scann(jtag_info
, 0xf);
210 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
212 fields
[0].device
= jtag_info
->chain_pos
;
213 fields
[0].num_bits
= 32;
214 fields
[0].out_value
= value_buf
;
215 fields
[0].out_mask
= NULL
;
216 fields
[0].in_value
= NULL
;
217 fields
[0].in_check_value
= NULL
;
218 fields
[0].in_check_mask
= NULL
;
219 fields
[0].in_handler
= NULL
;
220 fields
[0].in_handler_priv
= NULL
;
222 fields
[1].device
= jtag_info
->chain_pos
;
223 fields
[1].num_bits
= 1;
224 fields
[1].out_value
= &access
;
225 fields
[1].out_mask
= NULL
;
226 fields
[1].in_value
= &access
;
227 fields
[1].in_check_value
= NULL
;
228 fields
[1].in_check_mask
= NULL
;
229 fields
[1].in_handler
= NULL
;
230 fields
[1].in_handler_priv
= NULL
;
232 fields
[2].device
= jtag_info
->chain_pos
;
233 fields
[2].num_bits
= 14;
234 fields
[2].out_value
= address_buf
;
235 fields
[2].out_mask
= NULL
;
236 fields
[2].in_value
= NULL
;
237 fields
[2].in_check_value
= NULL
;
238 fields
[2].in_check_mask
= NULL
;
239 fields
[2].in_handler
= NULL
;
240 fields
[2].in_handler_priv
= NULL
;
242 fields
[3].device
= jtag_info
->chain_pos
;
243 fields
[3].num_bits
= 1;
244 fields
[3].out_value
= &nr_w_buf
;
245 fields
[3].out_mask
= NULL
;
246 fields
[3].in_value
= NULL
;
247 fields
[3].in_check_value
= NULL
;
248 fields
[3].in_check_mask
= NULL
;
249 fields
[3].in_handler
= NULL
;
250 fields
[3].in_handler_priv
= NULL
;
252 jtag_add_dr_scan(4, fields
, -1, NULL
);
256 /* rescan with NOP, to wait for the access to complete */
259 jtag_add_dr_scan(4, fields
, -1, NULL
);
260 jtag_execute_queue();
261 } while (buf_get_u32(&access
, 0, 1) != 1);
263 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
264 DEBUG("addr: 0x%x value: %8.8x", address
, value
);
267 arm_jtag_set_instr(jtag_info
, 0xf, &arm926ejs_catch_broken_irscan
);
272 int arm926ejs_examine_debug_reason(target_t
*target
)
274 armv4_5_common_t
*armv4_5
= target
->arch_info
;
275 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
276 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
280 embeddedice_read_reg(dbg_stat
);
281 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
284 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
286 switch (debug_reason
)
289 DEBUG("breakpoint from EICE unit 0");
290 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
293 DEBUG("breakpoint from EICE unit 1");
294 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
297 DEBUG("soft breakpoint (BKPT instruction)");
298 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
301 DEBUG("vector catch breakpoint");
302 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
305 DEBUG("external breakpoint");
306 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
309 DEBUG("watchpoint from EICE unit 0");
310 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
313 DEBUG("watchpoint from EICE unit 1");
314 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
317 DEBUG("external watchpoint");
318 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
321 DEBUG("internal debug request");
322 target
->debug_reason
= DBG_REASON_DBGRQ
;
325 DEBUG("external debug request");
326 target
->debug_reason
= DBG_REASON_DBGRQ
;
329 ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
332 ERROR("BUG: unknown debug reason: 0x%x", debug_reason
);
333 target
->debug_reason
= DBG_REASON_DBGRQ
;
339 u32
arm926ejs_get_ttb(target_t
*target
)
344 if ((retval
= arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb
)) != ERROR_OK
)
350 void arm926ejs_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
354 /* read cp15 control register */
355 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control
);
356 jtag_execute_queue();
361 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0);
363 cp15_control
&= ~0x1U
;
369 /* read-modify-write CP15 debug override register
370 * to enable "test and clean all" */
371 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override
);
372 debug_override
|= 0x80000;
373 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override
);
375 /* clean and invalidate DCache */
376 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
378 /* write CP15 debug override register
379 * to disable "test and clean all" */
380 debug_override
&= ~0x80000;
381 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override
);
383 cp15_control
&= ~0x4U
;
388 /* invalidate ICache */
389 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
391 cp15_control
&= ~0x1000U
;
394 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control
);
397 void arm926ejs_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
401 /* read cp15 control register */
402 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control
);
403 jtag_execute_queue();
406 cp15_control
|= 0x1U
;
409 cp15_control
|= 0x4U
;
412 cp15_control
|= 0x1000U
;
414 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control
);
417 void arm926ejs_post_debug_entry(target_t
*target
)
419 armv4_5_common_t
*armv4_5
= target
->arch_info
;
420 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
421 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
422 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
424 /* examine cp15 control reg */
425 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs
->cp15_control_reg
);
426 jtag_execute_queue();
427 DEBUG("cp15_control_reg: %8.8x", arm926ejs
->cp15_control_reg
);
429 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
432 /* identify caches */
433 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg
);
434 jtag_execute_queue();
435 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
438 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
439 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
440 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
442 /* save i/d fault status and address register */
443 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs
->d_fsr
);
444 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs
->i_fsr
);
445 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs
->d_far
);
447 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
448 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
453 /* read-modify-write CP15 cache debug control register
454 * to disable I/D-cache linefills and force WT */
455 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl
);
456 cache_dbg_ctrl
|= 0x7;
457 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl
);
460 void arm926ejs_pre_restore_context(target_t
*target
)
462 armv4_5_common_t
*armv4_5
= target
->arch_info
;
463 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
464 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
465 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
467 /* restore i/d fault status and address register */
468 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs
->d_fsr
);
469 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs
->i_fsr
);
470 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs
->d_far
);
474 /* read-modify-write CP15 cache debug control register
475 * to reenable I/D-cache linefills and disable WT */
476 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl
);
477 cache_dbg_ctrl
&= ~0x7;
478 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl
);
481 int arm926ejs_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm926ejs_common_t
**arm926ejs_p
)
483 armv4_5_common_t
*armv4_5
= target
->arch_info
;
484 arm7_9_common_t
*arm7_9
;
485 arm9tdmi_common_t
*arm9tdmi
;
486 arm926ejs_common_t
*arm926ejs
;
488 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
493 arm7_9
= armv4_5
->arch_info
;
494 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
499 arm9tdmi
= arm7_9
->arch_info
;
500 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
505 arm926ejs
= arm9tdmi
->arch_info
;
506 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
511 *armv4_5_p
= armv4_5
;
513 *arm9tdmi_p
= arm9tdmi
;
514 *arm926ejs_p
= arm926ejs
;
519 int arm926ejs_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
521 armv4_5_common_t
*armv4_5
= target
->arch_info
;
522 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
523 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
524 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
528 "disabled", "enabled"
531 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
533 ERROR("BUG: called for a non-ARMv4/5 target");
537 snprintf(buf
, buf_size
,
538 "target halted in %s state due to %s, current mode: %s\n"
539 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
540 "MMU: %s, D-Cache: %s, I-Cache: %s",
541 armv4_5_state_strings
[armv4_5
->core_state
],
542 target_debug_reason_strings
[target
->debug_reason
],
543 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
544 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
545 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
546 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
547 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
548 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
553 int arm926ejs_soft_reset_halt(struct target_s
*target
)
555 armv4_5_common_t
*armv4_5
= target
->arch_info
;
556 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
557 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
558 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
559 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
561 if (target
->state
== TARGET_RUNNING
)
563 target
->type
->halt(target
);
566 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
568 embeddedice_read_reg(dbg_stat
);
569 jtag_execute_queue();
572 target
->state
= TARGET_HALTED
;
574 /* SVC, ARM state, IRQ and FIQ disabled */
575 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
576 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
577 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
579 /* start fetching from 0x0 */
580 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
581 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
582 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
584 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
585 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
587 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
588 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
589 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
590 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
592 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
597 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
600 armv4_5_common_t
*armv4_5
= target
->arch_info
;
601 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
602 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
603 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
605 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
608 /* If ICache is enabled, we have to invalidate affected ICache lines
609 * the DCache is forced to write-through, so we don't have to clean it here
611 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
615 /* invalidate ICache single entry with MVA */
616 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address
);
620 /* invalidate ICache */
621 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address
);
628 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
630 arm9tdmi_init_target(cmd_ctx
, target
);
642 int arm926ejs_init_arch_info(target_t
*target
, arm926ejs_common_t
*arm926ejs
, int chain_pos
, char *variant
)
644 arm9tdmi_common_t
*arm9tdmi
= &arm926ejs
->arm9tdmi_common
;
645 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
647 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
649 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
651 arm9tdmi
->arch_info
= arm926ejs
;
652 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
654 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
655 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
657 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
658 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
659 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
660 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
661 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
662 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
663 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
664 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
666 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
668 /* The ARM926EJ-S implements the ARMv5TE architecture which
669 * has the BKPT instruction, so we don't have to use a watchpoint comparator
671 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
672 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
674 arm7_9
->sw_bkpts_use_wp
= 0;
675 arm7_9
->sw_bkpts_enabled
= 1;
680 int arm926ejs_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
683 char *variant
= NULL
;
684 arm926ejs_common_t
*arm926ejs
= malloc(sizeof(arm926ejs_common_t
));
688 ERROR("'target arm926ejs' requires at least one additional argument");
692 chain_pos
= strtoul(args
[3], NULL
, 0);
697 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
699 arm926ejs_init_arch_info(target
, arm926ejs
, chain_pos
, variant
);
704 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
)
707 command_t
*arm926ejs_cmd
;
710 retval
= arm9tdmi_register_commands(cmd_ctx
);
712 arm926ejs_cmd
= register_command(cmd_ctx
, NULL
, "arm926ejs", NULL
, COMMAND_ANY
, "arm926ejs specific commands");
714 register_command(cmd_ctx
, arm926ejs_cmd
, "cp15", arm926ejs_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
716 register_command(cmd_ctx
, arm926ejs_cmd
, "cache_info", arm926ejs_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
717 register_command(cmd_ctx
, arm926ejs_cmd
, "virt2phys", arm926ejs_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
719 register_command(cmd_ctx
, arm926ejs_cmd
, "mdw_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
720 register_command(cmd_ctx
, arm926ejs_cmd
, "mdh_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
721 register_command(cmd_ctx
, arm926ejs_cmd
, "mdb_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
723 register_command(cmd_ctx
, arm926ejs_cmd
, "mww_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
724 register_command(cmd_ctx
, arm926ejs_cmd
, "mwh_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
725 register_command(cmd_ctx
, arm926ejs_cmd
, "mwb_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
730 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
733 target_t
*target
= get_current_target(cmd_ctx
);
734 armv4_5_common_t
*armv4_5
;
735 arm7_9_common_t
*arm7_9
;
736 arm9tdmi_common_t
*arm9tdmi
;
737 arm926ejs_common_t
*arm926ejs
;
743 if ((argc
< 4) || (argc
> 5))
745 command_print(cmd_ctx
, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
749 opcode_1
= strtoul(args
[0], NULL
, 0);
750 opcode_2
= strtoul(args
[1], NULL
, 0);
751 CRn
= strtoul(args
[2], NULL
, 0);
752 CRm
= strtoul(args
[3], NULL
, 0);
754 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
756 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
760 if (target
->state
!= TARGET_HALTED
)
762 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
769 if ((retval
= arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(opcode_1
, opcode_2
, CRn
, CRm
), &value
)) != ERROR_OK
)
771 command_print(cmd_ctx
, "couldn't access register");
774 jtag_execute_queue();
776 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
780 u32 value
= strtoul(args
[4], NULL
, 0);
781 if ((retval
= arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(opcode_1
, opcode_2
, CRn
, CRm
), value
)) != ERROR_OK
)
783 command_print(cmd_ctx
, "couldn't access register");
786 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
792 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
794 target_t
*target
= get_current_target(cmd_ctx
);
795 armv4_5_common_t
*armv4_5
;
796 arm7_9_common_t
*arm7_9
;
797 arm9tdmi_common_t
*arm9tdmi
;
798 arm926ejs_common_t
*arm926ejs
;
800 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
802 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
806 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
809 int arm926ejs_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
811 target_t
*target
= get_current_target(cmd_ctx
);
812 armv4_5_common_t
*armv4_5
;
813 arm7_9_common_t
*arm7_9
;
814 arm9tdmi_common_t
*arm9tdmi
;
815 arm926ejs_common_t
*arm926ejs
;
816 arm_jtag_t
*jtag_info
;
818 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
820 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
824 jtag_info
= &arm7_9
->jtag_info
;
826 if (target
->state
!= TARGET_HALTED
)
828 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
832 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
835 int arm926ejs_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
837 target_t
*target
= get_current_target(cmd_ctx
);
838 armv4_5_common_t
*armv4_5
;
839 arm7_9_common_t
*arm7_9
;
840 arm9tdmi_common_t
*arm9tdmi
;
841 arm926ejs_common_t
*arm926ejs
;
842 arm_jtag_t
*jtag_info
;
844 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
846 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
850 jtag_info
= &arm7_9
->jtag_info
;
852 if (target
->state
!= TARGET_HALTED
)
854 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
858 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
861 int arm926ejs_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
863 target_t
*target
= get_current_target(cmd_ctx
);
864 armv4_5_common_t
*armv4_5
;
865 arm7_9_common_t
*arm7_9
;
866 arm9tdmi_common_t
*arm9tdmi
;
867 arm926ejs_common_t
*arm926ejs
;
868 arm_jtag_t
*jtag_info
;
870 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
872 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
876 jtag_info
= &arm7_9
->jtag_info
;
878 if (target
->state
!= TARGET_HALTED
)
880 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
884 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
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