1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "arm926ejs.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
31 #include "arm_opcodes.h"
35 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
36 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
37 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
39 * 1 ... core debugging
41 * 3 ... external boundary scan (SoC-specific, unused here)
43 * 15 ... coprocessor 15
47 #define _DEBUG_INSTRUCTION_EXECUTION_
50 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
52 static int arm926ejs_cp15_read(struct target
*target
, uint32_t op1
, uint32_t op2
,
53 uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
55 int retval
= ERROR_OK
;
56 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
57 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
58 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
59 struct scan_field fields
[4];
60 uint8_t address_buf
[2] = {0, 0};
64 buf_set_u32(address_buf
, 0, 14, address
);
66 if ((retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
)) != ERROR_OK
)
70 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
72 fields
[0].num_bits
= 32;
73 fields
[0].out_value
= NULL
;
74 fields
[0].in_value
= (uint8_t *)value
;
76 fields
[1].num_bits
= 1;
77 fields
[1].out_value
= &access_t
;
78 fields
[1].in_value
= &access_t
;
80 fields
[2].num_bits
= 14;
81 fields
[2].out_value
= address_buf
;
82 fields
[2].in_value
= NULL
;
84 fields
[3].num_bits
= 1;
85 fields
[3].out_value
= &nr_w_buf
;
86 fields
[3].in_value
= NULL
;
88 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
90 long long then
= timeval_ms();
94 /* rescan with NOP, to wait for the access to complete */
97 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
99 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
101 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
106 if (buf_get_u32(&access_t
, 0, 1) == 1)
112 if ((timeval_ms()-then
)>10)
114 LOG_ERROR("cp15 read operation timed out");
119 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
120 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
123 arm_jtag_set_instr(jtag_info
, 0xc, NULL
, TAP_IDLE
);
128 static int arm926ejs_mrc(struct target
*target
, int cpnum
, uint32_t op1
,
129 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
132 LOG_ERROR("Only cp15 is supported");
135 return arm926ejs_cp15_read(target
, op1
, op2
, CRn
, CRm
, value
);
138 static int arm926ejs_cp15_write(struct target
*target
, uint32_t op1
, uint32_t op2
,
139 uint32_t CRn
, uint32_t CRm
, uint32_t value
)
141 int retval
= ERROR_OK
;
142 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
143 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
144 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
145 struct scan_field fields
[4];
146 uint8_t value_buf
[4];
147 uint8_t address_buf
[2] = {0, 0};
148 uint8_t nr_w_buf
= 1;
149 uint8_t access_t
= 1;
151 buf_set_u32(address_buf
, 0, 14, address
);
152 buf_set_u32(value_buf
, 0, 32, value
);
154 if ((retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
)) != ERROR_OK
)
158 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
160 fields
[0].num_bits
= 32;
161 fields
[0].out_value
= value_buf
;
162 fields
[0].in_value
= NULL
;
164 fields
[1].num_bits
= 1;
165 fields
[1].out_value
= &access_t
;
166 fields
[1].in_value
= &access_t
;
168 fields
[2].num_bits
= 14;
169 fields
[2].out_value
= address_buf
;
170 fields
[2].in_value
= NULL
;
172 fields
[3].num_bits
= 1;
173 fields
[3].out_value
= &nr_w_buf
;
174 fields
[3].in_value
= NULL
;
176 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
178 long long then
= timeval_ms();
182 /* rescan with NOP, to wait for the access to complete */
185 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
186 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
191 if (buf_get_u32(&access_t
, 0, 1) == 1)
197 if ((timeval_ms()-then
)>10)
199 LOG_ERROR("cp15 write operation timed out");
204 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
205 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
208 arm_jtag_set_instr(jtag_info
, 0xf, NULL
, TAP_IDLE
);
213 static int arm926ejs_mcr(struct target
*target
, int cpnum
, uint32_t op1
,
214 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
217 LOG_ERROR("Only cp15 is supported");
220 return arm926ejs_cp15_write(target
, op1
, op2
, CRn
, CRm
, value
);
223 static int arm926ejs_examine_debug_reason(struct target
*target
)
225 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
226 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
230 embeddedice_read_reg(dbg_stat
);
231 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
234 /* Method-Of-Entry (MOE) field */
235 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
237 switch (debug_reason
)
240 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
241 /* ... since last restart or debug reset ... */
242 target
->debug_reason
= DBG_REASON_DBGRQ
;
245 LOG_DEBUG("breakpoint from EICE unit 0");
246 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
249 LOG_DEBUG("breakpoint from EICE unit 1");
250 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
253 LOG_DEBUG("soft breakpoint (BKPT instruction)");
254 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
257 LOG_DEBUG("vector catch breakpoint");
258 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
261 LOG_DEBUG("external breakpoint");
262 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
265 LOG_DEBUG("watchpoint from EICE unit 0");
266 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
269 LOG_DEBUG("watchpoint from EICE unit 1");
270 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
273 LOG_DEBUG("external watchpoint");
274 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
277 LOG_DEBUG("internal debug request");
278 target
->debug_reason
= DBG_REASON_DBGRQ
;
281 LOG_DEBUG("external debug request");
282 target
->debug_reason
= DBG_REASON_DBGRQ
;
285 LOG_DEBUG("debug re-entry from system speed access");
286 /* This is normal when connecting to something that's
287 * already halted, or in some related code paths, but
288 * otherwise is surprising (and presumably wrong).
290 switch (target
->debug_reason
) {
291 case DBG_REASON_DBGRQ
:
294 LOG_ERROR("unexpected -- debug re-entry");
296 case DBG_REASON_UNDEFINED
:
297 target
->debug_reason
= DBG_REASON_DBGRQ
;
302 /* FIX!!!! here be dragons!!! We need to fail here so
303 * the target will interpreted as halted but we won't
304 * try to talk to it right now... a resume + halt seems
305 * to sync things up again. Please send an email to
306 * openocd development mailing list if you have hardware
307 * to donate to look into this problem....
309 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
310 target
->debug_reason
= DBG_REASON_DBGRQ
;
313 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
314 /* Oh agony! should we interpret this as a halt request or
315 * that the target stopped on it's own accord?
317 target
->debug_reason
= DBG_REASON_DBGRQ
;
318 /* if we fail here, we won't talk to the target and it will
319 * be reported to be in the halted state */
326 static int arm926ejs_get_ttb(struct target
*target
, uint32_t *result
)
328 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
332 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
340 static int arm926ejs_disable_mmu_caches(struct target
*target
, int mmu
,
341 int d_u_cache
, int i_cache
)
343 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
344 uint32_t cp15_control
;
347 /* read cp15 control register */
348 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
349 if (retval
!= ERROR_OK
)
351 retval
= jtag_execute_queue();
352 if (retval
!= ERROR_OK
)
358 retval
= arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
359 if (retval
!= ERROR_OK
)
362 cp15_control
&= ~0x1U
;
367 uint32_t debug_override
;
368 /* read-modify-write CP15 debug override register
369 * to enable "test and clean all" */
370 retval
= arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
371 if (retval
!= ERROR_OK
)
373 debug_override
|= 0x80000;
374 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
375 if (retval
!= ERROR_OK
)
378 /* clean and invalidate DCache */
379 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
380 if (retval
!= ERROR_OK
)
383 /* write CP15 debug override register
384 * to disable "test and clean all" */
385 debug_override
&= ~0x80000;
386 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
387 if (retval
!= ERROR_OK
)
390 cp15_control
&= ~0x4U
;
395 /* invalidate ICache */
396 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
397 if (retval
!= ERROR_OK
)
400 cp15_control
&= ~0x1000U
;
403 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
407 static int arm926ejs_enable_mmu_caches(struct target
*target
, int mmu
,
408 int d_u_cache
, int i_cache
)
410 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
411 uint32_t cp15_control
;
414 /* read cp15 control register */
415 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
416 if (retval
!= ERROR_OK
)
418 retval
= jtag_execute_queue();
419 if (retval
!= ERROR_OK
)
423 cp15_control
|= 0x1U
;
426 cp15_control
|= 0x4U
;
429 cp15_control
|= 0x1000U
;
431 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
435 static void arm926ejs_post_debug_entry(struct target
*target
)
437 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
439 /* examine cp15 control reg */
440 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
441 jtag_execute_queue();
442 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
444 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
446 uint32_t cache_type_reg
;
447 /* identify caches */
448 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
449 jtag_execute_queue();
450 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
453 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
454 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
455 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
457 /* save i/d fault status and address register */
458 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
459 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
460 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
462 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
463 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
465 uint32_t cache_dbg_ctrl
;
467 /* read-modify-write CP15 cache debug control register
468 * to disable I/D-cache linefills and force WT */
469 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
470 cache_dbg_ctrl
|= 0x7;
471 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
474 static void arm926ejs_pre_restore_context(struct target
*target
)
476 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
478 /* restore i/d fault status and address register */
479 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
480 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
481 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
483 uint32_t cache_dbg_ctrl
;
485 /* read-modify-write CP15 cache debug control register
486 * to reenable I/D-cache linefills and disable WT */
487 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
488 cache_dbg_ctrl
&= ~0x7;
489 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
492 static const char arm926_not
[] = "target is not an ARM926";
494 static int arm926ejs_verify_pointer(struct command_context
*cmd_ctx
,
495 struct arm926ejs_common
*arm926
)
497 if (arm926
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
498 command_print(cmd_ctx
, arm926_not
);
499 return ERROR_TARGET_INVALID
;
504 /** Logs summary of ARM926 state for a halted target. */
505 int arm926ejs_arch_state(struct target
*target
)
507 static const char *state
[] =
509 "disabled", "enabled"
512 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
515 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
517 LOG_ERROR("BUG: %s", arm926_not
);
518 return ERROR_TARGET_INVALID
;
521 armv4_5
= &arm926ejs
->arm7_9_common
.armv4_5_common
;
523 arm_arch_state(target
);
524 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
525 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
526 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
527 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
532 int arm926ejs_soft_reset_halt(struct target
*target
)
534 int retval
= ERROR_OK
;
535 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
536 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
537 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
538 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
540 if ((retval
= target_halt(target
)) != ERROR_OK
)
545 long long then
= timeval_ms();
547 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
549 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
551 embeddedice_read_reg(dbg_stat
);
552 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
560 if (debug_level
>= 1)
562 /* do not eat all CPU, time out after 1 se*/
571 LOG_ERROR("Failed to halt CPU after 1 sec");
572 return ERROR_TARGET_TIMEOUT
;
575 target
->state
= TARGET_HALTED
;
577 /* SVC, ARM state, IRQ and FIQ disabled */
580 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
583 arm_set_cpsr(armv4_5
, cpsr
);
584 armv4_5
->cpsr
->dirty
= 1;
586 /* start fetching from 0x0 */
587 buf_set_u32(armv4_5
->pc
->value
, 0, 32, 0x0);
588 armv4_5
->pc
->dirty
= 1;
589 armv4_5
->pc
->valid
= 1;
591 retval
= arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
592 if (retval
!= ERROR_OK
)
594 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
595 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
596 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
598 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
601 /** Writes a buffer, in the specified word size, with current MMU settings. */
602 int arm926ejs_write_memory(struct target
*target
, uint32_t address
,
603 uint32_t size
, uint32_t count
, uint8_t *buffer
)
606 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
608 /* FIX!!!! this should be cleaned up and made much more general. The
609 * plan is to write up and test on arm926ejs specifically and
610 * then generalize and clean up afterwards.
613 * Also it should be moved to the callbacks that handle breakpoints
614 * specifically and not the generic memory write fn's. See XScale code.
616 if (arm926ejs
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) && ((size
==2) || (size
==4)))
618 /* special case the handling of single word writes to bypass MMU
619 * to allow implementation of breakpoints in memory marked read only
621 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
623 /* flush and invalidate data cache
625 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
628 retval
= arm926ejs
->write_cp15(target
, 0, 1, 7, 10, address
&~0x3);
629 if (retval
!= ERROR_OK
)
634 retval
= target
->type
->virt2phys(target
, address
, &pa
);
635 if (retval
!= ERROR_OK
)
638 /* write directly to physical memory bypassing any read only MMU bits, etc. */
639 retval
= armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
, pa
, size
, count
, buffer
);
640 if (retval
!= ERROR_OK
)
644 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
648 /* If ICache is enabled, we have to invalidate affected ICache lines
649 * the DCache is forced to write-through, so we don't have to clean it here
651 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
655 /* invalidate ICache single entry with MVA */
656 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
660 /* invalidate ICache */
661 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
668 static int arm926ejs_write_phys_memory(struct target
*target
,
669 uint32_t address
, uint32_t size
,
670 uint32_t count
, uint8_t *buffer
)
672 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
674 return armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
,
675 address
, size
, count
, buffer
);
678 static int arm926ejs_read_phys_memory(struct target
*target
,
679 uint32_t address
, uint32_t size
,
680 uint32_t count
, uint8_t *buffer
)
682 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
684 return armv4_5_mmu_read_physical(target
, &arm926ejs
->armv4_5_mmu
,
685 address
, size
, count
, buffer
);
688 int arm926ejs_init_arch_info(struct target
*target
, struct arm926ejs_common
*arm926ejs
,
689 struct jtag_tap
*tap
)
691 struct arm7_9_common
*arm7_9
= &arm926ejs
->arm7_9_common
;
693 arm7_9
->armv4_5_common
.mrc
= arm926ejs_mrc
;
694 arm7_9
->armv4_5_common
.mcr
= arm926ejs_mcr
;
696 /* initialize arm7/arm9 specific info (including armv4_5) */
697 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
699 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
701 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
702 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
704 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
705 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
706 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
707 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
708 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
709 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
710 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
711 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
712 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
713 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
715 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
717 /* The ARM926EJ-S implements the ARMv5TE architecture which
718 * has the BKPT instruction, so we don't have to use a watchpoint comparator
720 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
721 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
726 static int arm926ejs_target_create(struct target
*target
, Jim_Interp
*interp
)
728 struct arm926ejs_common
*arm926ejs
= calloc(1,sizeof(struct arm926ejs_common
));
730 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
731 target
->tap
->ir_capture_mask
= 0x0f;
733 return arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
736 COMMAND_HANDLER(arm926ejs_handle_cache_info_command
)
739 struct target
*target
= get_current_target(CMD_CTX
);
740 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
742 retval
= arm926ejs_verify_pointer(CMD_CTX
, arm926ejs
);
743 if (retval
!= ERROR_OK
)
746 return armv4_5_handle_cache_info_command(CMD_CTX
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
749 static int arm926ejs_virt2phys(struct target
*target
, uint32_t virtual, uint32_t *physical
)
752 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
755 int retval
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
,
757 if (retval
!= ERROR_OK
)
763 static int arm926ejs_mmu(struct target
*target
, int *enabled
)
765 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
767 if (target
->state
!= TARGET_HALTED
)
769 LOG_ERROR("Target not halted");
770 return ERROR_TARGET_INVALID
;
772 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
776 static const struct command_registration arm926ejs_exec_command_handlers
[] = {
778 .name
= "cache_info",
779 .handler
= arm926ejs_handle_cache_info_command
,
780 .mode
= COMMAND_EXEC
,
781 .help
= "display information about target caches",
784 COMMAND_REGISTRATION_DONE
786 const struct command_registration arm926ejs_command_handlers
[] = {
788 .chain
= arm9tdmi_command_handlers
,
793 .help
= "arm926ejs command group",
794 .chain
= arm926ejs_exec_command_handlers
,
796 COMMAND_REGISTRATION_DONE
799 /** Holds methods for ARM926 targets. */
800 struct target_type arm926ejs_target
=
805 .arch_state
= arm926ejs_arch_state
,
807 .target_request_data
= arm7_9_target_request_data
,
810 .resume
= arm7_9_resume
,
813 .assert_reset
= arm7_9_assert_reset
,
814 .deassert_reset
= arm7_9_deassert_reset
,
815 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
817 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
819 .read_memory
= arm7_9_read_memory
,
820 .write_memory
= arm926ejs_write_memory
,
821 .bulk_write_memory
= arm7_9_bulk_write_memory
,
823 .checksum_memory
= arm_checksum_memory
,
824 .blank_check_memory
= arm_blank_check_memory
,
826 .run_algorithm
= armv4_5_run_algorithm
,
828 .add_breakpoint
= arm7_9_add_breakpoint
,
829 .remove_breakpoint
= arm7_9_remove_breakpoint
,
830 .add_watchpoint
= arm7_9_add_watchpoint
,
831 .remove_watchpoint
= arm7_9_remove_watchpoint
,
833 .commands
= arm926ejs_command_handlers
,
834 .target_create
= arm926ejs_target_create
,
835 .init_target
= arm9tdmi_init_target
,
836 .examine
= arm7_9_examine
,
837 .check_reset
= arm7_9_check_reset
,
838 .virt2phys
= arm926ejs_virt2phys
,
839 .mmu
= arm926ejs_mmu
,
841 .read_phys_memory
= arm926ejs_read_phys_memory
,
842 .write_phys_memory
= arm926ejs_write_phys_memory
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)