1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "arm926ejs.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
31 #include "arm_opcodes.h"
35 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
36 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
37 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
39 * 1 ... core debugging
41 * 3 ... external boundary scan (SoC-specific, unused here)
43 * 15 ... coprocessor 15
47 #define _DEBUG_INSTRUCTION_EXECUTION_
50 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
52 static int arm926ejs_cp15_read(struct target
*target
, uint32_t op1
, uint32_t op2
,
53 uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
55 int retval
= ERROR_OK
;
56 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
57 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
58 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
59 struct scan_field fields
[4];
60 uint8_t address_buf
[2] = {0, 0};
64 buf_set_u32(address_buf
, 0, 14, address
);
66 if ((retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
)) != ERROR_OK
)
70 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
72 fields
[0].num_bits
= 32;
73 fields
[0].out_value
= NULL
;
74 fields
[0].in_value
= (uint8_t *)value
;
76 fields
[1].num_bits
= 1;
77 fields
[1].out_value
= &access_t
;
78 fields
[1].in_value
= &access_t
;
80 fields
[2].num_bits
= 14;
81 fields
[2].out_value
= address_buf
;
82 fields
[2].in_value
= NULL
;
84 fields
[3].num_bits
= 1;
85 fields
[3].out_value
= &nr_w_buf
;
86 fields
[3].in_value
= NULL
;
88 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
90 long long then
= timeval_ms();
94 /* rescan with NOP, to wait for the access to complete */
97 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
99 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
101 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
106 if (buf_get_u32(&access_t
, 0, 1) == 1)
112 if ((timeval_ms()-then
)>10)
114 LOG_ERROR("cp15 read operation timed out");
119 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
120 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
123 arm_jtag_set_instr(jtag_info
, 0xc, NULL
, TAP_IDLE
);
128 static int arm926ejs_mrc(struct target
*target
, int cpnum
, uint32_t op1
,
129 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
132 LOG_ERROR("Only cp15 is supported");
135 return arm926ejs_cp15_read(target
, op1
, op2
, CRn
, CRm
, value
);
138 static int arm926ejs_cp15_write(struct target
*target
, uint32_t op1
, uint32_t op2
,
139 uint32_t CRn
, uint32_t CRm
, uint32_t value
)
141 int retval
= ERROR_OK
;
142 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
143 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
144 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
145 struct scan_field fields
[4];
146 uint8_t value_buf
[4];
147 uint8_t address_buf
[2] = {0, 0};
148 uint8_t nr_w_buf
= 1;
149 uint8_t access_t
= 1;
151 buf_set_u32(address_buf
, 0, 14, address
);
152 buf_set_u32(value_buf
, 0, 32, value
);
154 if ((retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
)) != ERROR_OK
)
158 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
160 fields
[0].num_bits
= 32;
161 fields
[0].out_value
= value_buf
;
162 fields
[0].in_value
= NULL
;
164 fields
[1].num_bits
= 1;
165 fields
[1].out_value
= &access_t
;
166 fields
[1].in_value
= &access_t
;
168 fields
[2].num_bits
= 14;
169 fields
[2].out_value
= address_buf
;
170 fields
[2].in_value
= NULL
;
172 fields
[3].num_bits
= 1;
173 fields
[3].out_value
= &nr_w_buf
;
174 fields
[3].in_value
= NULL
;
176 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
178 long long then
= timeval_ms();
182 /* rescan with NOP, to wait for the access to complete */
185 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
186 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
191 if (buf_get_u32(&access_t
, 0, 1) == 1)
197 if ((timeval_ms()-then
)>10)
199 LOG_ERROR("cp15 write operation timed out");
204 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
205 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
208 arm_jtag_set_instr(jtag_info
, 0xf, NULL
, TAP_IDLE
);
213 static int arm926ejs_mcr(struct target
*target
, int cpnum
, uint32_t op1
,
214 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
217 LOG_ERROR("Only cp15 is supported");
220 return arm926ejs_cp15_write(target
, op1
, op2
, CRn
, CRm
, value
);
223 static int arm926ejs_examine_debug_reason(struct target
*target
)
225 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
226 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
230 embeddedice_read_reg(dbg_stat
);
231 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
234 /* Method-Of-Entry (MOE) field */
235 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
237 switch (debug_reason
)
240 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
241 /* ... since last restart or debug reset ... */
242 target
->debug_reason
= DBG_REASON_DBGRQ
;
245 LOG_DEBUG("breakpoint from EICE unit 0");
246 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
249 LOG_DEBUG("breakpoint from EICE unit 1");
250 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
253 LOG_DEBUG("soft breakpoint (BKPT instruction)");
254 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
257 LOG_DEBUG("vector catch breakpoint");
258 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
261 LOG_DEBUG("external breakpoint");
262 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
265 LOG_DEBUG("watchpoint from EICE unit 0");
266 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
269 LOG_DEBUG("watchpoint from EICE unit 1");
270 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
273 LOG_DEBUG("external watchpoint");
274 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
277 LOG_DEBUG("internal debug request");
278 target
->debug_reason
= DBG_REASON_DBGRQ
;
281 LOG_DEBUG("external debug request");
282 target
->debug_reason
= DBG_REASON_DBGRQ
;
285 LOG_DEBUG("debug re-entry from system speed access");
286 /* This is normal when connecting to something that's
287 * already halted, or in some related code paths, but
288 * otherwise is surprising (and presumably wrong).
290 switch (target
->debug_reason
) {
291 case DBG_REASON_DBGRQ
:
294 LOG_ERROR("unexpected -- debug re-entry");
296 case DBG_REASON_UNDEFINED
:
297 target
->debug_reason
= DBG_REASON_DBGRQ
;
302 /* FIX!!!! here be dragons!!! We need to fail here so
303 * the target will interpreted as halted but we won't
304 * try to talk to it right now... a resume + halt seems
305 * to sync things up again. Please send an email to
306 * openocd development mailing list if you have hardware
307 * to donate to look into this problem....
309 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
310 target
->debug_reason
= DBG_REASON_DBGRQ
;
313 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
314 /* Oh agony! should we interpret this as a halt request or
315 * that the target stopped on it's own accord?
317 target
->debug_reason
= DBG_REASON_DBGRQ
;
318 /* if we fail here, we won't talk to the target and it will
319 * be reported to be in the halted state */
326 static int arm926ejs_get_ttb(struct target
*target
, uint32_t *result
)
328 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
332 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
340 static void arm926ejs_disable_mmu_caches(struct target
*target
, int mmu
,
341 int d_u_cache
, int i_cache
)
343 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
344 uint32_t cp15_control
;
346 /* read cp15 control register */
347 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
348 jtag_execute_queue();
353 arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
355 cp15_control
&= ~0x1U
;
360 uint32_t debug_override
;
361 /* read-modify-write CP15 debug override register
362 * to enable "test and clean all" */
363 arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
364 debug_override
|= 0x80000;
365 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
367 /* clean and invalidate DCache */
368 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
370 /* write CP15 debug override register
371 * to disable "test and clean all" */
372 debug_override
&= ~0x80000;
373 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
375 cp15_control
&= ~0x4U
;
380 /* invalidate ICache */
381 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
383 cp15_control
&= ~0x1000U
;
386 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
389 static void arm926ejs_enable_mmu_caches(struct target
*target
, int mmu
,
390 int d_u_cache
, int i_cache
)
392 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
393 uint32_t cp15_control
;
395 /* read cp15 control register */
396 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
397 jtag_execute_queue();
400 cp15_control
|= 0x1U
;
403 cp15_control
|= 0x4U
;
406 cp15_control
|= 0x1000U
;
408 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
411 static void arm926ejs_post_debug_entry(struct target
*target
)
413 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
415 /* examine cp15 control reg */
416 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
417 jtag_execute_queue();
418 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
420 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
422 uint32_t cache_type_reg
;
423 /* identify caches */
424 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
425 jtag_execute_queue();
426 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
429 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
430 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
431 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
433 /* save i/d fault status and address register */
434 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
435 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
436 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
438 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
439 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
441 uint32_t cache_dbg_ctrl
;
443 /* read-modify-write CP15 cache debug control register
444 * to disable I/D-cache linefills and force WT */
445 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
446 cache_dbg_ctrl
|= 0x7;
447 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
450 static void arm926ejs_pre_restore_context(struct target
*target
)
452 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
454 /* restore i/d fault status and address register */
455 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
456 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
457 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
459 uint32_t cache_dbg_ctrl
;
461 /* read-modify-write CP15 cache debug control register
462 * to reenable I/D-cache linefills and disable WT */
463 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
464 cache_dbg_ctrl
&= ~0x7;
465 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
468 static const char arm926_not
[] = "target is not an ARM926";
470 static int arm926ejs_verify_pointer(struct command_context
*cmd_ctx
,
471 struct arm926ejs_common
*arm926
)
473 if (arm926
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
474 command_print(cmd_ctx
, arm926_not
);
475 return ERROR_TARGET_INVALID
;
480 /** Logs summary of ARM926 state for a halted target. */
481 int arm926ejs_arch_state(struct target
*target
)
483 static const char *state
[] =
485 "disabled", "enabled"
488 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
491 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
493 LOG_ERROR("BUG: %s", arm926_not
);
494 return ERROR_TARGET_INVALID
;
497 armv4_5
= &arm926ejs
->arm7_9_common
.armv4_5_common
;
499 arm_arch_state(target
);
500 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
501 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
502 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
503 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
508 int arm926ejs_soft_reset_halt(struct target
*target
)
510 int retval
= ERROR_OK
;
511 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
512 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
513 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
514 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
516 if ((retval
= target_halt(target
)) != ERROR_OK
)
521 long long then
= timeval_ms();
523 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
525 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
527 embeddedice_read_reg(dbg_stat
);
528 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
536 if (debug_level
>= 1)
538 /* do not eat all CPU, time out after 1 se*/
547 LOG_ERROR("Failed to halt CPU after 1 sec");
548 return ERROR_TARGET_TIMEOUT
;
551 target
->state
= TARGET_HALTED
;
553 /* SVC, ARM state, IRQ and FIQ disabled */
556 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
559 arm_set_cpsr(armv4_5
, cpsr
);
560 armv4_5
->cpsr
->dirty
= 1;
562 /* start fetching from 0x0 */
563 buf_set_u32(armv4_5
->pc
->value
, 0, 32, 0x0);
564 armv4_5
->pc
->dirty
= 1;
565 armv4_5
->pc
->valid
= 1;
567 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
568 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
569 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
570 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
572 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
575 /** Writes a buffer, in the specified word size, with current MMU settings. */
576 int arm926ejs_write_memory(struct target
*target
, uint32_t address
,
577 uint32_t size
, uint32_t count
, uint8_t *buffer
)
580 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
582 /* FIX!!!! this should be cleaned up and made much more general. The
583 * plan is to write up and test on arm926ejs specifically and
584 * then generalize and clean up afterwards.
587 * Also it should be moved to the callbacks that handle breakpoints
588 * specifically and not the generic memory write fn's. See XScale code.
590 if (arm926ejs
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) && ((size
==2) || (size
==4)))
592 /* special case the handling of single word writes to bypass MMU
593 * to allow implementation of breakpoints in memory marked read only
595 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
597 /* flush and invalidate data cache
599 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
602 retval
= arm926ejs
->write_cp15(target
, 0, 1, 7, 10, address
&~0x3);
603 if (retval
!= ERROR_OK
)
608 retval
= target
->type
->virt2phys(target
, address
, &pa
);
609 if (retval
!= ERROR_OK
)
612 /* write directly to physical memory bypassing any read only MMU bits, etc. */
613 retval
= armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
, pa
, size
, count
, buffer
);
614 if (retval
!= ERROR_OK
)
618 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
622 /* If ICache is enabled, we have to invalidate affected ICache lines
623 * the DCache is forced to write-through, so we don't have to clean it here
625 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
629 /* invalidate ICache single entry with MVA */
630 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
634 /* invalidate ICache */
635 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
642 static int arm926ejs_write_phys_memory(struct target
*target
,
643 uint32_t address
, uint32_t size
,
644 uint32_t count
, uint8_t *buffer
)
646 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
648 return armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
,
649 address
, size
, count
, buffer
);
652 static int arm926ejs_read_phys_memory(struct target
*target
,
653 uint32_t address
, uint32_t size
,
654 uint32_t count
, uint8_t *buffer
)
656 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
658 return armv4_5_mmu_read_physical(target
, &arm926ejs
->armv4_5_mmu
,
659 address
, size
, count
, buffer
);
662 int arm926ejs_init_arch_info(struct target
*target
, struct arm926ejs_common
*arm926ejs
,
663 struct jtag_tap
*tap
)
665 struct arm7_9_common
*arm7_9
= &arm926ejs
->arm7_9_common
;
667 arm7_9
->armv4_5_common
.mrc
= arm926ejs_mrc
;
668 arm7_9
->armv4_5_common
.mcr
= arm926ejs_mcr
;
670 /* initialize arm7/arm9 specific info (including armv4_5) */
671 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
673 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
675 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
676 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
678 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
679 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
680 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
681 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
682 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
683 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
684 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
685 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
686 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
687 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
689 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
691 /* The ARM926EJ-S implements the ARMv5TE architecture which
692 * has the BKPT instruction, so we don't have to use a watchpoint comparator
694 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
695 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
700 static int arm926ejs_target_create(struct target
*target
, Jim_Interp
*interp
)
702 struct arm926ejs_common
*arm926ejs
= calloc(1,sizeof(struct arm926ejs_common
));
704 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
705 target
->tap
->ir_capture_mask
= 0x0f;
707 return arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
710 COMMAND_HANDLER(arm926ejs_handle_cache_info_command
)
713 struct target
*target
= get_current_target(CMD_CTX
);
714 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
716 retval
= arm926ejs_verify_pointer(CMD_CTX
, arm926ejs
);
717 if (retval
!= ERROR_OK
)
720 return armv4_5_handle_cache_info_command(CMD_CTX
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
723 static int arm926ejs_virt2phys(struct target
*target
, uint32_t virtual, uint32_t *physical
)
726 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
729 int retval
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
,
731 if (retval
!= ERROR_OK
)
737 static int arm926ejs_mmu(struct target
*target
, int *enabled
)
739 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
741 if (target
->state
!= TARGET_HALTED
)
743 LOG_ERROR("Target not halted");
744 return ERROR_TARGET_INVALID
;
746 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
750 static const struct command_registration arm926ejs_exec_command_handlers
[] = {
752 .name
= "cache_info",
753 .handler
= arm926ejs_handle_cache_info_command
,
754 .mode
= COMMAND_EXEC
,
755 .help
= "display information about target caches",
758 COMMAND_REGISTRATION_DONE
760 const struct command_registration arm926ejs_command_handlers
[] = {
762 .chain
= arm9tdmi_command_handlers
,
767 .help
= "arm926ejs command group",
768 .chain
= arm926ejs_exec_command_handlers
,
770 COMMAND_REGISTRATION_DONE
773 /** Holds methods for ARM926 targets. */
774 struct target_type arm926ejs_target
=
779 .arch_state
= arm926ejs_arch_state
,
781 .target_request_data
= arm7_9_target_request_data
,
784 .resume
= arm7_9_resume
,
787 .assert_reset
= arm7_9_assert_reset
,
788 .deassert_reset
= arm7_9_deassert_reset
,
789 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
791 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
793 .read_memory
= arm7_9_read_memory
,
794 .write_memory
= arm926ejs_write_memory
,
795 .bulk_write_memory
= arm7_9_bulk_write_memory
,
797 .checksum_memory
= arm_checksum_memory
,
798 .blank_check_memory
= arm_blank_check_memory
,
800 .run_algorithm
= armv4_5_run_algorithm
,
802 .add_breakpoint
= arm7_9_add_breakpoint
,
803 .remove_breakpoint
= arm7_9_remove_breakpoint
,
804 .add_watchpoint
= arm7_9_add_watchpoint
,
805 .remove_watchpoint
= arm7_9_remove_watchpoint
,
807 .commands
= arm926ejs_command_handlers
,
808 .target_create
= arm926ejs_target_create
,
809 .init_target
= arm9tdmi_init_target
,
810 .examine
= arm7_9_examine
,
811 .check_reset
= arm7_9_check_reset
,
812 .virt2phys
= arm926ejs_virt2phys
,
813 .mmu
= arm926ejs_mmu
,
815 .read_phys_memory
= arm926ejs_read_phys_memory
,
816 .write_phys_memory
= arm926ejs_write_phys_memory
,
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