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4a4b9a1c1b08a52d7fda477966e5c5b27dffc5e0
[openocd.git] / src / target / arm9tdmi.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm9tdmi.h"
25
26 #include "arm7_9_common.h"
27 #include "register.h"
28 #include "target.h"
29 #include "armv4_5.h"
30 #include "embeddedice.h"
31 #include "etm.h"
32 #include "etb.h"
33 #include "log.h"
34 #include "jtag.h"
35 #include "arm_jtag.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 #if 0
41 #define _DEBUG_INSTRUCTION_EXECUTION_
42 #endif
43
44 /* cli handling */
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm9tdmi_quit();
52
53 target_type_t arm9tdmi_target =
54 {
55 .name = "arm9tdmi",
56
57 .poll = arm7_9_poll,
58 .arch_state = armv4_5_arch_state,
59
60 .target_request_data = arm7_9_target_request_data,
61
62 .halt = arm7_9_halt,
63 .resume = arm7_9_resume,
64 .step = arm7_9_step,
65
66 .assert_reset = arm7_9_assert_reset,
67 .deassert_reset = arm7_9_deassert_reset,
68 .soft_reset_halt = arm7_9_soft_reset_halt,
69
70 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
71
72 .read_memory = arm7_9_read_memory,
73 .write_memory = arm7_9_write_memory,
74 .bulk_write_memory = arm7_9_bulk_write_memory,
75 .checksum_memory = arm7_9_checksum_memory,
76
77 .run_algorithm = armv4_5_run_algorithm,
78
79 .add_breakpoint = arm7_9_add_breakpoint,
80 .remove_breakpoint = arm7_9_remove_breakpoint,
81 .add_watchpoint = arm7_9_add_watchpoint,
82 .remove_watchpoint = arm7_9_remove_watchpoint,
83
84 .register_commands = arm9tdmi_register_commands,
85 .target_command = arm9tdmi_target_command,
86 .init_target = arm9tdmi_init_target,
87 .quit = arm9tdmi_quit
88 };
89
90 arm9tdmi_vector_t arm9tdmi_vectors[] =
91 {
92 {"reset", ARM9TDMI_RESET_VECTOR},
93 {"undef", ARM9TDMI_UNDEF_VECTOR},
94 {"swi", ARM9TDMI_SWI_VECTOR},
95 {"pabt", ARM9TDMI_PABT_VECTOR},
96 {"dabt", ARM9TDMI_DABT_VECTOR},
97 {"reserved", ARM9TDMI_RESERVED_VECTOR},
98 {"irq", ARM9TDMI_IRQ_VECTOR},
99 {"fiq", ARM9TDMI_FIQ_VECTOR},
100 {0, 0},
101 };
102
103 int arm9tdmi_examine_debug_reason(target_t *target)
104 {
105 /* get pointers to arch-specific information */
106 armv4_5_common_t *armv4_5 = target->arch_info;
107 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
108
109 /* only check the debug reason if we don't know it already */
110 if ((target->debug_reason != DBG_REASON_DBGRQ)
111 && (target->debug_reason != DBG_REASON_SINGLESTEP))
112 {
113 scan_field_t fields[3];
114 u8 databus[4];
115 u8 instructionbus[4];
116 u8 debug_reason;
117
118 jtag_add_end_state(TAP_PD);
119
120 fields[0].device = arm7_9->jtag_info.chain_pos;
121 fields[0].num_bits = 32;
122 fields[0].out_value = NULL;
123 fields[0].out_mask = NULL;
124 fields[0].in_value = databus;
125 fields[0].in_check_value = NULL;
126 fields[0].in_check_mask = NULL;
127 fields[0].in_handler = NULL;
128 fields[0].in_handler_priv = NULL;
129
130 fields[1].device = arm7_9->jtag_info.chain_pos;
131 fields[1].num_bits = 3;
132 fields[1].out_value = NULL;
133 fields[1].out_mask = NULL;
134 fields[1].in_value = &debug_reason;
135 fields[1].in_check_value = NULL;
136 fields[1].in_check_mask = NULL;
137 fields[1].in_handler = NULL;
138 fields[1].in_handler_priv = NULL;
139
140 fields[2].device = arm7_9->jtag_info.chain_pos;
141 fields[2].num_bits = 32;
142 fields[2].out_value = NULL;
143 fields[2].out_mask = NULL;
144 fields[2].in_value = instructionbus;
145 fields[2].in_check_value = NULL;
146 fields[2].in_check_mask = NULL;
147 fields[2].in_handler = NULL;
148 fields[2].in_handler_priv = NULL;
149
150 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
151 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
152
153 jtag_add_dr_scan(3, fields, TAP_PD);
154 jtag_execute_queue();
155
156 fields[0].in_value = NULL;
157 fields[0].out_value = databus;
158 fields[1].in_value = NULL;
159 fields[1].out_value = &debug_reason;
160 fields[2].in_value = NULL;
161 fields[2].out_value = instructionbus;
162
163 jtag_add_dr_scan(3, fields, TAP_PD);
164
165 if (debug_reason & 0x4)
166 if (debug_reason & 0x2)
167 target->debug_reason = DBG_REASON_WPTANDBKPT;
168 else
169 target->debug_reason = DBG_REASON_WATCHPOINT;
170 else
171 target->debug_reason = DBG_REASON_BREAKPOINT;
172 }
173
174 return ERROR_OK;
175 }
176
177 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
178 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
179 {
180 scan_field_t fields[3];
181 u8 out_buf[4];
182 u8 instr_buf[4];
183 u8 sysspeed_buf = 0x0;
184
185 /* prepare buffer */
186 buf_set_u32(out_buf, 0, 32, out);
187
188 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
189
190 if (sysspeed)
191 buf_set_u32(&sysspeed_buf, 2, 1, 1);
192
193 jtag_add_end_state(TAP_PD);
194 arm_jtag_scann(jtag_info, 0x1);
195
196 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
197
198 fields[0].device = jtag_info->chain_pos;
199 fields[0].num_bits = 32;
200 fields[0].out_value = out_buf;
201 fields[0].out_mask = NULL;
202 fields[0].in_value = NULL;
203 if (in)
204 {
205 fields[0].in_handler = arm_jtag_buf_to_u32;
206 fields[0].in_handler_priv = in;
207 }
208 else
209 {
210 fields[0].in_handler = NULL;
211 fields[0].in_handler_priv = NULL;
212 }
213 fields[0].in_check_value = NULL;
214 fields[0].in_check_mask = NULL;
215
216 fields[1].device = jtag_info->chain_pos;
217 fields[1].num_bits = 3;
218 fields[1].out_value = &sysspeed_buf;
219 fields[1].out_mask = NULL;
220 fields[1].in_value = NULL;
221 fields[1].in_check_value = NULL;
222 fields[1].in_check_mask = NULL;
223 fields[1].in_handler = NULL;
224 fields[1].in_handler_priv = NULL;
225
226 fields[2].device = jtag_info->chain_pos;
227 fields[2].num_bits = 32;
228 fields[2].out_value = instr_buf;
229 fields[2].out_mask = NULL;
230 fields[2].in_value = NULL;
231 fields[2].in_check_value = NULL;
232 fields[2].in_check_mask = NULL;
233 fields[2].in_handler = NULL;
234 fields[2].in_handler_priv = NULL;
235
236 jtag_add_dr_scan(3, fields, -1);
237
238 jtag_add_runtest(0, -1);
239
240 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
241 {
242 jtag_execute_queue();
243
244 if (in)
245 {
246 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
247 }
248 else
249 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
250 }
251 #endif
252
253 return ERROR_OK;
254 }
255
256 /* just read data (instruction and data-out = don't care) */
257 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
258 {
259 scan_field_t fields[3];
260
261 jtag_add_end_state(TAP_PD);
262 arm_jtag_scann(jtag_info, 0x1);
263
264 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
265
266 fields[0].device = jtag_info->chain_pos;
267 fields[0].num_bits = 32;
268 fields[0].out_value = NULL;
269 fields[0].out_mask = NULL;
270 fields[0].in_value = NULL;
271 fields[0].in_handler = arm_jtag_buf_to_u32;
272 fields[0].in_handler_priv = in;
273 fields[0].in_check_value = NULL;
274 fields[0].in_check_mask = NULL;
275
276 fields[1].device = jtag_info->chain_pos;
277 fields[1].num_bits = 3;
278 fields[1].out_value = NULL;
279 fields[1].out_mask = NULL;
280 fields[1].in_value = NULL;
281 fields[1].in_handler = NULL;
282 fields[1].in_handler_priv = NULL;
283 fields[1].in_check_value = NULL;
284 fields[1].in_check_mask = NULL;
285
286 fields[2].device = jtag_info->chain_pos;
287 fields[2].num_bits = 32;
288 fields[2].out_value = NULL;
289 fields[2].out_mask = NULL;
290 fields[2].in_value = NULL;
291 fields[2].in_check_value = NULL;
292 fields[2].in_check_mask = NULL;
293 fields[2].in_handler = NULL;
294 fields[2].in_handler_priv = NULL;
295
296 jtag_add_dr_scan(3, fields, -1);
297
298 jtag_add_runtest(0, -1);
299
300 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
301 {
302 jtag_execute_queue();
303
304 if (in)
305 {
306 LOG_DEBUG("in: 0x%8.8x", *in);
307 }
308 else
309 {
310 LOG_ERROR("BUG: called with in == NULL");
311 }
312 }
313 #endif
314
315 return ERROR_OK;
316 }
317
318 /* clock the target, and read the databus
319 * the *in pointer points to a buffer where elements of 'size' bytes
320 * are stored in big (be==1) or little (be==0) endianness
321 */
322 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
323 {
324 scan_field_t fields[3];
325
326 jtag_add_end_state(TAP_PD);
327 arm_jtag_scann(jtag_info, 0x1);
328
329 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
330
331 fields[0].device = jtag_info->chain_pos;
332 fields[0].num_bits = 32;
333 fields[0].out_value = NULL;
334 fields[0].out_mask = NULL;
335 fields[0].in_value = NULL;
336 switch (size)
337 {
338 case 4:
339 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
340 break;
341 case 2:
342 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
343 break;
344 case 1:
345 fields[0].in_handler = arm_jtag_buf_to_8;
346 break;
347 }
348 fields[0].in_handler_priv = in;
349 fields[0].in_check_value = NULL;
350 fields[0].in_check_mask = NULL;
351
352 fields[1].device = jtag_info->chain_pos;
353 fields[1].num_bits = 3;
354 fields[1].out_value = NULL;
355 fields[1].out_mask = NULL;
356 fields[1].in_value = NULL;
357 fields[1].in_handler = NULL;
358 fields[1].in_handler_priv = NULL;
359 fields[1].in_check_value = NULL;
360 fields[1].in_check_mask = NULL;
361
362 fields[2].device = jtag_info->chain_pos;
363 fields[2].num_bits = 32;
364 fields[2].out_value = NULL;
365 fields[2].out_mask = NULL;
366 fields[2].in_value = NULL;
367 fields[2].in_check_value = NULL;
368 fields[2].in_check_mask = NULL;
369 fields[2].in_handler = NULL;
370 fields[2].in_handler_priv = NULL;
371
372 jtag_add_dr_scan(3, fields, -1);
373
374 jtag_add_runtest(0, -1);
375
376 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
377 {
378 jtag_execute_queue();
379
380 if (in)
381 {
382 LOG_DEBUG("in: 0x%8.8x", *in);
383 }
384 else
385 {
386 LOG_ERROR("BUG: called with in == NULL");
387 }
388 }
389 #endif
390
391 return ERROR_OK;
392 }
393
394 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
395 {
396 /* get pointers to arch-specific information */
397 armv4_5_common_t *armv4_5 = target->arch_info;
398 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
399 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
400
401 /* save r0 before using it and put system in ARM state
402 * to allow common handling of ARM and THUMB debugging */
403
404 /* fetch STR r0, [r0] */
405 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
406 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
407 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
408 /* STR r0, [r0] in Memory */
409 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
410
411 /* MOV r0, r15 fetched, STR in Decode */
412 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
413 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
414 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
415 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
417 /* nothing fetched, STR r0, [r0] in Memory */
418 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
419
420 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
421 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
422 /* LDR in Decode */
423 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
424 /* LDR in Execute */
425 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
426 /* LDR in Memory (to account for interlock) */
427 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
428
429 /* fetch BX */
430 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
431 /* NOP fetched, BX in Decode, MOV in Execute */
432 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
433 /* NOP fetched, BX in Execute (1) */
434 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
435
436 jtag_execute_queue();
437
438 /* fix program counter:
439 * MOV r0, r15 was the 5th instruction (+8)
440 * reading PC in Thumb state gives address of instruction + 4
441 */
442 *pc -= 0xc;
443 }
444
445 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
446 {
447 int i;
448 /* get pointers to arch-specific information */
449 armv4_5_common_t *armv4_5 = target->arch_info;
450 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
451 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
452
453 /* STMIA r0-15, [r0] at debug speed
454 * register values will start to appear on 4th DCLK
455 */
456 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
457
458 /* fetch NOP, STM in DECODE stage */
459 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
460 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
461 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
462
463 for (i = 0; i <= 15; i++)
464 {
465 if (mask & (1 << i))
466 /* nothing fetched, STM in MEMORY (i'th cycle) */
467 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
468 }
469
470 }
471
472 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
473 {
474 int i;
475 /* get pointers to arch-specific information */
476 armv4_5_common_t *armv4_5 = target->arch_info;
477 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
478 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
479 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
480 u32 *buf_u32 = buffer;
481 u16 *buf_u16 = buffer;
482 u8 *buf_u8 = buffer;
483
484 /* STMIA r0-15, [r0] at debug speed
485 * register values will start to appear on 4th DCLK
486 */
487 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
488
489 /* fetch NOP, STM in DECODE stage */
490 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
491 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
492 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
493
494 for (i = 0; i <= 15; i++)
495 {
496 if (mask & (1 << i))
497 /* nothing fetched, STM in MEMORY (i'th cycle) */
498 switch (size)
499 {
500 case 4:
501 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
502 break;
503 case 2:
504 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
505 break;
506 case 1:
507 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
508 break;
509 }
510 }
511
512 }
513
514 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
515 {
516 /* get pointers to arch-specific information */
517 armv4_5_common_t *armv4_5 = target->arch_info;
518 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
519 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
520
521 /* MRS r0, cpsr */
522 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
523 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
524 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
525 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
526 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
527
528 /* STR r0, [r15] */
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
530 /* fetch NOP, STR in DECODE stage */
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
532 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534 /* nothing fetched, STR in MEMORY */
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
536
537 }
538
539 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
540 {
541 /* get pointers to arch-specific information */
542 armv4_5_common_t *armv4_5 = target->arch_info;
543 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
544 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
545
546 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
547
548 /* MSR1 fetched */
549 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
550 /* MSR2 fetched, MSR1 in DECODE */
551 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
552 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
553 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
554 /* nothing fetched, MSR1 in EXECUTE (2) */
555 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
556 /* nothing fetched, MSR1 in EXECUTE (3) */
557 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
558 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
559 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
560 /* nothing fetched, MSR2 in EXECUTE (2) */
561 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
562 /* nothing fetched, MSR2 in EXECUTE (3) */
563 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
564 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
565 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
566 /* nothing fetched, MSR3 in EXECUTE (2) */
567 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
568 /* nothing fetched, MSR3 in EXECUTE (3) */
569 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
570 /* NOP fetched, MSR4 in EXECUTE (1) */
571 /* last MSR writes flags, which takes only one cycle */
572 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
573 }
574
575 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
576 {
577 /* get pointers to arch-specific information */
578 armv4_5_common_t *armv4_5 = target->arch_info;
579 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
580 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
581
582 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
583
584 /* MSR fetched */
585 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
586 /* NOP fetched, MSR in DECODE */
587 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
588 /* NOP fetched, MSR in EXECUTE (1) */
589 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
590
591 /* rot == 4 writes flags, which takes only one cycle */
592 if (rot != 4)
593 {
594 /* nothing fetched, MSR in EXECUTE (2) */
595 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
596 /* nothing fetched, MSR in EXECUTE (3) */
597 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
598 }
599 }
600
601 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
602 {
603 int i;
604 /* get pointers to arch-specific information */
605 armv4_5_common_t *armv4_5 = target->arch_info;
606 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
607 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
608
609 /* LDMIA r0-15, [r0] at debug speed
610 * register values will start to appear on 4th DCLK
611 */
612 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
613
614 /* fetch NOP, LDM in DECODE stage */
615 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
616 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
617 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
618
619 for (i = 0; i <= 15; i++)
620 {
621 if (mask & (1 << i))
622 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
623 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
624 }
625 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
626
627 }
628
629 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
630 {
631 /* get pointers to arch-specific information */
632 armv4_5_common_t *armv4_5 = target->arch_info;
633 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
634 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
635
636 /* put system-speed load-multiple into the pipeline */
637 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
638 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
639
640 }
641
642 void arm9tdmi_load_hword_reg(target_t *target, int num)
643 {
644 /* get pointers to arch-specific information */
645 armv4_5_common_t *armv4_5 = target->arch_info;
646 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
647 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
648
649 /* put system-speed load half-word into the pipeline */
650 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
651 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
652 }
653
654 void arm9tdmi_load_byte_reg(target_t *target, int num)
655 {
656 /* get pointers to arch-specific information */
657 armv4_5_common_t *armv4_5 = target->arch_info;
658 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
659 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
660
661 /* put system-speed load byte into the pipeline */
662 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
663 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
664
665 }
666
667 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
668 {
669 /* get pointers to arch-specific information */
670 armv4_5_common_t *armv4_5 = target->arch_info;
671 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
672 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
673
674 /* put system-speed store-multiple into the pipeline */
675 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
676 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
677
678 }
679
680 void arm9tdmi_store_hword_reg(target_t *target, int num)
681 {
682 /* get pointers to arch-specific information */
683 armv4_5_common_t *armv4_5 = target->arch_info;
684 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
685 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
686
687 /* put system-speed store half-word into the pipeline */
688 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
689 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
690
691 }
692
693 void arm9tdmi_store_byte_reg(target_t *target, int num)
694 {
695 /* get pointers to arch-specific information */
696 armv4_5_common_t *armv4_5 = target->arch_info;
697 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
698 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
699
700 /* put system-speed store byte into the pipeline */
701 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
702 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
703
704 }
705
706 void arm9tdmi_write_pc(target_t *target, u32 pc)
707 {
708 /* get pointers to arch-specific information */
709 armv4_5_common_t *armv4_5 = target->arch_info;
710 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
711 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
712
713 /* LDMIA r0-15, [r0] at debug speed
714 * register values will start to appear on 4th DCLK
715 */
716 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
717
718 /* fetch NOP, LDM in DECODE stage */
719 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
720 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
721 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
722 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
723 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
724 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
725 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
726 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
727 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
728 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
729 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
730
731 }
732
733 void arm9tdmi_branch_resume(target_t *target)
734 {
735 /* get pointers to arch-specific information */
736 armv4_5_common_t *armv4_5 = target->arch_info;
737 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
738 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
739
740 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
741 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
742
743 }
744
745 void arm9tdmi_branch_resume_thumb(target_t *target)
746 {
747 LOG_DEBUG("-");
748
749 /* get pointers to arch-specific information */
750 armv4_5_common_t *armv4_5 = target->arch_info;
751 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
752 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
753 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
754
755 /* LDMIA r0-15, [r0] at debug speed
756 * register values will start to appear on 4th DCLK
757 */
758 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
759
760 /* fetch NOP, LDM in DECODE stage */
761 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
762 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
763 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
764 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
765 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
766 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
767 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
768
769 /* Branch and eXchange */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
771
772 embeddedice_read_reg(dbg_stat);
773
774 /* fetch NOP, BX in DECODE stage */
775 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
776
777 embeddedice_read_reg(dbg_stat);
778
779 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
780 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
781
782 /* target is now in Thumb state */
783 embeddedice_read_reg(dbg_stat);
784
785 /* load r0 value, MOV_IM in Decode*/
786 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
787 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
788 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
789 /* fetch NOP, LDR in Execute */
790 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
791 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
792 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
793 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
794 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
795
796 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
797 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
798
799 embeddedice_read_reg(dbg_stat);
800
801 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
802 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
803
804 }
805
806 void arm9tdmi_enable_single_step(target_t *target)
807 {
808 /* get pointers to arch-specific information */
809 armv4_5_common_t *armv4_5 = target->arch_info;
810 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
811
812 if (arm7_9->has_single_step)
813 {
814 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
815 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
816 }
817 else
818 {
819 arm7_9_enable_eice_step(target);
820 }
821 }
822
823 void arm9tdmi_disable_single_step(target_t *target)
824 {
825 /* get pointers to arch-specific information */
826 armv4_5_common_t *armv4_5 = target->arch_info;
827 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
828
829 if (arm7_9->has_single_step)
830 {
831 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
832 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
833 }
834 else
835 {
836 arm7_9_disable_eice_step(target);
837 }
838 }
839
840 void arm9tdmi_build_reg_cache(target_t *target)
841 {
842 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
843 /* get pointers to arch-specific information */
844 armv4_5_common_t *armv4_5 = target->arch_info;
845 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
846 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
847
848 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
849 armv4_5->core_cache = (*cache_p);
850
851 /* one extra register (vector catch) */
852 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
853 arm7_9->eice_cache = (*cache_p)->next;
854
855 if (arm7_9->etm_ctx)
856 {
857 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
858 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
859 }
860 }
861
862 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
863 {
864
865 arm9tdmi_build_reg_cache(target);
866
867 return ERROR_OK;
868
869 }
870
871 int arm9tdmi_quit()
872 {
873
874 return ERROR_OK;
875 }
876
877 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
878 {
879 armv4_5_common_t *armv4_5;
880 arm7_9_common_t *arm7_9;
881
882 arm7_9 = &arm9tdmi->arm7_9_common;
883 armv4_5 = &arm7_9->armv4_5_common;
884
885 /* prepare JTAG information for the new target */
886 arm7_9->jtag_info.chain_pos = chain_pos;
887 arm7_9->jtag_info.scann_size = 5;
888
889 /* register arch-specific functions */
890 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
891 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
892 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
893 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
894 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
895
896 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
897 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
898 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
899
900 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
901 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
902 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
903
904 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
905 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
906 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
907
908 arm7_9->write_pc = arm9tdmi_write_pc;
909 arm7_9->branch_resume = arm9tdmi_branch_resume;
910 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
911
912 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
913 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
914
915 arm7_9->pre_debug_entry = NULL;
916 arm7_9->post_debug_entry = NULL;
917
918 arm7_9->pre_restore_context = NULL;
919 arm7_9->post_restore_context = NULL;
920
921 /* initialize arch-specific breakpoint handling */
922 arm7_9->arm_bkpt = 0xdeeedeee;
923 arm7_9->thumb_bkpt = 0xdeee;
924
925 arm7_9->sw_bkpts_use_wp = 1;
926 arm7_9->sw_bkpts_enabled = 0;
927 arm7_9->dbgreq_adjust_pc = 3;
928 arm7_9->arch_info = arm9tdmi;
929
930 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
931 arm9tdmi->arch_info = NULL;
932
933 if (variant)
934 {
935 arm9tdmi->variant = strdup(variant);
936 }
937 else
938 {
939 arm9tdmi->variant = strdup("");
940 }
941
942 arm7_9_init_arch_info(target, arm7_9);
943
944 /* override use of DBGRQ, this is safe on ARM9TDMI */
945 arm7_9->use_dbgrq = 1;
946
947 /* all ARM9s have the vector catch register */
948 arm7_9->has_vector_catch = 1;
949
950 return ERROR_OK;
951 }
952
953 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
954 {
955 armv4_5_common_t *armv4_5 = target->arch_info;
956 arm7_9_common_t *arm7_9;
957 arm9tdmi_common_t *arm9tdmi;
958
959 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
960 {
961 return -1;
962 }
963
964 arm7_9 = armv4_5->arch_info;
965 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
966 {
967 return -1;
968 }
969
970 arm9tdmi = arm7_9->arch_info;
971 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
972 {
973 return -1;
974 }
975
976 *armv4_5_p = armv4_5;
977 *arm7_9_p = arm7_9;
978 *arm9tdmi_p = arm9tdmi;
979
980 return ERROR_OK;
981 }
982
983
984 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
985 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
986 {
987 int chain_pos;
988 char *variant = NULL;
989 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
990 memset(arm9tdmi, 0, sizeof(*arm9tdmi));
991
992 if (argc < 4)
993 {
994 LOG_ERROR("'target arm9tdmi' requires at least one additional argument");
995 exit(-1);
996 }
997
998 chain_pos = strtoul(args[3], NULL, 0);
999
1000 if (argc >= 5)
1001 variant = args[4];
1002
1003 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1004
1005 return ERROR_OK;
1006 }
1007
1008 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1009 {
1010 int retval;
1011
1012 command_t *arm9tdmi_cmd;
1013
1014
1015 retval = arm7_9_register_commands(cmd_ctx);
1016
1017 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1018
1019 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1020
1021
1022 return ERROR_OK;
1023
1024 }
1025
1026 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1027 {
1028 target_t *target = get_current_target(cmd_ctx);
1029 armv4_5_common_t *armv4_5;
1030 arm7_9_common_t *arm7_9;
1031 arm9tdmi_common_t *arm9tdmi;
1032 reg_t *vector_catch;
1033 u32 vector_catch_value;
1034 int i, j;
1035
1036 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1037 {
1038 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1039 return ERROR_OK;
1040 }
1041
1042 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1043
1044 /* read the vector catch register if necessary */
1045 if (!vector_catch->valid)
1046 embeddedice_read_reg(vector_catch);
1047
1048 /* get the current setting */
1049 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1050
1051 if (argc > 0)
1052 {
1053 vector_catch_value = 0x0;
1054 if (strcmp(args[0], "all") == 0)
1055 {
1056 vector_catch_value = 0xdf;
1057 }
1058 else if (strcmp(args[0], "none") == 0)
1059 {
1060 /* do nothing */
1061 }
1062 else
1063 {
1064 for (i = 0; i < argc; i++)
1065 {
1066 /* go through list of vectors */
1067 for(j = 0; arm9tdmi_vectors[j].name; j++)
1068 {
1069 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1070 {
1071 vector_catch_value |= arm9tdmi_vectors[j].value;
1072 break;
1073 }
1074 }
1075
1076 /* complain if vector wasn't found */
1077 if (!arm9tdmi_vectors[j].name)
1078 {
1079 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1080
1081 /* reread current setting */
1082 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1083
1084 break;
1085 }
1086 }
1087 }
1088
1089 /* store new settings */
1090 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1091 embeddedice_store_reg(vector_catch);
1092 }
1093
1094 /* output current settings (skip RESERVED vector) */
1095 for (i = 0; i < 8; i++)
1096 {
1097 if (i != 5)
1098 {
1099 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1100 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1101 }
1102 }
1103
1104 return ERROR_OK;
1105 }
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