1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * Copyright (C) 2019-2021, Ampere Computing LLC *
18 * This program is free software; you can redistribute it and/or modify *
19 * it under the terms of the GNU General Public License as published by *
20 * the Free Software Foundation; either version 2 of the License, or *
21 * (at your option) any later version. *
23 * This program is distributed in the hope that it will be useful, *
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
26 * GNU General Public License for more details. *
28 * You should have received a copy of the GNU General Public License *
29 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focuses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction pipelining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include "arm_coresight.h"
80 #include "transport/transport.h"
81 #include <helper/align.h>
82 #include <helper/jep106.h>
83 #include <helper/time_support.h>
84 #include <helper/list.h>
85 #include <helper/jim-nvp.h>
87 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
90 uint32_t tar_block_size(uint32_t address)
91 Return the largest block starting at address that does not cross a tar block size alignment boundary
93 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, target_addr_t address
)
95 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
98 /***************************************************************************
100 * DP and MEM-AP register access through APACC and DPACC *
102 ***************************************************************************/
104 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
106 csw
|= ap
->csw_default
;
108 if (csw
!= ap
->csw_value
) {
109 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
110 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_CSW
, csw
);
111 if (retval
!= ERROR_OK
) {
120 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, target_addr_t tar
)
122 if (!ap
->tar_valid
|| tar
!= ap
->tar_value
) {
123 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
124 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR
, (uint32_t)(tar
& 0xffffffffUL
));
125 if (retval
== ERROR_OK
&& is_64bit_ap(ap
)) {
126 /* See if bits 63:32 of tar is different from last setting */
127 if ((ap
->tar_value
>> 32) != (tar
>> 32))
128 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR64
, (uint32_t)(tar
>> 32));
130 if (retval
!= ERROR_OK
) {
131 ap
->tar_valid
= false;
135 ap
->tar_valid
= true;
140 static int mem_ap_read_tar(struct adiv5_ap
*ap
, target_addr_t
*tar
)
145 int retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR
, &lower
);
146 if (retval
== ERROR_OK
&& is_64bit_ap(ap
))
147 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR64
, &upper
);
149 if (retval
!= ERROR_OK
) {
150 ap
->tar_valid
= false;
154 retval
= dap_run(ap
->dap
);
155 if (retval
!= ERROR_OK
) {
156 ap
->tar_valid
= false;
160 *tar
= (((target_addr_t
)upper
) << 32) | (target_addr_t
)lower
;
162 ap
->tar_value
= *tar
;
163 ap
->tar_valid
= true;
167 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap
*ap
)
169 switch (ap
->csw_value
& CSW_ADDRINC_MASK
) {
170 case CSW_ADDRINC_SINGLE
:
171 switch (ap
->csw_value
& CSW_SIZE_MASK
) {
181 case CSW_ADDRINC_PACKED
:
187 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
189 static void mem_ap_update_tar_cache(struct adiv5_ap
*ap
)
194 uint32_t inc
= mem_ap_get_tar_increment(ap
);
195 if (inc
>= max_tar_block_size(ap
->tar_autoincr_block
, ap
->tar_value
))
196 ap
->tar_valid
= false;
198 ap
->tar_value
+= inc
;
202 * Queue transactions setting up transfer parameters for the
203 * currently selected MEM-AP.
205 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
206 * initiate data reads or writes using memory or peripheral addresses.
207 * If the CSW is configured for it, the TAR may be automatically
208 * incremented after each transfer.
210 * @param ap The MEM-AP.
211 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
212 * matches the cached value, the register is not changed.
213 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
214 * matches the cached address, the register is not changed.
216 * @return ERROR_OK if the transaction was properly queued, else a fault code.
218 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, target_addr_t tar
)
221 retval
= mem_ap_setup_csw(ap
, csw
);
222 if (retval
!= ERROR_OK
)
224 retval
= mem_ap_setup_tar(ap
, tar
);
225 if (retval
!= ERROR_OK
)
231 * Asynchronous (queued) read of a word from memory or a system register.
233 * @param ap The MEM-AP to access.
234 * @param address Address of the 32-bit word to read; it must be
235 * readable by the currently selected MEM-AP.
236 * @param value points to where the word will be stored when the
237 * transaction queue is flushed (assuming no errors).
239 * @return ERROR_OK for success. Otherwise a fault code.
241 int mem_ap_read_u32(struct adiv5_ap
*ap
, target_addr_t address
,
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when reading several consecutive addresses.
249 retval
= mem_ap_setup_transfer(ap
,
250 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
251 address
& 0xFFFFFFFFFFFFFFF0ull
);
252 if (retval
!= ERROR_OK
)
255 return dap_queue_ap_read(ap
, MEM_AP_REG_BD0
| (address
& 0xC), value
);
259 * Synchronous read of a word from memory or a system register.
260 * As a side effect, this flushes any queued transactions.
262 * @param ap The MEM-AP to access.
263 * @param address Address of the 32-bit word to read; it must be
264 * readable by the currently selected MEM-AP.
265 * @param value points to where the result will be stored.
267 * @return ERROR_OK for success; *value holds the result.
268 * Otherwise a fault code.
270 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, target_addr_t address
,
275 retval
= mem_ap_read_u32(ap
, address
, value
);
276 if (retval
!= ERROR_OK
)
279 return dap_run(ap
->dap
);
283 * Asynchronous (queued) write of a word to memory or a system register.
285 * @param ap The MEM-AP to access.
286 * @param address Address to be written; it must be writable by
287 * the currently selected MEM-AP.
288 * @param value Word that will be written to the address when transaction
289 * queue is flushed (assuming no errors).
291 * @return ERROR_OK for success. Otherwise a fault code.
293 int mem_ap_write_u32(struct adiv5_ap
*ap
, target_addr_t address
,
298 /* Use banked addressing (REG_BDx) to avoid some link traffic
299 * (updating TAR) when writing several consecutive addresses.
301 retval
= mem_ap_setup_transfer(ap
,
302 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
303 address
& 0xFFFFFFFFFFFFFFF0ull
);
304 if (retval
!= ERROR_OK
)
307 return dap_queue_ap_write(ap
, MEM_AP_REG_BD0
| (address
& 0xC),
312 * Synchronous write of a word to memory or a system register.
313 * As a side effect, this flushes any queued transactions.
315 * @param ap The MEM-AP to access.
316 * @param address Address to be written; it must be writable by
317 * the currently selected MEM-AP.
318 * @param value Word that will be written.
320 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
322 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, target_addr_t address
,
325 int retval
= mem_ap_write_u32(ap
, address
, value
);
327 if (retval
!= ERROR_OK
)
330 return dap_run(ap
->dap
);
334 * Synchronous write of a block of memory, using a specific access size.
336 * @param ap The MEM-AP to access.
337 * @param buffer The data buffer to write. No particular alignment is assumed.
338 * @param size Which access size to use, in bytes. 1, 2 or 4.
339 * @param count The number of writes to do (in size units, not bytes).
340 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
341 * @param addrinc Whether the target address should be increased for each write or not. This
342 * should normally be true, except when writing to e.g. a FIFO.
343 * @return ERROR_OK on success, otherwise an error code.
345 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
346 target_addr_t address
, bool addrinc
)
348 struct adiv5_dap
*dap
= ap
->dap
;
349 size_t nbytes
= size
* count
;
350 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
352 target_addr_t addr_xor
;
353 int retval
= ERROR_OK
;
355 /* TI BE-32 Quirks mode:
356 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
357 * size write address bytes written in order
358 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
359 * 2 TAR ^ 2 (val >> 8), (val)
361 * For example, if you attempt to write a single byte to address 0, the processor
362 * will actually write a byte to address 3.
364 * To make writes of size < 4 work as expected, we xor a value with the address before
365 * setting the TAP, and we set the TAP after every transfer rather then relying on
366 * address increment. */
369 csw_size
= CSW_32BIT
;
371 } else if (size
== 2) {
372 csw_size
= CSW_16BIT
;
373 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
374 } else if (size
== 1) {
376 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
378 return ERROR_TARGET_UNALIGNED_ACCESS
;
381 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
382 return ERROR_TARGET_UNALIGNED_ACCESS
;
385 uint32_t this_size
= size
;
387 /* Select packed transfer if possible */
388 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
389 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
391 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
393 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
396 if (retval
!= ERROR_OK
)
399 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
400 if (retval
!= ERROR_OK
)
403 /* How many source bytes each transfer will consume, and their location in the DRW,
404 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
405 uint32_t outvalue
= 0;
406 uint32_t drw_byte_idx
= address
;
407 if (dap
->ti_be_32_quirks
) {
410 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
411 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
412 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
413 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
& 3) ^ addr_xor
);
416 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
417 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
& 3) ^ addr_xor
);
420 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (drw_byte_idx
& 3) ^ addr_xor
);
426 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
427 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
430 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
433 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
& 3);
439 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_DRW
, outvalue
);
440 if (retval
!= ERROR_OK
)
443 mem_ap_update_tar_cache(ap
);
445 address
+= this_size
;
448 /* REVISIT: Might want to have a queued version of this function that does not run. */
449 if (retval
== ERROR_OK
)
450 retval
= dap_run(dap
);
452 if (retval
!= ERROR_OK
) {
454 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
)
455 LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT
, tar
);
457 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
464 * Synchronous read of a block of memory, using a specific access size.
466 * @param ap The MEM-AP to access.
467 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
468 * @param size Which access size to use, in bytes. 1, 2 or 4.
469 * @param count The number of reads to do (in size units, not bytes).
470 * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
471 * @param addrinc Whether the target address should be increased after each read or not. This
472 * should normally be true, except when reading from e.g. a FIFO.
473 * @return ERROR_OK on success, otherwise an error code.
475 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
476 target_addr_t adr
, bool addrinc
)
478 struct adiv5_dap
*dap
= ap
->dap
;
479 size_t nbytes
= size
* count
;
480 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
482 target_addr_t address
= adr
;
483 int retval
= ERROR_OK
;
485 /* TI BE-32 Quirks mode:
486 * Reads on big-endian TMS570 behave strangely differently than writes.
487 * They read from the physical address requested, but with DRW byte-reversed.
488 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
489 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
493 csw_size
= CSW_32BIT
;
495 csw_size
= CSW_16BIT
;
499 return ERROR_TARGET_UNALIGNED_ACCESS
;
501 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
502 return ERROR_TARGET_UNALIGNED_ACCESS
;
504 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
505 * over-allocation if packed transfers are going to be used, but determining the real need at
506 * this point would be messy. */
507 uint32_t *read_buf
= calloc(count
, sizeof(uint32_t));
508 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
509 uint32_t *read_ptr
= read_buf
;
511 LOG_ERROR("Failed to allocate read buffer");
515 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
516 * useful bytes it contains, and their location in the word, depends on the type of transfer
519 uint32_t this_size
= size
;
521 /* Select packed transfer if possible */
522 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
523 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
525 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
527 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
529 if (retval
!= ERROR_OK
)
532 retval
= mem_ap_setup_tar(ap
, address
);
533 if (retval
!= ERROR_OK
)
536 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_DRW
, read_ptr
++);
537 if (retval
!= ERROR_OK
)
542 address
+= this_size
;
544 mem_ap_update_tar_cache(ap
);
547 if (retval
== ERROR_OK
)
548 retval
= dap_run(dap
);
552 nbytes
= size
* count
;
555 /* If something failed, read TAR to find out how much data was successfully read, so we can
556 * at least give the caller what we have. */
557 if (retval
!= ERROR_OK
) {
559 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
) {
560 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
561 LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT
, tar
);
562 if (nbytes
> tar
- address
)
563 nbytes
= tar
- address
;
565 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
570 /* Replay loop to populate caller's buffer from the correct word and byte lane */
572 uint32_t this_size
= size
;
574 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
575 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
579 if (dap
->ti_be_32_quirks
) {
582 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
583 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
586 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
589 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
594 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
595 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
598 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
601 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
613 int mem_ap_read_buf(struct adiv5_ap
*ap
,
614 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
616 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
619 int mem_ap_write_buf(struct adiv5_ap
*ap
,
620 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
622 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
625 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
626 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
628 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
631 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
632 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
634 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
637 /*--------------------------------------------------------------------------*/
640 #define DAP_POWER_DOMAIN_TIMEOUT (10)
642 /*--------------------------------------------------------------------------*/
645 * Invalidate cached DP select and cached TAR and CSW of all APs
647 void dap_invalidate_cache(struct adiv5_dap
*dap
)
649 dap
->select
= DP_SELECT_INVALID
;
650 dap
->last_read
= NULL
;
653 for (i
= 0; i
<= DP_APSEL_MAX
; i
++) {
654 /* force csw and tar write on the next mem-ap access */
655 dap
->ap
[i
].tar_valid
= false;
656 dap
->ap
[i
].csw_value
= 0;
661 * Initialize a DAP. This sets up the power domains, prepares the DP
662 * for further use and activates overrun checking.
664 * @param dap The DAP being initialized.
666 int dap_dp_init(struct adiv5_dap
*dap
)
670 LOG_DEBUG("%s", adiv5_dap_name(dap
));
672 dap
->do_reconnect
= false;
673 dap_invalidate_cache(dap
);
676 * Early initialize dap->dp_ctrl_stat.
677 * In jtag mode only, if the following queue run (in dap_dp_poll_register)
678 * fails and sets the sticky error, it will trigger the clearing
679 * of the sticky. Without this initialization system and debug power
680 * would be disabled while clearing the sticky error bit.
682 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
685 * This write operation clears the sticky error bit in jtag mode only and
686 * is ignored in swd mode. It also powers-up system and debug domains in
687 * both jtag and swd modes, if not done before.
689 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
| SSTICKYERR
);
690 if (retval
!= ERROR_OK
)
693 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
694 if (retval
!= ERROR_OK
)
697 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
698 if (retval
!= ERROR_OK
)
701 /* Check that we have debug power domains activated */
702 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
703 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
704 CDBGPWRUPACK
, CDBGPWRUPACK
,
705 DAP_POWER_DOMAIN_TIMEOUT
);
706 if (retval
!= ERROR_OK
)
709 if (!dap
->ignore_syspwrupack
) {
710 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
711 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
712 CSYSPWRUPACK
, CSYSPWRUPACK
,
713 DAP_POWER_DOMAIN_TIMEOUT
);
714 if (retval
!= ERROR_OK
)
718 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
719 if (retval
!= ERROR_OK
)
722 /* With debug power on we can activate OVERRUN checking */
723 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
724 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
725 if (retval
!= ERROR_OK
)
727 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
728 if (retval
!= ERROR_OK
)
731 retval
= dap_run(dap
);
732 if (retval
!= ERROR_OK
)
739 * Initialize a DAP or do reconnect if DAP is not accessible.
741 * @param dap The DAP being initialized.
743 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
)
745 LOG_DEBUG("%s", adiv5_dap_name(dap
));
748 * Early initialize dap->dp_ctrl_stat.
749 * In jtag mode only, if the following atomic reads fail and set the
750 * sticky error, it will trigger the clearing of the sticky. Without this
751 * initialization system and debug power would be disabled while clearing
752 * the sticky error bit.
754 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
756 dap
->do_reconnect
= false;
758 dap_dp_read_atomic(dap
, DP_CTRL_STAT
, NULL
);
759 if (dap
->do_reconnect
) {
760 /* dap connect calls dap_dp_init() after transport dependent initialization */
761 return dap
->ops
->connect(dap
);
763 return dap_dp_init(dap
);
768 * Initialize a DAP. This sets up the power domains, prepares the DP
769 * for further use, and arranges to use AP #0 for all AP operations
770 * until dap_ap-select() changes that policy.
772 * @param ap The MEM-AP being initialized.
774 int mem_ap_init(struct adiv5_ap
*ap
)
776 /* check that we support packed transfers */
779 struct adiv5_dap
*dap
= ap
->dap
;
781 /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
782 /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
783 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG
, &cfg
);
784 if (retval
!= ERROR_OK
)
787 retval
= dap_run(dap
);
788 if (retval
!= ERROR_OK
)
792 ap
->tar_valid
= false;
793 ap
->csw_value
= 0; /* force csw and tar write */
794 retval
= mem_ap_setup_transfer(ap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
795 if (retval
!= ERROR_OK
)
798 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CSW
, &csw
);
799 if (retval
!= ERROR_OK
)
802 retval
= dap_run(dap
);
803 if (retval
!= ERROR_OK
)
806 if (csw
& CSW_ADDRINC_PACKED
)
807 ap
->packed_transfers
= true;
809 ap
->packed_transfers
= false;
811 /* Packed transfers on TI BE-32 processors do not work correctly in
813 if (dap
->ti_be_32_quirks
)
814 ap
->packed_transfers
= false;
816 LOG_DEBUG("MEM_AP Packed Transfers: %s",
817 ap
->packed_transfers
? "enabled" : "disabled");
819 /* The ARM ADI spec leaves implementation-defined whether unaligned
820 * memory accesses work, only work partially, or cause a sticky error.
821 * On TI BE-32 processors, reads seem to return garbage in some bytes
822 * and unaligned writes seem to cause a sticky error.
823 * TODO: it would be nice to have a way to detect whether unaligned
824 * operations are supported on other processors. */
825 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
827 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
828 !!(cfg
& MEM_AP_REG_CFG_LD
), !!(cfg
& MEM_AP_REG_CFG_LA
), !!(cfg
& MEM_AP_REG_CFG_BE
));
834 * Put the debug link into SWD mode, if the target supports it.
835 * The link's initial mode may be either JTAG (for example,
836 * with SWJ-DP after reset) or SWD.
838 * Note that targets using the JTAG-DP do not support SWD, and that
839 * some targets which could otherwise support it may have been
840 * configured to disable SWD signaling
842 * @param dap The DAP used
843 * @return ERROR_OK or else a fault code.
845 int dap_to_swd(struct adiv5_dap
*dap
)
847 LOG_DEBUG("Enter SWD mode");
849 return dap_send_sequence(dap
, JTAG_TO_SWD
);
853 * Put the debug link into JTAG mode, if the target supports it.
854 * The link's initial mode may be either SWD or JTAG.
856 * Note that targets implemented with SW-DP do not support JTAG, and
857 * that some targets which could otherwise support it may have been
858 * configured to disable JTAG signaling
860 * @param dap The DAP used
861 * @return ERROR_OK or else a fault code.
863 int dap_to_jtag(struct adiv5_dap
*dap
)
865 LOG_DEBUG("Enter JTAG mode");
867 return dap_send_sequence(dap
, SWD_TO_JTAG
);
870 /* CID interpretation -- see ARM IHI 0029E table B2-7
871 * and ARM IHI 0031E table D1-2.
873 * From 2009/11/25 commit 21378f58b604:
874 * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
875 * Let's keep it as is, for the time being
877 static const char *class_description
[16] = {
878 [0x0] = "Generic verification component",
887 [0x9] = "CoreSight component",
889 [0xB] = "Peripheral Test Block",
891 [0xD] = "OptimoDE DESS", /* see above */
892 [0xE] = "Generic IP component",
893 [0xF] = "CoreLink, PrimeCell or System component",
896 #define ARCH_ID(architect, archid) ( \
897 (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
898 (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
901 static const struct {
903 const char *description
;
904 } class0x9_devarch
[] = {
905 /* keep same unsorted order as in ARM IHI0029E */
906 { ARCH_ID(ARM_ID
, 0x0A00), "RAS architecture" },
907 { ARCH_ID(ARM_ID
, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
908 { ARCH_ID(ARM_ID
, 0x1A02), "DWT architecture" },
909 { ARCH_ID(ARM_ID
, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
910 { ARCH_ID(ARM_ID
, 0x2A04), "Processor debug architecture (ARMv8-M)" },
911 { ARCH_ID(ARM_ID
, 0x6A05), "Processor debug architecture (ARMv8-R)" },
912 { ARCH_ID(ARM_ID
, 0x0A10), "PC sample-based profiling" },
913 { ARCH_ID(ARM_ID
, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
914 { ARCH_ID(ARM_ID
, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
915 { ARCH_ID(ARM_ID
, 0x6A15), "Processor debug architecture (v8.0-A)" },
916 { ARCH_ID(ARM_ID
, 0x7A15), "Processor debug architecture (v8.1-A)" },
917 { ARCH_ID(ARM_ID
, 0x8A15), "Processor debug architecture (v8.2-A)" },
918 { ARCH_ID(ARM_ID
, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
919 { ARCH_ID(ARM_ID
, 0x0A17), "Memory Access Port v2 architecture" },
920 { ARCH_ID(ARM_ID
, 0x0A27), "JTAG Access Port v2 architecture" },
921 { ARCH_ID(ARM_ID
, 0x0A31), "Basic trace router" },
922 { ARCH_ID(ARM_ID
, 0x0A37), "Power requestor" },
923 { ARCH_ID(ARM_ID
, 0x0A47), "Unknown Access Port v2 architecture" },
924 { ARCH_ID(ARM_ID
, 0x0A50), "HSSTP architecture" },
925 { ARCH_ID(ARM_ID
, 0x0A63), "System Trace Macrocell (STM) architecture" },
926 { ARCH_ID(ARM_ID
, 0x0A75), "CoreSight ELA architecture" },
927 { ARCH_ID(ARM_ID
, 0x0AF7), "CoreSight ROM architecture" },
930 #define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
931 #define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
933 static const char *class0x9_devarch_description(uint32_t devarch
)
935 if (!(devarch
& ARM_CS_C9_DEVARCH_PRESENT
))
936 return "not present";
938 for (unsigned int i
= 0; i
< ARRAY_SIZE(class0x9_devarch
); i
++)
939 if ((devarch
& DEVARCH_ID_MASK
) == class0x9_devarch
[i
].arch_id
)
940 return class0x9_devarch
[i
].description
;
945 static const struct {
947 const char *description
;
949 { AP_TYPE_JTAG_AP
, "JTAG-AP" },
950 { AP_TYPE_COM_AP
, "COM-AP" },
951 { AP_TYPE_AHB3_AP
, "MEM-AP AHB3" },
952 { AP_TYPE_APB_AP
, "MEM-AP APB2 or APB3" },
953 { AP_TYPE_AXI_AP
, "MEM-AP AXI3 or AXI4" },
954 { AP_TYPE_AHB5_AP
, "MEM-AP AHB5" },
955 { AP_TYPE_APB4_AP
, "MEM-AP APB4" },
956 { AP_TYPE_AXI5_AP
, "MEM-AP AXI5" },
957 { AP_TYPE_AHB5H_AP
, "MEM-AP AHB5 with enhanced HPROT" },
960 static const char *ap_type_to_description(enum ap_type type
)
962 for (unsigned int i
= 0; i
< ARRAY_SIZE(ap_types
); i
++)
963 if (type
== ap_types
[i
].type
)
964 return ap_types
[i
].description
;
970 * This function checks the ID for each access port to find the requested Access Port type
972 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
976 /* Maximum AP number is 255 since the SELECT register is 8 bits */
977 for (ap_num
= 0; ap_num
<= DP_APSEL_MAX
; ap_num
++) {
979 /* read the IDR register of the Access Port */
982 int retval
= dap_queue_ap_read(dap_ap(dap
, ap_num
), AP_REG_IDR
, &id_val
);
983 if (retval
!= ERROR_OK
)
986 retval
= dap_run(dap
);
988 /* Reading register for a non-existent AP should not cause an error,
989 * but just to be sure, try to continue searching if an error does happen.
991 if (retval
== ERROR_OK
&& (id_val
& AP_TYPE_MASK
) == type_to_find
) {
992 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
993 ap_type_to_description(type_to_find
),
996 *ap_out
= &dap
->ap
[ap_num
];
1001 LOG_DEBUG("No %s found", ap_type_to_description(type_to_find
));
1005 int dap_get_debugbase(struct adiv5_ap
*ap
,
1006 target_addr_t
*dbgbase
, uint32_t *apid
)
1008 struct adiv5_dap
*dap
= ap
->dap
;
1010 uint32_t baseptr_upper
, baseptr_lower
;
1012 if (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
) {
1013 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG
, &ap
->cfg_reg
);
1014 if (retval
!= ERROR_OK
)
1017 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE
, &baseptr_lower
);
1018 if (retval
!= ERROR_OK
)
1020 retval
= dap_queue_ap_read(ap
, AP_REG_IDR
, apid
);
1021 if (retval
!= ERROR_OK
)
1023 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1024 if (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
|| is_64bit_ap(ap
)) {
1025 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE64
, &baseptr_upper
);
1026 if (retval
!= ERROR_OK
)
1030 retval
= dap_run(dap
);
1031 if (retval
!= ERROR_OK
)
1034 if (!is_64bit_ap(ap
))
1036 *dbgbase
= (((target_addr_t
)baseptr_upper
) << 32) | baseptr_lower
;
1041 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
1042 target_addr_t dbgbase
, uint8_t type
, target_addr_t
*addr
, int32_t *idx
)
1044 uint32_t romentry
, entry_offset
= 0, devtype
;
1045 target_addr_t component_base
;
1048 dbgbase
&= 0xFFFFFFFFFFFFF000ull
;
1052 retval
= mem_ap_read_atomic_u32(ap
, dbgbase
|
1053 entry_offset
, &romentry
);
1054 if (retval
!= ERROR_OK
)
1057 component_base
= dbgbase
+ (target_addr_t
)(romentry
& ARM_CS_ROMENTRY_OFFSET_MASK
);
1059 if (romentry
& ARM_CS_ROMENTRY_PRESENT
) {
1061 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ ARM_CS_CIDR1
, &c_cid1
);
1062 if (retval
!= ERROR_OK
) {
1063 LOG_ERROR("Can't read component with base address " TARGET_ADDR_FMT
1064 ", the corresponding core might be turned off", component_base
);
1067 unsigned int class = (c_cid1
& ARM_CS_CIDR1_CLASS_MASK
) >> ARM_CS_CIDR1_CLASS_SHIFT
;
1068 if (class == ARM_CS_CLASS_0X1_ROM_TABLE
) {
1069 retval
= dap_lookup_cs_component(ap
, component_base
,
1071 if (retval
== ERROR_OK
)
1073 if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1077 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ ARM_CS_C9_DEVTYPE
, &devtype
);
1078 if (retval
!= ERROR_OK
)
1080 if ((devtype
& ARM_CS_C9_DEVTYPE_MASK
) == type
) {
1082 *addr
= component_base
;
1089 } while ((romentry
> 0) && (entry_offset
< 0xf00));
1092 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1097 /** Holds registers of a CoreSight component */
1098 struct cs_component_vals
{
1102 uint32_t devtype_memtype
;
1106 * Read the CoreSight registers needed during ROM Table Parsing (RTP).
1108 * @param ap Pointer to AP containing the component.
1109 * @param component_base On MEM-AP access method, base address of the component.
1110 * @param v Pointer to the struct holding the value of registers.
1112 * @return ERROR_OK on success, else a fault code.
1114 static int rtp_read_cs_regs(struct adiv5_ap
*ap
, target_addr_t component_base
,
1115 struct cs_component_vals
*v
)
1117 assert(IS_ALIGNED(component_base
, ARM_CS_ALIGN
));
1120 uint32_t cid0
, cid1
, cid2
, cid3
;
1121 uint32_t pid0
, pid1
, pid2
, pid3
, pid4
;
1122 int retval
= ERROR_OK
;
1124 /* sort by offset to gain speed */
1127 * Registers DEVARCH and DEVTYPE are valid on Class 0x9 devices
1128 * only, but are at offset above 0xf00, so can be read on any device
1129 * without triggering error. Read them for eventual use on Class 0x9.
1131 if (retval
== ERROR_OK
)
1132 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_C9_DEVARCH
, &v
->devarch
);
1134 /* Same address as ARM_CS_C1_MEMTYPE */
1135 if (retval
== ERROR_OK
)
1136 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_C9_DEVTYPE
, &v
->devtype_memtype
);
1138 if (retval
== ERROR_OK
)
1139 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_PIDR4
, &pid4
);
1141 if (retval
== ERROR_OK
)
1142 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_PIDR0
, &pid0
);
1143 if (retval
== ERROR_OK
)
1144 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_PIDR1
, &pid1
);
1145 if (retval
== ERROR_OK
)
1146 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_PIDR2
, &pid2
);
1147 if (retval
== ERROR_OK
)
1148 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_PIDR3
, &pid3
);
1150 if (retval
== ERROR_OK
)
1151 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_CIDR0
, &cid0
);
1152 if (retval
== ERROR_OK
)
1153 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_CIDR1
, &cid1
);
1154 if (retval
== ERROR_OK
)
1155 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_CIDR2
, &cid2
);
1156 if (retval
== ERROR_OK
)
1157 retval
= mem_ap_read_u32(ap
, component_base
+ ARM_CS_CIDR3
, &cid3
);
1159 if (retval
== ERROR_OK
)
1160 retval
= dap_run(ap
->dap
);
1161 if (retval
!= ERROR_OK
) {
1162 LOG_DEBUG("Failed read CoreSight registers");
1166 v
->cid
= (cid3
& 0xff) << 24
1167 | (cid2
& 0xff) << 16
1168 | (cid1
& 0xff) << 8
1170 v
->pid
= (uint64_t)(pid4
& 0xff) << 32
1171 | (pid3
& 0xff) << 24
1172 | (pid2
& 0xff) << 16
1173 | (pid1
& 0xff) << 8
1179 /* Part number interpretations are from Cortex
1180 * core specs, the CoreSight components TRM
1181 * (ARM DDI 0314H), CoreSight System Design
1182 * Guide (ARM DGI 0012D) and ETM specs; also
1183 * from chip observation (e.g. TI SDTI).
1186 static const struct dap_part_nums
{
1187 uint16_t designer_id
;
1191 } dap_part_nums
[] = {
1192 { ARM_ID
, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1193 { ARM_ID
, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1194 { ARM_ID
, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1195 { ARM_ID
, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1196 { ARM_ID
, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1197 { ARM_ID
, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1198 { ARM_ID
, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1199 { ARM_ID
, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1200 { ARM_ID
, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1201 { ARM_ID
, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1202 { ARM_ID
, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
1203 { ARM_ID
, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1204 { ARM_ID
, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1205 { ARM_ID
, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1206 { ARM_ID
, 0x492, "Cortex-R52 GICD", "(Distributor)", },
1207 { ARM_ID
, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
1208 { ARM_ID
, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1209 { ARM_ID
, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1210 { ARM_ID
, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1211 { ARM_ID
, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1212 { ARM_ID
, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1213 { ARM_ID
, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1214 { ARM_ID
, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1215 { ARM_ID
, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1216 { ARM_ID
, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
1217 { ARM_ID
, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1218 { ARM_ID
, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1219 { ARM_ID
, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1220 { ARM_ID
, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1221 { ARM_ID
, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1222 { ARM_ID
, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1223 { ARM_ID
, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
1224 { ARM_ID
, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1225 { ARM_ID
, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1226 { ARM_ID
, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1227 { ARM_ID
, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1228 { ARM_ID
, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1229 { ARM_ID
, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1230 { ARM_ID
, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1231 { ARM_ID
, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1232 { ARM_ID
, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1233 { ARM_ID
, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1234 { ARM_ID
, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1235 { ARM_ID
, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1236 { ARM_ID
, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1237 { ARM_ID
, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1238 { ARM_ID
, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1239 { ARM_ID
, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1240 { ARM_ID
, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1241 { ARM_ID
, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1242 { ARM_ID
, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1243 { ARM_ID
, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1244 { ARM_ID
, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1245 { ARM_ID
, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1246 { ARM_ID
, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1247 { ARM_ID
, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1248 { ARM_ID
, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1249 { ARM_ID
, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1250 { ARM_ID
, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1251 { ARM_ID
, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1252 { ARM_ID
, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1253 { ARM_ID
, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1254 { ARM_ID
, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1255 { ARM_ID
, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1256 { ARM_ID
, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1257 { ARM_ID
, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1258 { ARM_ID
, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1259 { ARM_ID
, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1260 { ARM_ID
, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1261 { ARM_ID
, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1262 { ARM_ID
, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1263 { ARM_ID
, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1264 { ARM_ID
, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1265 { ARM_ID
, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1266 { ARM_ID
, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1267 { ARM_ID
, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1268 { ARM_ID
, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
1269 { ARM_ID
, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
1270 { ARM_ID
, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
1271 { ARM_ID
, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
1272 { ARM_ID
, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
1273 { ARM_ID
, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
1274 { ARM_ID
, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
1275 { ARM_ID
, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
1276 { ARM_ID
, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
1277 { ARM_ID
, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
1278 { ARM_ID
, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
1279 { ARM_ID
, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
1280 { ARM_ID
, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
1281 { ARM_ID
, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1282 { ARM_ID
, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1283 { ARM_ID
, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1284 { ARM_ID
, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1285 { ARM_ID
, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1286 { ARM_ID
, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1287 { ARM_ID
, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1288 { ARM_ID
, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1289 { ARM_ID
, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1290 { ARM_ID
, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1291 { ARM_ID
, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1292 { ARM_ID
, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1293 { ARM_ID
, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1294 { ARM_ID
, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
1295 { ARM_ID
, 0xd0c, "Neoverse N1", "(Debug Unit)", },
1296 { ARM_ID
, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
1297 { ARM_ID
, 0xd49, "Neoverse N2", "(Debug Unit)", },
1298 { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1299 { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1300 { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
1301 { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1302 { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1303 { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1304 { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1305 { 0x065, 0x000, "SHARC+/Blackfin+", "", },
1306 { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1307 { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
1308 { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
1309 { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
1310 { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
1311 { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1312 { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1313 { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1314 { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
1315 { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1318 static const struct dap_part_nums
*pidr_to_part_num(unsigned int designer_id
, unsigned int part_num
)
1320 static const struct dap_part_nums unknown
= {
1321 .type
= "Unrecognized",
1325 for (unsigned int i
= 0; i
< ARRAY_SIZE(dap_part_nums
); i
++)
1326 if (dap_part_nums
[i
].designer_id
== designer_id
&& dap_part_nums
[i
].part_num
== part_num
)
1327 return &dap_part_nums
[i
];
1332 static int dap_devtype_display(struct command_invocation
*cmd
, uint32_t devtype
)
1334 const char *major
= "Reserved", *subtype
= "Reserved";
1335 const unsigned int minor
= (devtype
& ARM_CS_C9_DEVTYPE_SUB_MASK
) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT
;
1336 const unsigned int devtype_major
= (devtype
& ARM_CS_C9_DEVTYPE_MAJOR_MASK
) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT
;
1337 switch (devtype_major
) {
1339 major
= "Miscellaneous";
1345 subtype
= "Validation component";
1350 major
= "Trace Sink";
1367 major
= "Trace Link";
1373 subtype
= "Funnel, router";
1379 subtype
= "FIFO, buffer";
1384 major
= "Trace Source";
1390 subtype
= "Processor";
1396 subtype
= "Engine/Coprocessor";
1402 subtype
= "Software";
1407 major
= "Debug Control";
1413 subtype
= "Trigger Matrix";
1416 subtype
= "Debug Auth";
1419 subtype
= "Power Requestor";
1424 major
= "Debug Logic";
1430 subtype
= "Processor";
1436 subtype
= "Engine/Coprocessor";
1447 major
= "Performance Monitor";
1453 subtype
= "Processor";
1459 subtype
= "Engine/Coprocessor";
1470 command_print(cmd
, "\t\tType is 0x%02x, %s, %s",
1471 devtype
& ARM_CS_C9_DEVTYPE_MASK
,
1476 static int rtp_cs_component(struct command_invocation
*cmd
,
1477 struct adiv5_ap
*ap
, target_addr_t dbgbase
, int depth
);
1479 static int rtp_rom_loop(struct command_invocation
*cmd
,
1480 struct adiv5_ap
*ap
, target_addr_t base_address
, int depth
,
1481 unsigned int max_entries
)
1483 assert(IS_ALIGNED(base_address
, ARM_CS_ALIGN
));
1488 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
1490 unsigned int offset
= 0;
1491 while (max_entries
--) {
1493 unsigned int saved_offset
= offset
;
1495 int retval
= mem_ap_read_atomic_u32(ap
, base_address
+ offset
, &romentry
);
1497 if (retval
!= ERROR_OK
) {
1498 LOG_DEBUG("Failed read ROM table entry");
1499 command_print(cmd
, "\t%sROMTABLE[0x%x] Read error", tabs
, saved_offset
);
1500 command_print(cmd
, "\t\tUnable to continue");
1501 command_print(cmd
, "\t%s\tStop parsing of ROM table", tabs
);
1505 command_print(cmd
, "\t%sROMTABLE[0x%x] = 0x%08" PRIx32
,
1506 tabs
, saved_offset
, romentry
);
1508 if (romentry
== 0) {
1509 command_print(cmd
, "\t%s\tEnd of ROM table", tabs
);
1513 if (!(romentry
& ARM_CS_ROMENTRY_PRESENT
)) {
1514 command_print(cmd
, "\t\tComponent not present");
1518 /* Recurse. "romentry" is signed */
1519 target_addr_t component_base
= base_address
+ (int32_t)(romentry
& ARM_CS_ROMENTRY_OFFSET_MASK
);
1520 retval
= rtp_cs_component(cmd
, ap
, component_base
, depth
+ 1);
1521 if (retval
!= ERROR_OK
)
1528 static int rtp_cs_component(struct command_invocation
*cmd
,
1529 struct adiv5_ap
*ap
, target_addr_t base_address
, int depth
)
1531 struct cs_component_vals v
;
1535 assert(IS_ALIGNED(base_address
, ARM_CS_ALIGN
));
1538 command_print(cmd
, "\tTables too deep");
1543 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
1545 command_print(cmd
, "\t\tComponent base address " TARGET_ADDR_FMT
, base_address
);
1547 retval
= rtp_read_cs_regs(ap
, base_address
, &v
);
1548 if (retval
!= ERROR_OK
) {
1549 command_print(cmd
, "\t\tCan't read component, the corresponding core might be turned off");
1550 return ERROR_OK
; /* Don't abort recursion */
1553 if (!is_valid_arm_cs_cidr(v
.cid
)) {
1554 command_print(cmd
, "\t\tInvalid CID 0x%08" PRIx32
, v
.cid
);
1555 return ERROR_OK
; /* Don't abort recursion */
1558 /* component may take multiple 4K pages */
1559 uint32_t size
= ARM_CS_PIDR_SIZE(v
.pid
);
1561 command_print(cmd
, "\t\tStart address " TARGET_ADDR_FMT
, base_address
- 0x1000 * size
);
1563 command_print(cmd
, "\t\tPeripheral ID 0x%010" PRIx64
, v
.pid
);
1565 const unsigned int class = ARM_CS_CIDR_CLASS(v
.cid
);
1566 const unsigned int part_num
= ARM_CS_PIDR_PART(v
.pid
);
1567 unsigned int designer_id
= ARM_CS_PIDR_DESIGNER(v
.pid
);
1569 if (v
.pid
& ARM_CS_PIDR_JEDEC
) {
1571 command_print(cmd
, "\t\tDesigner is 0x%03x, %s",
1572 designer_id
, jep106_manufacturer(designer_id
));
1574 /* Legacy ASCII ID, clear invalid bits */
1575 designer_id
&= 0x7f;
1576 command_print(cmd
, "\t\tDesigner ASCII code 0x%02x, %s",
1577 designer_id
, designer_id
== 0x41 ? "ARM" : "<unknown>");
1580 const struct dap_part_nums
*partnum
= pidr_to_part_num(designer_id
, part_num
);
1581 command_print(cmd
, "\t\tPart is 0x%03x, %s %s", part_num
, partnum
->type
, partnum
->full
);
1582 command_print(cmd
, "\t\tComponent class is 0x%x, %s", class, class_description
[class]);
1584 if (class == ARM_CS_CLASS_0X1_ROM_TABLE
) {
1585 if (v
.devtype_memtype
& ARM_CS_C1_MEMTYPE_SYSMEM_MASK
)
1586 command_print(cmd
, "\t\tMEMTYPE system memory present on bus");
1588 command_print(cmd
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1590 return rtp_rom_loop(cmd
, ap
, base_address
, depth
, 960);
1593 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT
) {
1594 retval
= dap_devtype_display(cmd
, v
.devtype_memtype
);
1595 if (retval
!= ERROR_OK
)
1598 /* REVISIT also show ARM_CS_C9_DEVID */
1600 if ((v
.devarch
& ARM_CS_C9_DEVARCH_PRESENT
) == 0)
1603 unsigned int architect_id
= (v
.devarch
& ARM_CS_C9_DEVARCH_ARCHITECT_MASK
) >> ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT
;
1604 unsigned int revision
= (v
.devarch
& ARM_CS_C9_DEVARCH_REVISION_MASK
) >> ARM_CS_C9_DEVARCH_REVISION_SHIFT
;
1605 command_print(cmd
, "\t\tDev Arch is 0x%08" PRIx32
", %s \"%s\" rev.%u", v
.devarch
,
1606 jep106_manufacturer(architect_id
), class0x9_devarch_description(v
.devarch
),
1608 /* quit if not ROM table */
1609 if ((v
.devarch
& DEVARCH_ID_MASK
) != DEVARCH_ROM_C_0X9
)
1612 return rtp_rom_loop(cmd
, ap
, base_address
, depth
, 512);
1615 /* Class other than 0x1 and 0x9 */
1619 int dap_info_command(struct command_invocation
*cmd
,
1620 struct adiv5_ap
*ap
)
1624 target_addr_t dbgbase
;
1625 target_addr_t dbgaddr
;
1627 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1628 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
1629 if (retval
!= ERROR_OK
)
1632 command_print(cmd
, "AP ID register 0x%8.8" PRIx32
, apid
);
1634 command_print(cmd
, "No AP found at this ap 0x%x", ap
->ap_num
);
1638 command_print(cmd
, "\tType is %s", ap_type_to_description(apid
& AP_TYPE_MASK
));
1640 /* NOTE: a MEM-AP may have a single CoreSight component that's
1641 * not a ROM table ... or have no such components at all.
1643 const unsigned int class = (apid
& AP_REG_IDR_CLASS_MASK
) >> AP_REG_IDR_CLASS_SHIFT
;
1645 if (class == AP_REG_IDR_CLASS_MEM_AP
) {
1646 if (is_64bit_ap(ap
))
1647 dbgaddr
= 0xFFFFFFFFFFFFFFFFull
;
1649 dbgaddr
= 0xFFFFFFFFul
;
1651 command_print(cmd
, "MEM-AP BASE " TARGET_ADDR_FMT
, dbgbase
);
1653 if (dbgbase
== dbgaddr
|| (dbgbase
& 0x3) == 0x2) {
1654 command_print(cmd
, "\tNo ROM table present");
1657 command_print(cmd
, "\tValid ROM table present");
1659 command_print(cmd
, "\tROM table in legacy format");
1661 rtp_cs_component(cmd
, ap
, dbgbase
& 0xFFFFFFFFFFFFF000ull
, 0);
1668 enum adiv5_cfg_param
{
1672 CFG_CTIBASE
, /* DEPRECATED */
1675 static const struct jim_nvp nvp_config_opts
[] = {
1676 { .name
= "-dap", .value
= CFG_DAP
},
1677 { .name
= "-ap-num", .value
= CFG_AP_NUM
},
1678 { .name
= "-baseaddr", .value
= CFG_BASEADDR
},
1679 { .name
= "-ctibase", .value
= CFG_CTIBASE
}, /* DEPRECATED */
1680 { .name
= NULL
, .value
= -1 }
1683 static int adiv5_jim_spot_configure(struct jim_getopt_info
*goi
,
1684 struct adiv5_dap
**dap_p
, int *ap_num_p
, uint32_t *base_p
)
1689 Jim_SetEmptyResult(goi
->interp
);
1692 int e
= jim_nvp_name2value_obj(goi
->interp
, nvp_config_opts
,
1695 return JIM_CONTINUE
;
1697 /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
1698 if (!base_p
&& (n
->value
== CFG_BASEADDR
|| n
->value
== CFG_CTIBASE
))
1699 return JIM_CONTINUE
;
1701 e
= jim_getopt_obj(goi
, NULL
);
1707 if (goi
->isconfigure
) {
1709 struct adiv5_dap
*dap
;
1710 e
= jim_getopt_obj(goi
, &o_t
);
1713 dap
= dap_instance_by_jim_obj(goi
->interp
, o_t
);
1715 Jim_SetResultString(goi
->interp
, "DAP name invalid!", -1);
1718 if (*dap_p
&& *dap_p
!= dap
) {
1719 Jim_SetResultString(goi
->interp
,
1720 "DAP assignment cannot be changed!", -1);
1728 Jim_SetResultString(goi
->interp
, "DAP not configured", -1);
1731 Jim_SetResultString(goi
->interp
, adiv5_dap_name(*dap_p
), -1);
1736 if (goi
->isconfigure
) {
1738 e
= jim_getopt_wide(goi
, &ap_num
);
1741 if (ap_num
< 0 || ap_num
> DP_APSEL_MAX
) {
1742 Jim_SetResultString(goi
->interp
, "Invalid AP number!", -1);
1749 if (*ap_num_p
== DP_APSEL_INVALID
) {
1750 Jim_SetResultString(goi
->interp
, "AP number not configured", -1);
1753 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, *ap_num_p
));
1758 LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
1761 if (goi
->isconfigure
) {
1763 e
= jim_getopt_wide(goi
, &base
);
1766 *base_p
= (uint32_t)base
;
1770 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, *base_p
));
1778 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
, "NO PARAMS");
1782 int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
)
1784 struct adiv5_private_config
*pc
;
1787 pc
= (struct adiv5_private_config
*)target
->private_config
;
1789 pc
= calloc(1, sizeof(struct adiv5_private_config
));
1790 pc
->ap_num
= DP_APSEL_INVALID
;
1791 target
->private_config
= pc
;
1794 target
->has_dap
= true;
1796 e
= adiv5_jim_spot_configure(goi
, &pc
->dap
, &pc
->ap_num
, NULL
);
1800 if (pc
->dap
&& !target
->dap_configured
) {
1801 if (target
->tap_configured
) {
1803 Jim_SetResultString(goi
->interp
,
1804 "-chain-position and -dap configparams are mutually exclusive!", -1);
1807 target
->tap
= pc
->dap
->tap
;
1808 target
->dap_configured
= true;
1814 int adiv5_verify_config(struct adiv5_private_config
*pc
)
1825 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
1826 struct jim_getopt_info
*goi
)
1828 return adiv5_jim_spot_configure(goi
, &cfg
->dap
, &cfg
->ap_num
, &cfg
->base
);
1831 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
)
1834 p
->ap_num
= DP_APSEL_INVALID
;
1839 COMMAND_HANDLER(handle_dap_info_command
)
1841 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1849 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1850 if (apsel
> DP_APSEL_MAX
) {
1851 command_print(CMD
, "Invalid AP number");
1852 return ERROR_COMMAND_ARGUMENT_INVALID
;
1856 return ERROR_COMMAND_SYNTAX_ERROR
;
1859 return dap_info_command(CMD
, &dap
->ap
[apsel
]);
1862 COMMAND_HANDLER(dap_baseaddr_command
)
1864 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1865 uint32_t apsel
, baseaddr_lower
, baseaddr_upper
;
1866 struct adiv5_ap
*ap
;
1867 target_addr_t baseaddr
;
1877 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1878 /* AP address is in bits 31:24 of DP_SELECT */
1879 if (apsel
> DP_APSEL_MAX
) {
1880 command_print(CMD
, "Invalid AP number");
1881 return ERROR_COMMAND_ARGUMENT_INVALID
;
1885 return ERROR_COMMAND_SYNTAX_ERROR
;
1888 /* NOTE: assumes we're talking to a MEM-AP, which
1889 * has a base address. There are other kinds of AP,
1890 * though they're not common for now. This should
1891 * use the ID register to verify it's a MEM-AP.
1894 ap
= dap_ap(dap
, apsel
);
1895 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE
, &baseaddr_lower
);
1897 if (retval
== ERROR_OK
&& ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
)
1898 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG
, &ap
->cfg_reg
);
1900 if (retval
== ERROR_OK
&& (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
|| is_64bit_ap(ap
))) {
1901 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1902 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE64
, &baseaddr_upper
);
1905 if (retval
== ERROR_OK
)
1906 retval
= dap_run(dap
);
1907 if (retval
!= ERROR_OK
)
1910 if (is_64bit_ap(ap
)) {
1911 baseaddr
= (((target_addr_t
)baseaddr_upper
) << 32) | baseaddr_lower
;
1912 command_print(CMD
, "0x%016" PRIx64
, baseaddr
);
1914 command_print(CMD
, "0x%08" PRIx32
, baseaddr_lower
);
1919 COMMAND_HANDLER(dap_memaccess_command
)
1921 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1922 uint32_t memaccess_tck
;
1926 memaccess_tck
= dap
->ap
[dap
->apsel
].memaccess_tck
;
1929 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1932 return ERROR_COMMAND_SYNTAX_ERROR
;
1934 dap
->ap
[dap
->apsel
].memaccess_tck
= memaccess_tck
;
1936 command_print(CMD
, "memory bus access delay set to %" PRIu32
" tck",
1937 dap
->ap
[dap
->apsel
].memaccess_tck
);
1942 COMMAND_HANDLER(dap_apsel_command
)
1944 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1949 command_print(CMD
, "%" PRIu32
, dap
->apsel
);
1952 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1953 /* AP address is in bits 31:24 of DP_SELECT */
1954 if (apsel
> DP_APSEL_MAX
) {
1955 command_print(CMD
, "Invalid AP number");
1956 return ERROR_COMMAND_ARGUMENT_INVALID
;
1960 return ERROR_COMMAND_SYNTAX_ERROR
;
1967 COMMAND_HANDLER(dap_apcsw_command
)
1969 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1970 uint32_t apcsw
= dap
->ap
[dap
->apsel
].csw_default
;
1971 uint32_t csw_val
, csw_mask
;
1975 command_print(CMD
, "ap %" PRIu32
" selected, csw 0x%8.8" PRIx32
,
1979 if (strcmp(CMD_ARGV
[0], "default") == 0)
1980 csw_val
= CSW_AHB_DEFAULT
;
1982 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
1984 if (csw_val
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
1985 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1986 return ERROR_COMMAND_ARGUMENT_INVALID
;
1991 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
1992 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], csw_mask
);
1993 if (csw_mask
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
1994 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1995 return ERROR_COMMAND_ARGUMENT_INVALID
;
1997 apcsw
= (apcsw
& ~csw_mask
) | (csw_val
& csw_mask
);
2000 return ERROR_COMMAND_SYNTAX_ERROR
;
2002 dap
->ap
[dap
->apsel
].csw_default
= apcsw
;
2009 COMMAND_HANDLER(dap_apid_command
)
2011 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2012 uint32_t apsel
, apid
;
2020 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
2021 /* AP address is in bits 31:24 of DP_SELECT */
2022 if (apsel
> DP_APSEL_MAX
) {
2023 command_print(CMD
, "Invalid AP number");
2024 return ERROR_COMMAND_ARGUMENT_INVALID
;
2028 return ERROR_COMMAND_SYNTAX_ERROR
;
2031 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), AP_REG_IDR
, &apid
);
2032 if (retval
!= ERROR_OK
)
2034 retval
= dap_run(dap
);
2035 if (retval
!= ERROR_OK
)
2038 command_print(CMD
, "0x%8.8" PRIx32
, apid
);
2043 COMMAND_HANDLER(dap_apreg_command
)
2045 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2046 uint32_t apsel
, reg
, value
;
2047 struct adiv5_ap
*ap
;
2050 if (CMD_ARGC
< 2 || CMD_ARGC
> 3)
2051 return ERROR_COMMAND_SYNTAX_ERROR
;
2053 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
2054 /* AP address is in bits 31:24 of DP_SELECT */
2055 if (apsel
> DP_APSEL_MAX
) {
2056 command_print(CMD
, "Invalid AP number");
2057 return ERROR_COMMAND_ARGUMENT_INVALID
;
2060 ap
= dap_ap(dap
, apsel
);
2062 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg
);
2063 if (reg
>= 256 || (reg
& 3)) {
2064 command_print(CMD
, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2065 return ERROR_COMMAND_ARGUMENT_INVALID
;
2068 if (CMD_ARGC
== 3) {
2069 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
2071 case MEM_AP_REG_CSW
:
2072 ap
->csw_value
= 0; /* invalid, in case write fails */
2073 retval
= dap_queue_ap_write(ap
, reg
, value
);
2074 if (retval
== ERROR_OK
)
2075 ap
->csw_value
= value
;
2077 case MEM_AP_REG_TAR
:
2078 retval
= dap_queue_ap_write(ap
, reg
, value
);
2079 if (retval
== ERROR_OK
)
2080 ap
->tar_value
= (ap
->tar_value
& ~0xFFFFFFFFull
) | value
;
2082 /* To track independent writes to TAR and TAR64, two tar_valid flags */
2083 /* should be used. To keep it simple, tar_valid is only invalidated on a */
2084 /* write fail. This approach causes a later re-write of the TAR and TAR64 */
2085 /* if tar_valid is false. */
2086 ap
->tar_valid
= false;
2089 case MEM_AP_REG_TAR64
:
2090 retval
= dap_queue_ap_write(ap
, reg
, value
);
2091 if (retval
== ERROR_OK
)
2092 ap
->tar_value
= (ap
->tar_value
& 0xFFFFFFFFull
) | (((target_addr_t
)value
) << 32);
2094 /* See above comment for the MEM_AP_REG_TAR failed write case */
2095 ap
->tar_valid
= false;
2099 retval
= dap_queue_ap_write(ap
, reg
, value
);
2103 retval
= dap_queue_ap_read(ap
, reg
, &value
);
2105 if (retval
== ERROR_OK
)
2106 retval
= dap_run(dap
);
2108 if (retval
!= ERROR_OK
)
2112 command_print(CMD
, "0x%08" PRIx32
, value
);
2117 COMMAND_HANDLER(dap_dpreg_command
)
2119 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2120 uint32_t reg
, value
;
2123 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2124 return ERROR_COMMAND_SYNTAX_ERROR
;
2126 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg
);
2127 if (reg
>= 256 || (reg
& 3)) {
2128 command_print(CMD
, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2129 return ERROR_COMMAND_ARGUMENT_INVALID
;
2132 if (CMD_ARGC
== 2) {
2133 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2134 retval
= dap_queue_dp_write(dap
, reg
, value
);
2136 retval
= dap_queue_dp_read(dap
, reg
, &value
);
2138 if (retval
== ERROR_OK
)
2139 retval
= dap_run(dap
);
2141 if (retval
!= ERROR_OK
)
2145 command_print(CMD
, "0x%08" PRIx32
, value
);
2150 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
2152 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2153 return CALL_COMMAND_HANDLER(handle_command_parse_bool
, &dap
->ti_be_32_quirks
,
2154 "TI BE-32 quirks mode");
2157 const struct command_registration dap_instance_commands
[] = {
2160 .handler
= handle_dap_info_command
,
2161 .mode
= COMMAND_EXEC
,
2162 .help
= "display ROM table for MEM-AP "
2163 "(default currently selected AP)",
2164 .usage
= "[ap_num]",
2168 .handler
= dap_apsel_command
,
2169 .mode
= COMMAND_ANY
,
2170 .help
= "Set the currently selected AP (default 0) "
2171 "and display the result",
2172 .usage
= "[ap_num]",
2176 .handler
= dap_apcsw_command
,
2177 .mode
= COMMAND_ANY
,
2178 .help
= "Set CSW default bits",
2179 .usage
= "[value [mask]]",
2184 .handler
= dap_apid_command
,
2185 .mode
= COMMAND_EXEC
,
2186 .help
= "return ID register from AP "
2187 "(default currently selected AP)",
2188 .usage
= "[ap_num]",
2192 .handler
= dap_apreg_command
,
2193 .mode
= COMMAND_EXEC
,
2194 .help
= "read/write a register from AP "
2195 "(reg is byte address of a word register, like 0 4 8...)",
2196 .usage
= "ap_num reg [value]",
2200 .handler
= dap_dpreg_command
,
2201 .mode
= COMMAND_EXEC
,
2202 .help
= "read/write a register from DP "
2203 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
2204 .usage
= "reg [value]",
2208 .handler
= dap_baseaddr_command
,
2209 .mode
= COMMAND_EXEC
,
2210 .help
= "return debug base address from MEM-AP "
2211 "(default currently selected AP)",
2212 .usage
= "[ap_num]",
2215 .name
= "memaccess",
2216 .handler
= dap_memaccess_command
,
2217 .mode
= COMMAND_EXEC
,
2218 .help
= "set/get number of extra tck for MEM-AP memory "
2219 "bus access [0-255]",
2220 .usage
= "[cycles]",
2223 .name
= "ti_be_32_quirks",
2224 .handler
= dap_ti_be_32_quirks_command
,
2225 .mode
= COMMAND_CONFIG
,
2226 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
2227 .usage
= "[enable]",
2229 COMMAND_REGISTRATION_DONE
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