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[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * Copyright (C) 2019-2021, Ampere Computing LLC *
17 * *
18 * This program is free software; you can redistribute it and/or modify *
19 * it under the terms of the GNU General Public License as published by *
20 * the Free Software Foundation; either version 2 of the License, or *
21 * (at your option) any later version. *
22 * *
23 * This program is distributed in the hope that it will be useful, *
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
26 * GNU General Public License for more details. *
27 * *
28 * You should have received a copy of the GNU General Public License *
29 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focuses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction pipelining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include "arm_coresight.h"
79 #include "jtag/swd.h"
80 #include "transport/transport.h"
81 #include <helper/align.h>
82 #include <helper/jep106.h>
83 #include <helper/time_support.h>
84 #include <helper/list.h>
85 #include <helper/jim-nvp.h>
86
87 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
88
89 /*
90 uint32_t tar_block_size(uint32_t address)
91 Return the largest block starting at address that does not cross a tar block size alignment boundary
92 */
93 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
94 {
95 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
96 }
97
98 /***************************************************************************
99 * *
100 * DP and MEM-AP register access through APACC and DPACC *
101 * *
102 ***************************************************************************/
103
104 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
105 {
106 csw |= ap->csw_default;
107
108 if (csw != ap->csw_value) {
109 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
110 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
111 if (retval != ERROR_OK) {
112 ap->csw_value = 0;
113 return retval;
114 }
115 ap->csw_value = csw;
116 }
117 return ERROR_OK;
118 }
119
120 static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
121 {
122 if (!ap->tar_valid || tar != ap->tar_value) {
123 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
124 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, (uint32_t)(tar & 0xffffffffUL));
125 if (retval == ERROR_OK && is_64bit_ap(ap)) {
126 /* See if bits 63:32 of tar is different from last setting */
127 if ((ap->tar_value >> 32) != (tar >> 32))
128 retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64, (uint32_t)(tar >> 32));
129 }
130 if (retval != ERROR_OK) {
131 ap->tar_valid = false;
132 return retval;
133 }
134 ap->tar_value = tar;
135 ap->tar_valid = true;
136 }
137 return ERROR_OK;
138 }
139
140 static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
141 {
142 uint32_t lower;
143 uint32_t upper = 0;
144
145 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, &lower);
146 if (retval == ERROR_OK && is_64bit_ap(ap))
147 retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64, &upper);
148
149 if (retval != ERROR_OK) {
150 ap->tar_valid = false;
151 return retval;
152 }
153
154 retval = dap_run(ap->dap);
155 if (retval != ERROR_OK) {
156 ap->tar_valid = false;
157 return retval;
158 }
159
160 *tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower;
161
162 ap->tar_value = *tar;
163 ap->tar_valid = true;
164 return ERROR_OK;
165 }
166
167 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
168 {
169 switch (ap->csw_value & CSW_ADDRINC_MASK) {
170 case CSW_ADDRINC_SINGLE:
171 switch (ap->csw_value & CSW_SIZE_MASK) {
172 case CSW_8BIT:
173 return 1;
174 case CSW_16BIT:
175 return 2;
176 case CSW_32BIT:
177 return 4;
178 default:
179 return 0;
180 }
181 case CSW_ADDRINC_PACKED:
182 return 4;
183 }
184 return 0;
185 }
186
187 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
188 */
189 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
190 {
191 if (!ap->tar_valid)
192 return;
193
194 uint32_t inc = mem_ap_get_tar_increment(ap);
195 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
196 ap->tar_valid = false;
197 else
198 ap->tar_value += inc;
199 }
200
201 /**
202 * Queue transactions setting up transfer parameters for the
203 * currently selected MEM-AP.
204 *
205 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
206 * initiate data reads or writes using memory or peripheral addresses.
207 * If the CSW is configured for it, the TAR may be automatically
208 * incremented after each transfer.
209 *
210 * @param ap The MEM-AP.
211 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
212 * matches the cached value, the register is not changed.
213 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
214 * matches the cached address, the register is not changed.
215 *
216 * @return ERROR_OK if the transaction was properly queued, else a fault code.
217 */
218 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
219 {
220 int retval;
221 retval = mem_ap_setup_csw(ap, csw);
222 if (retval != ERROR_OK)
223 return retval;
224 retval = mem_ap_setup_tar(ap, tar);
225 if (retval != ERROR_OK)
226 return retval;
227 return ERROR_OK;
228 }
229
230 /**
231 * Asynchronous (queued) read of a word from memory or a system register.
232 *
233 * @param ap The MEM-AP to access.
234 * @param address Address of the 32-bit word to read; it must be
235 * readable by the currently selected MEM-AP.
236 * @param value points to where the word will be stored when the
237 * transaction queue is flushed (assuming no errors).
238 *
239 * @return ERROR_OK for success. Otherwise a fault code.
240 */
241 int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
242 uint32_t *value)
243 {
244 int retval;
245
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when reading several consecutive addresses.
248 */
249 retval = mem_ap_setup_transfer(ap,
250 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
251 address & 0xFFFFFFFFFFFFFFF0ull);
252 if (retval != ERROR_OK)
253 return retval;
254
255 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
256 }
257
258 /**
259 * Synchronous read of a word from memory or a system register.
260 * As a side effect, this flushes any queued transactions.
261 *
262 * @param ap The MEM-AP to access.
263 * @param address Address of the 32-bit word to read; it must be
264 * readable by the currently selected MEM-AP.
265 * @param value points to where the result will be stored.
266 *
267 * @return ERROR_OK for success; *value holds the result.
268 * Otherwise a fault code.
269 */
270 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
271 uint32_t *value)
272 {
273 int retval;
274
275 retval = mem_ap_read_u32(ap, address, value);
276 if (retval != ERROR_OK)
277 return retval;
278
279 return dap_run(ap->dap);
280 }
281
282 /**
283 * Asynchronous (queued) write of a word to memory or a system register.
284 *
285 * @param ap The MEM-AP to access.
286 * @param address Address to be written; it must be writable by
287 * the currently selected MEM-AP.
288 * @param value Word that will be written to the address when transaction
289 * queue is flushed (assuming no errors).
290 *
291 * @return ERROR_OK for success. Otherwise a fault code.
292 */
293 int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
294 uint32_t value)
295 {
296 int retval;
297
298 /* Use banked addressing (REG_BDx) to avoid some link traffic
299 * (updating TAR) when writing several consecutive addresses.
300 */
301 retval = mem_ap_setup_transfer(ap,
302 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
303 address & 0xFFFFFFFFFFFFFFF0ull);
304 if (retval != ERROR_OK)
305 return retval;
306
307 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
308 value);
309 }
310
311 /**
312 * Synchronous write of a word to memory or a system register.
313 * As a side effect, this flushes any queued transactions.
314 *
315 * @param ap The MEM-AP to access.
316 * @param address Address to be written; it must be writable by
317 * the currently selected MEM-AP.
318 * @param value Word that will be written.
319 *
320 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
321 */
322 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
323 uint32_t value)
324 {
325 int retval = mem_ap_write_u32(ap, address, value);
326
327 if (retval != ERROR_OK)
328 return retval;
329
330 return dap_run(ap->dap);
331 }
332
333 /**
334 * Synchronous write of a block of memory, using a specific access size.
335 *
336 * @param ap The MEM-AP to access.
337 * @param buffer The data buffer to write. No particular alignment is assumed.
338 * @param size Which access size to use, in bytes. 1, 2 or 4.
339 * @param count The number of writes to do (in size units, not bytes).
340 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
341 * @param addrinc Whether the target address should be increased for each write or not. This
342 * should normally be true, except when writing to e.g. a FIFO.
343 * @return ERROR_OK on success, otherwise an error code.
344 */
345 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
346 target_addr_t address, bool addrinc)
347 {
348 struct adiv5_dap *dap = ap->dap;
349 size_t nbytes = size * count;
350 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
351 uint32_t csw_size;
352 target_addr_t addr_xor;
353 int retval = ERROR_OK;
354
355 /* TI BE-32 Quirks mode:
356 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
357 * size write address bytes written in order
358 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
359 * 2 TAR ^ 2 (val >> 8), (val)
360 * 1 TAR ^ 3 (val)
361 * For example, if you attempt to write a single byte to address 0, the processor
362 * will actually write a byte to address 3.
363 *
364 * To make writes of size < 4 work as expected, we xor a value with the address before
365 * setting the TAP, and we set the TAP after every transfer rather then relying on
366 * address increment. */
367
368 if (size == 4) {
369 csw_size = CSW_32BIT;
370 addr_xor = 0;
371 } else if (size == 2) {
372 csw_size = CSW_16BIT;
373 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
374 } else if (size == 1) {
375 csw_size = CSW_8BIT;
376 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
377 } else {
378 return ERROR_TARGET_UNALIGNED_ACCESS;
379 }
380
381 if (ap->unaligned_access_bad && (address % size != 0))
382 return ERROR_TARGET_UNALIGNED_ACCESS;
383
384 while (nbytes > 0) {
385 uint32_t this_size = size;
386
387 /* Select packed transfer if possible */
388 if (addrinc && ap->packed_transfers && nbytes >= 4
389 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
390 this_size = 4;
391 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
392 } else {
393 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
394 }
395
396 if (retval != ERROR_OK)
397 break;
398
399 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
400 if (retval != ERROR_OK)
401 return retval;
402
403 /* How many source bytes each transfer will consume, and their location in the DRW,
404 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
405 uint32_t outvalue = 0;
406 uint32_t drw_byte_idx = address;
407 if (dap->ti_be_32_quirks) {
408 switch (this_size) {
409 case 4:
410 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
411 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
412 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
413 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
414 break;
415 case 2:
416 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
417 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
418 break;
419 case 1:
420 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
421 break;
422 }
423 } else {
424 switch (this_size) {
425 case 4:
426 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
427 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
428 /* fallthrough */
429 case 2:
430 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
431 /* fallthrough */
432 case 1:
433 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
434 }
435 }
436
437 nbytes -= this_size;
438
439 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
440 if (retval != ERROR_OK)
441 break;
442
443 mem_ap_update_tar_cache(ap);
444 if (addrinc)
445 address += this_size;
446 }
447
448 /* REVISIT: Might want to have a queued version of this function that does not run. */
449 if (retval == ERROR_OK)
450 retval = dap_run(dap);
451
452 if (retval != ERROR_OK) {
453 target_addr_t tar;
454 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
455 LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
456 else
457 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
458 }
459
460 return retval;
461 }
462
463 /**
464 * Synchronous read of a block of memory, using a specific access size.
465 *
466 * @param ap The MEM-AP to access.
467 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
468 * @param size Which access size to use, in bytes. 1, 2 or 4.
469 * @param count The number of reads to do (in size units, not bytes).
470 * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
471 * @param addrinc Whether the target address should be increased after each read or not. This
472 * should normally be true, except when reading from e.g. a FIFO.
473 * @return ERROR_OK on success, otherwise an error code.
474 */
475 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
476 target_addr_t adr, bool addrinc)
477 {
478 struct adiv5_dap *dap = ap->dap;
479 size_t nbytes = size * count;
480 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
481 uint32_t csw_size;
482 target_addr_t address = adr;
483 int retval = ERROR_OK;
484
485 /* TI BE-32 Quirks mode:
486 * Reads on big-endian TMS570 behave strangely differently than writes.
487 * They read from the physical address requested, but with DRW byte-reversed.
488 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
489 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
490 * so avoid them. */
491
492 if (size == 4)
493 csw_size = CSW_32BIT;
494 else if (size == 2)
495 csw_size = CSW_16BIT;
496 else if (size == 1)
497 csw_size = CSW_8BIT;
498 else
499 return ERROR_TARGET_UNALIGNED_ACCESS;
500
501 if (ap->unaligned_access_bad && (adr % size != 0))
502 return ERROR_TARGET_UNALIGNED_ACCESS;
503
504 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
505 * over-allocation if packed transfers are going to be used, but determining the real need at
506 * this point would be messy. */
507 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
508 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
509 uint32_t *read_ptr = read_buf;
510 if (!read_buf) {
511 LOG_ERROR("Failed to allocate read buffer");
512 return ERROR_FAIL;
513 }
514
515 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
516 * useful bytes it contains, and their location in the word, depends on the type of transfer
517 * and alignment. */
518 while (nbytes > 0) {
519 uint32_t this_size = size;
520
521 /* Select packed transfer if possible */
522 if (addrinc && ap->packed_transfers && nbytes >= 4
523 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
524 this_size = 4;
525 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
526 } else {
527 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
528 }
529 if (retval != ERROR_OK)
530 break;
531
532 retval = mem_ap_setup_tar(ap, address);
533 if (retval != ERROR_OK)
534 break;
535
536 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
537 if (retval != ERROR_OK)
538 break;
539
540 nbytes -= this_size;
541 if (addrinc)
542 address += this_size;
543
544 mem_ap_update_tar_cache(ap);
545 }
546
547 if (retval == ERROR_OK)
548 retval = dap_run(dap);
549
550 /* Restore state */
551 address = adr;
552 nbytes = size * count;
553 read_ptr = read_buf;
554
555 /* If something failed, read TAR to find out how much data was successfully read, so we can
556 * at least give the caller what we have. */
557 if (retval != ERROR_OK) {
558 target_addr_t tar;
559 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
560 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
561 LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
562 if (nbytes > tar - address)
563 nbytes = tar - address;
564 } else {
565 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
566 nbytes = 0;
567 }
568 }
569
570 /* Replay loop to populate caller's buffer from the correct word and byte lane */
571 while (nbytes > 0) {
572 uint32_t this_size = size;
573
574 if (addrinc && ap->packed_transfers && nbytes >= 4
575 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
576 this_size = 4;
577 }
578
579 if (dap->ti_be_32_quirks) {
580 switch (this_size) {
581 case 4:
582 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
583 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
584 /* fallthrough */
585 case 2:
586 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
587 /* fallthrough */
588 case 1:
589 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
590 }
591 } else {
592 switch (this_size) {
593 case 4:
594 *buffer++ = *read_ptr >> 8 * (address++ & 3);
595 *buffer++ = *read_ptr >> 8 * (address++ & 3);
596 /* fallthrough */
597 case 2:
598 *buffer++ = *read_ptr >> 8 * (address++ & 3);
599 /* fallthrough */
600 case 1:
601 *buffer++ = *read_ptr >> 8 * (address++ & 3);
602 }
603 }
604
605 read_ptr++;
606 nbytes -= this_size;
607 }
608
609 free(read_buf);
610 return retval;
611 }
612
613 int mem_ap_read_buf(struct adiv5_ap *ap,
614 uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
615 {
616 return mem_ap_read(ap, buffer, size, count, address, true);
617 }
618
619 int mem_ap_write_buf(struct adiv5_ap *ap,
620 const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
621 {
622 return mem_ap_write(ap, buffer, size, count, address, true);
623 }
624
625 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
626 uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
627 {
628 return mem_ap_read(ap, buffer, size, count, address, false);
629 }
630
631 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
632 const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
633 {
634 return mem_ap_write(ap, buffer, size, count, address, false);
635 }
636
637 /*--------------------------------------------------------------------------*/
638
639
640 #define DAP_POWER_DOMAIN_TIMEOUT (10)
641
642 /*--------------------------------------------------------------------------*/
643
644 /**
645 * Invalidate cached DP select and cached TAR and CSW of all APs
646 */
647 void dap_invalidate_cache(struct adiv5_dap *dap)
648 {
649 dap->select = DP_SELECT_INVALID;
650 dap->last_read = NULL;
651
652 int i;
653 for (i = 0; i <= DP_APSEL_MAX; i++) {
654 /* force csw and tar write on the next mem-ap access */
655 dap->ap[i].tar_valid = false;
656 dap->ap[i].csw_value = 0;
657 }
658 }
659
660 /**
661 * Initialize a DAP. This sets up the power domains, prepares the DP
662 * for further use and activates overrun checking.
663 *
664 * @param dap The DAP being initialized.
665 */
666 int dap_dp_init(struct adiv5_dap *dap)
667 {
668 int retval;
669
670 LOG_DEBUG("%s", adiv5_dap_name(dap));
671
672 dap->do_reconnect = false;
673 dap_invalidate_cache(dap);
674
675 /*
676 * Early initialize dap->dp_ctrl_stat.
677 * In jtag mode only, if the following queue run (in dap_dp_poll_register)
678 * fails and sets the sticky error, it will trigger the clearing
679 * of the sticky. Without this initialization system and debug power
680 * would be disabled while clearing the sticky error bit.
681 */
682 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
683
684 /*
685 * This write operation clears the sticky error bit in jtag mode only and
686 * is ignored in swd mode. It also powers-up system and debug domains in
687 * both jtag and swd modes, if not done before.
688 */
689 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
690 if (retval != ERROR_OK)
691 return retval;
692
693 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
694 if (retval != ERROR_OK)
695 return retval;
696
697 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
698 if (retval != ERROR_OK)
699 return retval;
700
701 /* Check that we have debug power domains activated */
702 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
703 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
704 CDBGPWRUPACK, CDBGPWRUPACK,
705 DAP_POWER_DOMAIN_TIMEOUT);
706 if (retval != ERROR_OK)
707 return retval;
708
709 if (!dap->ignore_syspwrupack) {
710 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
711 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
712 CSYSPWRUPACK, CSYSPWRUPACK,
713 DAP_POWER_DOMAIN_TIMEOUT);
714 if (retval != ERROR_OK)
715 return retval;
716 }
717
718 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
719 if (retval != ERROR_OK)
720 return retval;
721
722 /* With debug power on we can activate OVERRUN checking */
723 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
724 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
725 if (retval != ERROR_OK)
726 return retval;
727 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
728 if (retval != ERROR_OK)
729 return retval;
730
731 retval = dap_run(dap);
732 if (retval != ERROR_OK)
733 return retval;
734
735 return retval;
736 }
737
738 /**
739 * Initialize a DAP or do reconnect if DAP is not accessible.
740 *
741 * @param dap The DAP being initialized.
742 */
743 int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
744 {
745 LOG_DEBUG("%s", adiv5_dap_name(dap));
746
747 /*
748 * Early initialize dap->dp_ctrl_stat.
749 * In jtag mode only, if the following atomic reads fail and set the
750 * sticky error, it will trigger the clearing of the sticky. Without this
751 * initialization system and debug power would be disabled while clearing
752 * the sticky error bit.
753 */
754 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
755
756 dap->do_reconnect = false;
757
758 dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
759 if (dap->do_reconnect) {
760 /* dap connect calls dap_dp_init() after transport dependent initialization */
761 return dap->ops->connect(dap);
762 } else {
763 return dap_dp_init(dap);
764 }
765 }
766
767 /**
768 * Initialize a DAP. This sets up the power domains, prepares the DP
769 * for further use, and arranges to use AP #0 for all AP operations
770 * until dap_ap-select() changes that policy.
771 *
772 * @param ap The MEM-AP being initialized.
773 */
774 int mem_ap_init(struct adiv5_ap *ap)
775 {
776 /* check that we support packed transfers */
777 uint32_t csw, cfg;
778 int retval;
779 struct adiv5_dap *dap = ap->dap;
780
781 /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
782 /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
783 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
784 if (retval != ERROR_OK)
785 return retval;
786
787 retval = dap_run(dap);
788 if (retval != ERROR_OK)
789 return retval;
790
791 ap->cfg_reg = cfg;
792 ap->tar_valid = false;
793 ap->csw_value = 0; /* force csw and tar write */
794 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
795 if (retval != ERROR_OK)
796 return retval;
797
798 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
799 if (retval != ERROR_OK)
800 return retval;
801
802 retval = dap_run(dap);
803 if (retval != ERROR_OK)
804 return retval;
805
806 if (csw & CSW_ADDRINC_PACKED)
807 ap->packed_transfers = true;
808 else
809 ap->packed_transfers = false;
810
811 /* Packed transfers on TI BE-32 processors do not work correctly in
812 * many cases. */
813 if (dap->ti_be_32_quirks)
814 ap->packed_transfers = false;
815
816 LOG_DEBUG("MEM_AP Packed Transfers: %s",
817 ap->packed_transfers ? "enabled" : "disabled");
818
819 /* The ARM ADI spec leaves implementation-defined whether unaligned
820 * memory accesses work, only work partially, or cause a sticky error.
821 * On TI BE-32 processors, reads seem to return garbage in some bytes
822 * and unaligned writes seem to cause a sticky error.
823 * TODO: it would be nice to have a way to detect whether unaligned
824 * operations are supported on other processors. */
825 ap->unaligned_access_bad = dap->ti_be_32_quirks;
826
827 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
828 !!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE));
829
830 return ERROR_OK;
831 }
832
833 /**
834 * Put the debug link into SWD mode, if the target supports it.
835 * The link's initial mode may be either JTAG (for example,
836 * with SWJ-DP after reset) or SWD.
837 *
838 * Note that targets using the JTAG-DP do not support SWD, and that
839 * some targets which could otherwise support it may have been
840 * configured to disable SWD signaling
841 *
842 * @param dap The DAP used
843 * @return ERROR_OK or else a fault code.
844 */
845 int dap_to_swd(struct adiv5_dap *dap)
846 {
847 LOG_DEBUG("Enter SWD mode");
848
849 return dap_send_sequence(dap, JTAG_TO_SWD);
850 }
851
852 /**
853 * Put the debug link into JTAG mode, if the target supports it.
854 * The link's initial mode may be either SWD or JTAG.
855 *
856 * Note that targets implemented with SW-DP do not support JTAG, and
857 * that some targets which could otherwise support it may have been
858 * configured to disable JTAG signaling
859 *
860 * @param dap The DAP used
861 * @return ERROR_OK or else a fault code.
862 */
863 int dap_to_jtag(struct adiv5_dap *dap)
864 {
865 LOG_DEBUG("Enter JTAG mode");
866
867 return dap_send_sequence(dap, SWD_TO_JTAG);
868 }
869
870 /* CID interpretation -- see ARM IHI 0029E table B2-7
871 * and ARM IHI 0031E table D1-2.
872 *
873 * From 2009/11/25 commit 21378f58b604:
874 * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
875 * Let's keep it as is, for the time being
876 */
877 static const char *class_description[16] = {
878 [0x0] = "Generic verification component",
879 [0x1] = "ROM table",
880 [0x2] = "Reserved",
881 [0x3] = "Reserved",
882 [0x4] = "Reserved",
883 [0x5] = "Reserved",
884 [0x6] = "Reserved",
885 [0x7] = "Reserved",
886 [0x8] = "Reserved",
887 [0x9] = "CoreSight component",
888 [0xA] = "Reserved",
889 [0xB] = "Peripheral Test Block",
890 [0xC] = "Reserved",
891 [0xD] = "OptimoDE DESS", /* see above */
892 [0xE] = "Generic IP component",
893 [0xF] = "CoreLink, PrimeCell or System component",
894 };
895
896 #define ARCH_ID(architect, archid) ( \
897 (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
898 (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
899 )
900
901 static const struct {
902 uint32_t arch_id;
903 const char *description;
904 } class0x9_devarch[] = {
905 /* keep same unsorted order as in ARM IHI0029E */
906 { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
907 { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
908 { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
909 { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
910 { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
911 { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
912 { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
913 { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
914 { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
915 { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
916 { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
917 { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
918 { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
919 { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
920 { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
921 { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
922 { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
923 { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
924 { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
925 { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
926 { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
927 { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
928 };
929
930 #define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
931 #define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
932
933 static const char *class0x9_devarch_description(uint32_t devarch)
934 {
935 if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
936 return "not present";
937
938 for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++)
939 if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id)
940 return class0x9_devarch[i].description;
941
942 return "unknown";
943 }
944
945 static const struct {
946 enum ap_type type;
947 const char *description;
948 } ap_types[] = {
949 { AP_TYPE_JTAG_AP, "JTAG-AP" },
950 { AP_TYPE_COM_AP, "COM-AP" },
951 { AP_TYPE_AHB3_AP, "MEM-AP AHB3" },
952 { AP_TYPE_APB_AP, "MEM-AP APB2 or APB3" },
953 { AP_TYPE_AXI_AP, "MEM-AP AXI3 or AXI4" },
954 { AP_TYPE_AHB5_AP, "MEM-AP AHB5" },
955 { AP_TYPE_APB4_AP, "MEM-AP APB4" },
956 { AP_TYPE_AXI5_AP, "MEM-AP AXI5" },
957 { AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
958 };
959
960 static const char *ap_type_to_description(enum ap_type type)
961 {
962 for (unsigned int i = 0; i < ARRAY_SIZE(ap_types); i++)
963 if (type == ap_types[i].type)
964 return ap_types[i].description;
965
966 return "Unknown";
967 }
968
969 /*
970 * This function checks the ID for each access port to find the requested Access Port type
971 */
972 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
973 {
974 int ap_num;
975
976 /* Maximum AP number is 255 since the SELECT register is 8 bits */
977 for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
978
979 /* read the IDR register of the Access Port */
980 uint32_t id_val = 0;
981
982 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
983 if (retval != ERROR_OK)
984 return retval;
985
986 retval = dap_run(dap);
987
988 /* Reading register for a non-existent AP should not cause an error,
989 * but just to be sure, try to continue searching if an error does happen.
990 */
991 if (retval == ERROR_OK && (id_val & AP_TYPE_MASK) == type_to_find) {
992 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
993 ap_type_to_description(type_to_find),
994 ap_num, id_val);
995
996 *ap_out = &dap->ap[ap_num];
997 return ERROR_OK;
998 }
999 }
1000
1001 LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
1002 return ERROR_FAIL;
1003 }
1004
1005 int dap_get_debugbase(struct adiv5_ap *ap,
1006 target_addr_t *dbgbase, uint32_t *apid)
1007 {
1008 struct adiv5_dap *dap = ap->dap;
1009 int retval;
1010 uint32_t baseptr_upper, baseptr_lower;
1011
1012 if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
1013 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
1014 if (retval != ERROR_OK)
1015 return retval;
1016 }
1017 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower);
1018 if (retval != ERROR_OK)
1019 return retval;
1020 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
1021 if (retval != ERROR_OK)
1022 return retval;
1023 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1024 if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
1025 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
1026 if (retval != ERROR_OK)
1027 return retval;
1028 }
1029
1030 retval = dap_run(dap);
1031 if (retval != ERROR_OK)
1032 return retval;
1033
1034 if (!is_64bit_ap(ap))
1035 baseptr_upper = 0;
1036 *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
1037
1038 return ERROR_OK;
1039 }
1040
1041 int dap_lookup_cs_component(struct adiv5_ap *ap,
1042 target_addr_t dbgbase, uint8_t type, target_addr_t *addr, int32_t *idx)
1043 {
1044 uint32_t romentry, entry_offset = 0, devtype;
1045 target_addr_t component_base;
1046 int retval;
1047
1048 dbgbase &= 0xFFFFFFFFFFFFF000ull;
1049 *addr = 0;
1050
1051 do {
1052 retval = mem_ap_read_atomic_u32(ap, dbgbase |
1053 entry_offset, &romentry);
1054 if (retval != ERROR_OK)
1055 return retval;
1056
1057 component_base = dbgbase + (target_addr_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK);
1058
1059 if (romentry & ARM_CS_ROMENTRY_PRESENT) {
1060 uint32_t c_cid1;
1061 retval = mem_ap_read_atomic_u32(ap, component_base + ARM_CS_CIDR1, &c_cid1);
1062 if (retval != ERROR_OK) {
1063 LOG_ERROR("Can't read component with base address " TARGET_ADDR_FMT
1064 ", the corresponding core might be turned off", component_base);
1065 return retval;
1066 }
1067 unsigned int class = (c_cid1 & ARM_CS_CIDR1_CLASS_MASK) >> ARM_CS_CIDR1_CLASS_SHIFT;
1068 if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
1069 retval = dap_lookup_cs_component(ap, component_base,
1070 type, addr, idx);
1071 if (retval == ERROR_OK)
1072 break;
1073 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1074 return retval;
1075 }
1076
1077 retval = mem_ap_read_atomic_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &devtype);
1078 if (retval != ERROR_OK)
1079 return retval;
1080 if ((devtype & ARM_CS_C9_DEVTYPE_MASK) == type) {
1081 if (!*idx) {
1082 *addr = component_base;
1083 break;
1084 } else
1085 (*idx)--;
1086 }
1087 }
1088 entry_offset += 4;
1089 } while ((romentry > 0) && (entry_offset < 0xf00));
1090
1091 if (!*addr)
1092 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1093
1094 return ERROR_OK;
1095 }
1096
1097 /** Holds registers and coordinates of a CoreSight component */
1098 struct cs_component_vals {
1099 struct adiv5_ap *ap;
1100 target_addr_t component_base;
1101 uint64_t pid;
1102 uint32_t cid;
1103 uint32_t devarch;
1104 uint32_t devid;
1105 uint32_t devtype_memtype;
1106 };
1107
1108 /**
1109 * Read the CoreSight registers needed during ROM Table Parsing (RTP).
1110 *
1111 * @param ap Pointer to AP containing the component.
1112 * @param component_base On MEM-AP access method, base address of the component.
1113 * @param v Pointer to the struct holding the value of registers.
1114 *
1115 * @return ERROR_OK on success, else a fault code.
1116 */
1117 static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
1118 struct cs_component_vals *v)
1119 {
1120 assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
1121 assert(ap && v);
1122
1123 uint32_t cid0, cid1, cid2, cid3;
1124 uint32_t pid0, pid1, pid2, pid3, pid4;
1125 int retval = ERROR_OK;
1126
1127 v->ap = ap;
1128 v->component_base = component_base;
1129
1130 /* sort by offset to gain speed */
1131
1132 /*
1133 * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices
1134 * only, but are at offset above 0xf00, so can be read on any device
1135 * without triggering error. Read them for eventual use on Class 0x9.
1136 */
1137 if (retval == ERROR_OK)
1138 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVARCH, &v->devarch);
1139
1140 if (retval == ERROR_OK)
1141 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVID, &v->devid);
1142
1143 /* Same address as ARM_CS_C1_MEMTYPE */
1144 if (retval == ERROR_OK)
1145 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
1146
1147 if (retval == ERROR_OK)
1148 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
1149
1150 if (retval == ERROR_OK)
1151 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
1152 if (retval == ERROR_OK)
1153 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
1154 if (retval == ERROR_OK)
1155 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
1156 if (retval == ERROR_OK)
1157 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
1158
1159 if (retval == ERROR_OK)
1160 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
1161 if (retval == ERROR_OK)
1162 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
1163 if (retval == ERROR_OK)
1164 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
1165 if (retval == ERROR_OK)
1166 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
1167
1168 if (retval == ERROR_OK)
1169 retval = dap_run(ap->dap);
1170 if (retval != ERROR_OK) {
1171 LOG_DEBUG("Failed read CoreSight registers");
1172 return retval;
1173 }
1174
1175 v->cid = (cid3 & 0xff) << 24
1176 | (cid2 & 0xff) << 16
1177 | (cid1 & 0xff) << 8
1178 | (cid0 & 0xff);
1179 v->pid = (uint64_t)(pid4 & 0xff) << 32
1180 | (pid3 & 0xff) << 24
1181 | (pid2 & 0xff) << 16
1182 | (pid1 & 0xff) << 8
1183 | (pid0 & 0xff);
1184
1185 return ERROR_OK;
1186 }
1187
1188 /* Part number interpretations are from Cortex
1189 * core specs, the CoreSight components TRM
1190 * (ARM DDI 0314H), CoreSight System Design
1191 * Guide (ARM DGI 0012D) and ETM specs; also
1192 * from chip observation (e.g. TI SDTI).
1193 */
1194
1195 static const struct dap_part_nums {
1196 uint16_t designer_id;
1197 uint16_t part_num;
1198 const char *type;
1199 const char *full;
1200 } dap_part_nums[] = {
1201 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1202 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1203 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1204 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1205 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1206 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1207 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1208 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1209 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1210 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1211 { ARM_ID, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
1212 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1213 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1214 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1215 { ARM_ID, 0x492, "Cortex-R52 GICD", "(Distributor)", },
1216 { ARM_ID, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
1217 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1218 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1219 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1220 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1221 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1222 { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1223 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1224 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1225 { ARM_ID, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
1226 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1227 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1228 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1229 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1230 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1231 { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1232 { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
1233 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1234 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1235 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1236 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1237 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1238 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1239 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1240 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1241 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1242 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1243 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1244 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1245 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1246 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1247 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1248 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1249 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1250 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1251 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1252 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1253 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1254 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1255 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1256 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1257 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1258 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1259 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1260 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1261 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1262 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1263 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1264 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1265 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1266 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1267 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1268 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1269 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1270 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1271 { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1272 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1273 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1274 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1275 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1276 { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1277 { ARM_ID, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
1278 { ARM_ID, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
1279 { ARM_ID, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
1280 { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
1281 { ARM_ID, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
1282 { ARM_ID, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
1283 { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
1284 { ARM_ID, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
1285 { ARM_ID, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
1286 { ARM_ID, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
1287 { ARM_ID, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
1288 { ARM_ID, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
1289 { ARM_ID, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
1290 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1291 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1292 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1293 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1294 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1295 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1296 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1297 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1298 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1299 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1300 { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1301 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1302 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1303 { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
1304 { ARM_ID, 0xd0c, "Neoverse N1", "(Debug Unit)", },
1305 { ARM_ID, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
1306 { ARM_ID, 0xd49, "Neoverse N2", "(Debug Unit)", },
1307 { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1308 { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1309 { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
1310 { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1311 { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1312 { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1313 { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1314 { 0x065, 0x000, "SHARC+/Blackfin+", "", },
1315 { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1316 { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
1317 { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
1318 { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
1319 { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
1320 { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1321 { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1322 { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1323 { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
1324 { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1325 };
1326
1327 static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
1328 {
1329 static const struct dap_part_nums unknown = {
1330 .type = "Unrecognized",
1331 .full = "",
1332 };
1333
1334 for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
1335 if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
1336 return &dap_part_nums[i];
1337
1338 return &unknown;
1339 }
1340
1341 static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
1342 {
1343 const char *major = "Reserved", *subtype = "Reserved";
1344 const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
1345 const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
1346 switch (devtype_major) {
1347 case 0:
1348 major = "Miscellaneous";
1349 switch (minor) {
1350 case 0:
1351 subtype = "other";
1352 break;
1353 case 4:
1354 subtype = "Validation component";
1355 break;
1356 }
1357 break;
1358 case 1:
1359 major = "Trace Sink";
1360 switch (minor) {
1361 case 0:
1362 subtype = "other";
1363 break;
1364 case 1:
1365 subtype = "Port";
1366 break;
1367 case 2:
1368 subtype = "Buffer";
1369 break;
1370 case 3:
1371 subtype = "Router";
1372 break;
1373 }
1374 break;
1375 case 2:
1376 major = "Trace Link";
1377 switch (minor) {
1378 case 0:
1379 subtype = "other";
1380 break;
1381 case 1:
1382 subtype = "Funnel, router";
1383 break;
1384 case 2:
1385 subtype = "Filter";
1386 break;
1387 case 3:
1388 subtype = "FIFO, buffer";
1389 break;
1390 }
1391 break;
1392 case 3:
1393 major = "Trace Source";
1394 switch (minor) {
1395 case 0:
1396 subtype = "other";
1397 break;
1398 case 1:
1399 subtype = "Processor";
1400 break;
1401 case 2:
1402 subtype = "DSP";
1403 break;
1404 case 3:
1405 subtype = "Engine/Coprocessor";
1406 break;
1407 case 4:
1408 subtype = "Bus";
1409 break;
1410 case 6:
1411 subtype = "Software";
1412 break;
1413 }
1414 break;
1415 case 4:
1416 major = "Debug Control";
1417 switch (minor) {
1418 case 0:
1419 subtype = "other";
1420 break;
1421 case 1:
1422 subtype = "Trigger Matrix";
1423 break;
1424 case 2:
1425 subtype = "Debug Auth";
1426 break;
1427 case 3:
1428 subtype = "Power Requestor";
1429 break;
1430 }
1431 break;
1432 case 5:
1433 major = "Debug Logic";
1434 switch (minor) {
1435 case 0:
1436 subtype = "other";
1437 break;
1438 case 1:
1439 subtype = "Processor";
1440 break;
1441 case 2:
1442 subtype = "DSP";
1443 break;
1444 case 3:
1445 subtype = "Engine/Coprocessor";
1446 break;
1447 case 4:
1448 subtype = "Bus";
1449 break;
1450 case 5:
1451 subtype = "Memory";
1452 break;
1453 }
1454 break;
1455 case 6:
1456 major = "Performance Monitor";
1457 switch (minor) {
1458 case 0:
1459 subtype = "other";
1460 break;
1461 case 1:
1462 subtype = "Processor";
1463 break;
1464 case 2:
1465 subtype = "DSP";
1466 break;
1467 case 3:
1468 subtype = "Engine/Coprocessor";
1469 break;
1470 case 4:
1471 subtype = "Bus";
1472 break;
1473 case 5:
1474 subtype = "Memory";
1475 break;
1476 }
1477 break;
1478 }
1479 command_print(cmd, "\t\tType is 0x%02x, %s, %s",
1480 devtype & ARM_CS_C9_DEVTYPE_MASK,
1481 major, subtype);
1482 return ERROR_OK;
1483 }
1484
1485 /* Broken ROM tables can have circular references. Stop after a while */
1486 #define ROM_TABLE_MAX_DEPTH (16)
1487
1488 /* TODO: these prototypes will be removed in a following patch */
1489 static int dap_info_mem_ap_header(struct command_invocation *cmd,
1490 int retval, struct adiv5_ap *ap,
1491 target_addr_t dbgbase, uint32_t apid);
1492 static int dap_info_cs_component(struct command_invocation *cmd,
1493 int retval, struct cs_component_vals *v, int depth);
1494 static int dap_info_rom_table_entry(struct command_invocation *cmd,
1495 int retval, int depth,
1496 unsigned int offset, uint32_t romentry);
1497
1498 static int rtp_cs_component(struct command_invocation *cmd,
1499 struct adiv5_ap *ap, target_addr_t dbgbase, int depth);
1500
1501 static int rtp_rom_loop(struct command_invocation *cmd,
1502 struct adiv5_ap *ap, target_addr_t base_address, int depth,
1503 unsigned int max_entries)
1504 {
1505 assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1506
1507 unsigned int offset = 0;
1508 while (max_entries--) {
1509 uint32_t romentry;
1510 unsigned int saved_offset = offset;
1511
1512 int retval = mem_ap_read_atomic_u32(ap, base_address + offset, &romentry);
1513 offset += 4;
1514 if (retval != ERROR_OK)
1515 LOG_DEBUG("Failed read ROM table entry");
1516
1517 retval = dap_info_rom_table_entry(cmd, retval, depth, saved_offset, romentry);
1518 if (retval != ERROR_OK)
1519 return retval;
1520
1521 if (romentry == 0) {
1522 /* End of ROM table */
1523 break;
1524 }
1525
1526 if (!(romentry & ARM_CS_ROMENTRY_PRESENT))
1527 continue;
1528
1529 /* Recurse. "romentry" is signed */
1530 target_addr_t component_base = base_address + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK);
1531 retval = rtp_cs_component(cmd, ap, component_base, depth + 1);
1532 if (retval != ERROR_OK) {
1533 /* TODO: do we need to send an ABORT before continuing? */
1534 LOG_DEBUG("Ignore error parsing CoreSight component");
1535 continue;
1536 }
1537 }
1538
1539 return ERROR_OK;
1540 }
1541
1542 static int rtp_cs_component(struct command_invocation *cmd,
1543 struct adiv5_ap *ap, target_addr_t base_address, int depth)
1544 {
1545 struct cs_component_vals v;
1546 int retval;
1547
1548 assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1549
1550 if (depth > ROM_TABLE_MAX_DEPTH)
1551 retval = ERROR_FAIL;
1552 else
1553 retval = rtp_read_cs_regs(ap, base_address, &v);
1554
1555 retval = dap_info_cs_component(cmd, retval, &v, depth);
1556 if (retval != ERROR_OK)
1557 return ERROR_OK; /* Don't abort recursion */
1558
1559 if (!is_valid_arm_cs_cidr(v.cid))
1560 return ERROR_OK; /* Don't abort recursion */
1561
1562 const unsigned int class = ARM_CS_CIDR_CLASS(v.cid);
1563
1564 if (class == ARM_CS_CLASS_0X1_ROM_TABLE)
1565 return rtp_rom_loop(cmd, ap, base_address, depth, 960);
1566
1567 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
1568 if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
1569 return ERROR_OK;
1570
1571 /* quit if not ROM table */
1572 if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
1573 return ERROR_OK;
1574
1575 return rtp_rom_loop(cmd, ap, base_address, depth, 512);
1576 }
1577
1578 /* Class other than 0x1 and 0x9 */
1579 return ERROR_OK;
1580 }
1581
1582 int dap_info_command(struct command_invocation *cmd,
1583 struct adiv5_ap *ap)
1584 {
1585 int retval;
1586 uint32_t apid;
1587 target_addr_t dbgbase;
1588 target_addr_t invalid_entry;
1589
1590 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1591 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1592 retval = dap_info_mem_ap_header(cmd, retval, ap, dbgbase, apid);
1593 if (retval != ERROR_OK)
1594 return retval;
1595
1596 if (apid == 0)
1597 return ERROR_FAIL;
1598
1599 /* NOTE: a MEM-AP may have a single CoreSight component that's
1600 * not a ROM table ... or have no such components at all.
1601 */
1602 const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
1603
1604 if (class == AP_REG_IDR_CLASS_MEM_AP) {
1605 if (is_64bit_ap(ap))
1606 invalid_entry = 0xFFFFFFFFFFFFFFFFull;
1607 else
1608 invalid_entry = 0xFFFFFFFFul;
1609
1610 if (dbgbase != invalid_entry && (dbgbase & 0x3) != 0x2)
1611 rtp_cs_component(cmd, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0);
1612 }
1613
1614 return ERROR_OK;
1615 }
1616
1617 /* Actions for command "dap info" */
1618
1619 static int dap_info_mem_ap_header(struct command_invocation *cmd,
1620 int retval, struct adiv5_ap *ap,
1621 target_addr_t dbgbase, uint32_t apid)
1622 {
1623 target_addr_t invalid_entry;
1624
1625 if (retval != ERROR_OK) {
1626 command_print(cmd, "\t\tCan't read MEM-AP, the corresponding core might be turned off");
1627 return retval;
1628 }
1629
1630 command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
1631 if (apid == 0) {
1632 command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num);
1633 return ERROR_FAIL;
1634 }
1635
1636 command_print(cmd, "\tType is %s", ap_type_to_description(apid & AP_TYPE_MASK));
1637
1638 /* NOTE: a MEM-AP may have a single CoreSight component that's
1639 * not a ROM table ... or have no such components at all.
1640 */
1641 const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
1642
1643 if (class == AP_REG_IDR_CLASS_MEM_AP) {
1644 if (is_64bit_ap(ap))
1645 invalid_entry = 0xFFFFFFFFFFFFFFFFull;
1646 else
1647 invalid_entry = 0xFFFFFFFFul;
1648
1649 command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase);
1650
1651 if (dbgbase == invalid_entry || (dbgbase & 0x3) == 0x2) {
1652 command_print(cmd, "\tNo ROM table present");
1653 } else {
1654 if (dbgbase & 0x01)
1655 command_print(cmd, "\tValid ROM table present");
1656 else
1657 command_print(cmd, "\tROM table in legacy format");
1658 }
1659 }
1660
1661 return ERROR_OK;
1662 }
1663
1664 static int dap_info_cs_component(struct command_invocation *cmd,
1665 int retval, struct cs_component_vals *v, int depth)
1666 {
1667 if (depth > ROM_TABLE_MAX_DEPTH) {
1668 command_print(cmd, "\tTables too deep");
1669 return ERROR_FAIL;
1670 }
1671
1672 command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
1673
1674 if (retval != ERROR_OK) {
1675 command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
1676 return retval;
1677 }
1678
1679 if (!is_valid_arm_cs_cidr(v->cid)) {
1680 command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, v->cid);
1681 return ERROR_OK; /* Don't abort recursion */
1682 }
1683
1684 /* component may take multiple 4K pages */
1685 uint32_t size = ARM_CS_PIDR_SIZE(v->pid);
1686 if (size > 0)
1687 command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, v->component_base - 0x1000 * size);
1688
1689 command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, v->pid);
1690
1691 const unsigned int part_num = ARM_CS_PIDR_PART(v->pid);
1692 unsigned int designer_id = ARM_CS_PIDR_DESIGNER(v->pid);
1693
1694 if (v->pid & ARM_CS_PIDR_JEDEC) {
1695 /* JEP106 code */
1696 command_print(cmd, "\t\tDesigner is 0x%03x, %s",
1697 designer_id, jep106_manufacturer(designer_id));
1698 } else {
1699 /* Legacy ASCII ID, clear invalid bits */
1700 designer_id &= 0x7f;
1701 command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s",
1702 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1703 }
1704
1705 const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num);
1706 command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full);
1707
1708 const unsigned int class = ARM_CS_CIDR_CLASS(v->cid);
1709 command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]);
1710
1711 if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
1712 if (v->devtype_memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
1713 command_print(cmd, "\t\tMEMTYPE system memory present on bus");
1714 else
1715 command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1716 return ERROR_OK;
1717 }
1718
1719 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
1720 dap_devtype_display(cmd, v->devtype_memtype);
1721
1722 /* REVISIT also show ARM_CS_C9_DEVID */
1723
1724 if ((v->devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
1725 return ERROR_OK;
1726
1727 unsigned int architect_id = ARM_CS_C9_DEVARCH_ARCHITECT(v->devarch);
1728 unsigned int revision = ARM_CS_C9_DEVARCH_REVISION(v->devarch);
1729 command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", v->devarch,
1730 jep106_manufacturer(architect_id), class0x9_devarch_description(v->devarch),
1731 revision);
1732
1733 if ((v->devarch & DEVARCH_ID_MASK) == DEVARCH_ROM_C_0X9) {
1734 command_print(cmd, "\t\tType is ROM table");
1735
1736 if (v->devid & ARM_CS_C9_DEVID_SYSMEM_MASK)
1737 command_print(cmd, "\t\tMEMTYPE system memory present on bus");
1738 else
1739 command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1740 }
1741 return ERROR_OK;
1742 }
1743
1744 /* Class other than 0x1 and 0x9 */
1745 return ERROR_OK;
1746 }
1747
1748 static int dap_info_rom_table_entry(struct command_invocation *cmd,
1749 int retval, int depth,
1750 unsigned int offset, uint32_t romentry)
1751 {
1752 char tabs[16] = "";
1753
1754 if (depth)
1755 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1756
1757 if (retval != ERROR_OK) {
1758 command_print(cmd, "\t%sROMTABLE[0x%x] Read error", tabs, offset);
1759 command_print(cmd, "\t\tUnable to continue");
1760 command_print(cmd, "\t%s\tStop parsing of ROM table", tabs);
1761 return retval;
1762 }
1763
1764 command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%08" PRIx32,
1765 tabs, offset, romentry);
1766
1767 if (romentry == 0) {
1768 command_print(cmd, "\t%s\tEnd of ROM table", tabs);
1769 return ERROR_OK;
1770 }
1771
1772 if (!(romentry & ARM_CS_ROMENTRY_PRESENT)) {
1773 command_print(cmd, "\t\tComponent not present");
1774 return ERROR_OK;
1775 }
1776
1777 return ERROR_OK;
1778 }
1779
1780 enum adiv5_cfg_param {
1781 CFG_DAP,
1782 CFG_AP_NUM,
1783 CFG_BASEADDR,
1784 CFG_CTIBASE, /* DEPRECATED */
1785 };
1786
1787 static const struct jim_nvp nvp_config_opts[] = {
1788 { .name = "-dap", .value = CFG_DAP },
1789 { .name = "-ap-num", .value = CFG_AP_NUM },
1790 { .name = "-baseaddr", .value = CFG_BASEADDR },
1791 { .name = "-ctibase", .value = CFG_CTIBASE }, /* DEPRECATED */
1792 { .name = NULL, .value = -1 }
1793 };
1794
1795 static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
1796 struct adiv5_dap **dap_p, int *ap_num_p, uint32_t *base_p)
1797 {
1798 if (!goi->argc)
1799 return JIM_OK;
1800
1801 Jim_SetEmptyResult(goi->interp);
1802
1803 struct jim_nvp *n;
1804 int e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
1805 goi->argv[0], &n);
1806 if (e != JIM_OK)
1807 return JIM_CONTINUE;
1808
1809 /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
1810 if (!base_p && (n->value == CFG_BASEADDR || n->value == CFG_CTIBASE))
1811 return JIM_CONTINUE;
1812
1813 e = jim_getopt_obj(goi, NULL);
1814 if (e != JIM_OK)
1815 return e;
1816
1817 switch (n->value) {
1818 case CFG_DAP:
1819 if (goi->isconfigure) {
1820 Jim_Obj *o_t;
1821 struct adiv5_dap *dap;
1822 e = jim_getopt_obj(goi, &o_t);
1823 if (e != JIM_OK)
1824 return e;
1825 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1826 if (!dap) {
1827 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1828 return JIM_ERR;
1829 }
1830 if (*dap_p && *dap_p != dap) {
1831 Jim_SetResultString(goi->interp,
1832 "DAP assignment cannot be changed!", -1);
1833 return JIM_ERR;
1834 }
1835 *dap_p = dap;
1836 } else {
1837 if (goi->argc)
1838 goto err_no_param;
1839 if (!*dap_p) {
1840 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1841 return JIM_ERR;
1842 }
1843 Jim_SetResultString(goi->interp, adiv5_dap_name(*dap_p), -1);
1844 }
1845 break;
1846
1847 case CFG_AP_NUM:
1848 if (goi->isconfigure) {
1849 jim_wide ap_num;
1850 e = jim_getopt_wide(goi, &ap_num);
1851 if (e != JIM_OK)
1852 return e;
1853 if (ap_num < 0 || ap_num > DP_APSEL_MAX) {
1854 Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
1855 return JIM_ERR;
1856 }
1857 *ap_num_p = ap_num;
1858 } else {
1859 if (goi->argc)
1860 goto err_no_param;
1861 if (*ap_num_p == DP_APSEL_INVALID) {
1862 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1863 return JIM_ERR;
1864 }
1865 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *ap_num_p));
1866 }
1867 break;
1868
1869 case CFG_CTIBASE:
1870 LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
1871 /* fall through */
1872 case CFG_BASEADDR:
1873 if (goi->isconfigure) {
1874 jim_wide base;
1875 e = jim_getopt_wide(goi, &base);
1876 if (e != JIM_OK)
1877 return e;
1878 *base_p = (uint32_t)base;
1879 } else {
1880 if (goi->argc)
1881 goto err_no_param;
1882 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *base_p));
1883 }
1884 break;
1885 };
1886
1887 return JIM_OK;
1888
1889 err_no_param:
1890 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "NO PARAMS");
1891 return JIM_ERR;
1892 }
1893
1894 int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
1895 {
1896 struct adiv5_private_config *pc;
1897 int e;
1898
1899 pc = (struct adiv5_private_config *)target->private_config;
1900 if (!pc) {
1901 pc = calloc(1, sizeof(struct adiv5_private_config));
1902 pc->ap_num = DP_APSEL_INVALID;
1903 target->private_config = pc;
1904 }
1905
1906 target->has_dap = true;
1907
1908 e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL);
1909 if (e != JIM_OK)
1910 return e;
1911
1912 if (pc->dap && !target->dap_configured) {
1913 if (target->tap_configured) {
1914 pc->dap = NULL;
1915 Jim_SetResultString(goi->interp,
1916 "-chain-position and -dap configparams are mutually exclusive!", -1);
1917 return JIM_ERR;
1918 }
1919 target->tap = pc->dap->tap;
1920 target->dap_configured = true;
1921 }
1922
1923 return JIM_OK;
1924 }
1925
1926 int adiv5_verify_config(struct adiv5_private_config *pc)
1927 {
1928 if (!pc)
1929 return ERROR_FAIL;
1930
1931 if (!pc->dap)
1932 return ERROR_FAIL;
1933
1934 return ERROR_OK;
1935 }
1936
1937 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
1938 struct jim_getopt_info *goi)
1939 {
1940 return adiv5_jim_spot_configure(goi, &cfg->dap, &cfg->ap_num, &cfg->base);
1941 }
1942
1943 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
1944 {
1945 p->dap = NULL;
1946 p->ap_num = DP_APSEL_INVALID;
1947 p->base = 0;
1948 return ERROR_OK;
1949 }
1950
1951 COMMAND_HANDLER(handle_dap_info_command)
1952 {
1953 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1954 uint32_t apsel;
1955
1956 switch (CMD_ARGC) {
1957 case 0:
1958 apsel = dap->apsel;
1959 break;
1960 case 1:
1961 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1962 if (apsel > DP_APSEL_MAX) {
1963 command_print(CMD, "Invalid AP number");
1964 return ERROR_COMMAND_ARGUMENT_INVALID;
1965 }
1966 break;
1967 default:
1968 return ERROR_COMMAND_SYNTAX_ERROR;
1969 }
1970
1971 return dap_info_command(CMD, &dap->ap[apsel]);
1972 }
1973
1974 COMMAND_HANDLER(dap_baseaddr_command)
1975 {
1976 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1977 uint32_t apsel, baseaddr_lower, baseaddr_upper;
1978 struct adiv5_ap *ap;
1979 target_addr_t baseaddr;
1980 int retval;
1981
1982 baseaddr_upper = 0;
1983
1984 switch (CMD_ARGC) {
1985 case 0:
1986 apsel = dap->apsel;
1987 break;
1988 case 1:
1989 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1990 /* AP address is in bits 31:24 of DP_SELECT */
1991 if (apsel > DP_APSEL_MAX) {
1992 command_print(CMD, "Invalid AP number");
1993 return ERROR_COMMAND_ARGUMENT_INVALID;
1994 }
1995 break;
1996 default:
1997 return ERROR_COMMAND_SYNTAX_ERROR;
1998 }
1999
2000 /* NOTE: assumes we're talking to a MEM-AP, which
2001 * has a base address. There are other kinds of AP,
2002 * though they're not common for now. This should
2003 * use the ID register to verify it's a MEM-AP.
2004 */
2005
2006 ap = dap_ap(dap, apsel);
2007 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower);
2008
2009 if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
2010 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
2011
2012 if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
2013 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
2014 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper);
2015 }
2016
2017 if (retval == ERROR_OK)
2018 retval = dap_run(dap);
2019 if (retval != ERROR_OK)
2020 return retval;
2021
2022 if (is_64bit_ap(ap)) {
2023 baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
2024 command_print(CMD, "0x%016" PRIx64, baseaddr);
2025 } else
2026 command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
2027
2028 return ERROR_OK;
2029 }
2030
2031 COMMAND_HANDLER(dap_memaccess_command)
2032 {
2033 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2034 uint32_t memaccess_tck;
2035
2036 switch (CMD_ARGC) {
2037 case 0:
2038 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
2039 break;
2040 case 1:
2041 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
2042 break;
2043 default:
2044 return ERROR_COMMAND_SYNTAX_ERROR;
2045 }
2046 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
2047
2048 command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
2049 dap->ap[dap->apsel].memaccess_tck);
2050
2051 return ERROR_OK;
2052 }
2053
2054 COMMAND_HANDLER(dap_apsel_command)
2055 {
2056 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2057 uint32_t apsel;
2058
2059 switch (CMD_ARGC) {
2060 case 0:
2061 command_print(CMD, "%" PRIu32, dap->apsel);
2062 return ERROR_OK;
2063 case 1:
2064 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
2065 /* AP address is in bits 31:24 of DP_SELECT */
2066 if (apsel > DP_APSEL_MAX) {
2067 command_print(CMD, "Invalid AP number");
2068 return ERROR_COMMAND_ARGUMENT_INVALID;
2069 }
2070 break;
2071 default:
2072 return ERROR_COMMAND_SYNTAX_ERROR;
2073 }
2074
2075 dap->apsel = apsel;
2076 return ERROR_OK;
2077 }
2078
2079 COMMAND_HANDLER(dap_apcsw_command)
2080 {
2081 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2082 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
2083 uint32_t csw_val, csw_mask;
2084
2085 switch (CMD_ARGC) {
2086 case 0:
2087 command_print(CMD, "ap %" PRIu32 " selected, csw 0x%8.8" PRIx32,
2088 dap->apsel, apcsw);
2089 return ERROR_OK;
2090 case 1:
2091 if (strcmp(CMD_ARGV[0], "default") == 0)
2092 csw_val = CSW_AHB_DEFAULT;
2093 else
2094 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
2095
2096 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
2097 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
2098 return ERROR_COMMAND_ARGUMENT_INVALID;
2099 }
2100 apcsw = csw_val;
2101 break;
2102 case 2:
2103 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
2104 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
2105 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
2106 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
2107 return ERROR_COMMAND_ARGUMENT_INVALID;
2108 }
2109 apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
2110 break;
2111 default:
2112 return ERROR_COMMAND_SYNTAX_ERROR;
2113 }
2114 dap->ap[dap->apsel].csw_default = apcsw;
2115
2116 return 0;
2117 }
2118
2119
2120
2121 COMMAND_HANDLER(dap_apid_command)
2122 {
2123 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2124 uint32_t apsel, apid;
2125 int retval;
2126
2127 switch (CMD_ARGC) {
2128 case 0:
2129 apsel = dap->apsel;
2130 break;
2131 case 1:
2132 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
2133 /* AP address is in bits 31:24 of DP_SELECT */
2134 if (apsel > DP_APSEL_MAX) {
2135 command_print(CMD, "Invalid AP number");
2136 return ERROR_COMMAND_ARGUMENT_INVALID;
2137 }
2138 break;
2139 default:
2140 return ERROR_COMMAND_SYNTAX_ERROR;
2141 }
2142
2143 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
2144 if (retval != ERROR_OK)
2145 return retval;
2146 retval = dap_run(dap);
2147 if (retval != ERROR_OK)
2148 return retval;
2149
2150 command_print(CMD, "0x%8.8" PRIx32, apid);
2151
2152 return retval;
2153 }
2154
2155 COMMAND_HANDLER(dap_apreg_command)
2156 {
2157 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2158 uint32_t apsel, reg, value;
2159 struct adiv5_ap *ap;
2160 int retval;
2161
2162 if (CMD_ARGC < 2 || CMD_ARGC > 3)
2163 return ERROR_COMMAND_SYNTAX_ERROR;
2164
2165 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
2166 /* AP address is in bits 31:24 of DP_SELECT */
2167 if (apsel > DP_APSEL_MAX) {
2168 command_print(CMD, "Invalid AP number");
2169 return ERROR_COMMAND_ARGUMENT_INVALID;
2170 }
2171
2172 ap = dap_ap(dap, apsel);
2173
2174 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
2175 if (reg >= 256 || (reg & 3)) {
2176 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2177 return ERROR_COMMAND_ARGUMENT_INVALID;
2178 }
2179
2180 if (CMD_ARGC == 3) {
2181 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2182 switch (reg) {
2183 case MEM_AP_REG_CSW:
2184 ap->csw_value = 0; /* invalid, in case write fails */
2185 retval = dap_queue_ap_write(ap, reg, value);
2186 if (retval == ERROR_OK)
2187 ap->csw_value = value;
2188 break;
2189 case MEM_AP_REG_TAR:
2190 retval = dap_queue_ap_write(ap, reg, value);
2191 if (retval == ERROR_OK)
2192 ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value;
2193 else {
2194 /* To track independent writes to TAR and TAR64, two tar_valid flags */
2195 /* should be used. To keep it simple, tar_valid is only invalidated on a */
2196 /* write fail. This approach causes a later re-write of the TAR and TAR64 */
2197 /* if tar_valid is false. */
2198 ap->tar_valid = false;
2199 }
2200 break;
2201 case MEM_AP_REG_TAR64:
2202 retval = dap_queue_ap_write(ap, reg, value);
2203 if (retval == ERROR_OK)
2204 ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32);
2205 else {
2206 /* See above comment for the MEM_AP_REG_TAR failed write case */
2207 ap->tar_valid = false;
2208 }
2209 break;
2210 default:
2211 retval = dap_queue_ap_write(ap, reg, value);
2212 break;
2213 }
2214 } else {
2215 retval = dap_queue_ap_read(ap, reg, &value);
2216 }
2217 if (retval == ERROR_OK)
2218 retval = dap_run(dap);
2219
2220 if (retval != ERROR_OK)
2221 return retval;
2222
2223 if (CMD_ARGC == 2)
2224 command_print(CMD, "0x%08" PRIx32, value);
2225
2226 return retval;
2227 }
2228
2229 COMMAND_HANDLER(dap_dpreg_command)
2230 {
2231 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2232 uint32_t reg, value;
2233 int retval;
2234
2235 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2236 return ERROR_COMMAND_SYNTAX_ERROR;
2237
2238 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
2239 if (reg >= 256 || (reg & 3)) {
2240 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2241 return ERROR_COMMAND_ARGUMENT_INVALID;
2242 }
2243
2244 if (CMD_ARGC == 2) {
2245 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2246 retval = dap_queue_dp_write(dap, reg, value);
2247 } else {
2248 retval = dap_queue_dp_read(dap, reg, &value);
2249 }
2250 if (retval == ERROR_OK)
2251 retval = dap_run(dap);
2252
2253 if (retval != ERROR_OK)
2254 return retval;
2255
2256 if (CMD_ARGC == 1)
2257 command_print(CMD, "0x%08" PRIx32, value);
2258
2259 return retval;
2260 }
2261
2262 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
2263 {
2264 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2265 return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
2266 "TI BE-32 quirks mode");
2267 }
2268
2269 const struct command_registration dap_instance_commands[] = {
2270 {
2271 .name = "info",
2272 .handler = handle_dap_info_command,
2273 .mode = COMMAND_EXEC,
2274 .help = "display ROM table for MEM-AP "
2275 "(default currently selected AP)",
2276 .usage = "[ap_num]",
2277 },
2278 {
2279 .name = "apsel",
2280 .handler = dap_apsel_command,
2281 .mode = COMMAND_ANY,
2282 .help = "Set the currently selected AP (default 0) "
2283 "and display the result",
2284 .usage = "[ap_num]",
2285 },
2286 {
2287 .name = "apcsw",
2288 .handler = dap_apcsw_command,
2289 .mode = COMMAND_ANY,
2290 .help = "Set CSW default bits",
2291 .usage = "[value [mask]]",
2292 },
2293
2294 {
2295 .name = "apid",
2296 .handler = dap_apid_command,
2297 .mode = COMMAND_EXEC,
2298 .help = "return ID register from AP "
2299 "(default currently selected AP)",
2300 .usage = "[ap_num]",
2301 },
2302 {
2303 .name = "apreg",
2304 .handler = dap_apreg_command,
2305 .mode = COMMAND_EXEC,
2306 .help = "read/write a register from AP "
2307 "(reg is byte address of a word register, like 0 4 8...)",
2308 .usage = "ap_num reg [value]",
2309 },
2310 {
2311 .name = "dpreg",
2312 .handler = dap_dpreg_command,
2313 .mode = COMMAND_EXEC,
2314 .help = "read/write a register from DP "
2315 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
2316 .usage = "reg [value]",
2317 },
2318 {
2319 .name = "baseaddr",
2320 .handler = dap_baseaddr_command,
2321 .mode = COMMAND_EXEC,
2322 .help = "return debug base address from MEM-AP "
2323 "(default currently selected AP)",
2324 .usage = "[ap_num]",
2325 },
2326 {
2327 .name = "memaccess",
2328 .handler = dap_memaccess_command,
2329 .mode = COMMAND_EXEC,
2330 .help = "set/get number of extra tck for MEM-AP memory "
2331 "bus access [0-255]",
2332 .usage = "[cycles]",
2333 },
2334 {
2335 .name = "ti_be_32_quirks",
2336 .handler = dap_ti_be_32_quirks_command,
2337 .mode = COMMAND_CONFIG,
2338 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
2339 .usage = "[enable]",
2340 },
2341 COMMAND_REGISTRATION_DONE
2342 };
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