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[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * Copyright (C) 2019-2021, Ampere Computing LLC *
17 * *
18 * This program is free software; you can redistribute it and/or modify *
19 * it under the terms of the GNU General Public License as published by *
20 * the Free Software Foundation; either version 2 of the License, or *
21 * (at your option) any later version. *
22 * *
23 * This program is distributed in the hope that it will be useful, *
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
26 * GNU General Public License for more details. *
27 * *
28 * You should have received a copy of the GNU General Public License *
29 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focuses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction pipelining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include "arm_coresight.h"
79 #include "jtag/swd.h"
80 #include "transport/transport.h"
81 #include <helper/align.h>
82 #include <helper/jep106.h>
83 #include <helper/time_support.h>
84 #include <helper/list.h>
85 #include <helper/jim-nvp.h>
86
87 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
88
89 /*
90 uint32_t tar_block_size(uint32_t address)
91 Return the largest block starting at address that does not cross a tar block size alignment boundary
92 */
93 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
94 {
95 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
96 }
97
98 /***************************************************************************
99 * *
100 * DP and MEM-AP register access through APACC and DPACC *
101 * *
102 ***************************************************************************/
103
104 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
105 {
106 csw |= ap->csw_default;
107
108 if (csw != ap->csw_value) {
109 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
110 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW(ap->dap), csw);
111 if (retval != ERROR_OK) {
112 ap->csw_value = 0;
113 return retval;
114 }
115 ap->csw_value = csw;
116 }
117 return ERROR_OK;
118 }
119
120 static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
121 {
122 if (!ap->tar_valid || tar != ap->tar_value) {
123 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
124 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR(ap->dap), (uint32_t)(tar & 0xffffffffUL));
125 if (retval == ERROR_OK && is_64bit_ap(ap)) {
126 /* See if bits 63:32 of tar is different from last setting */
127 if ((ap->tar_value >> 32) != (tar >> 32))
128 retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64(ap->dap), (uint32_t)(tar >> 32));
129 }
130 if (retval != ERROR_OK) {
131 ap->tar_valid = false;
132 return retval;
133 }
134 ap->tar_value = tar;
135 ap->tar_valid = true;
136 }
137 return ERROR_OK;
138 }
139
140 static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
141 {
142 uint32_t lower;
143 uint32_t upper = 0;
144
145 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR(ap->dap), &lower);
146 if (retval == ERROR_OK && is_64bit_ap(ap))
147 retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64(ap->dap), &upper);
148
149 if (retval != ERROR_OK) {
150 ap->tar_valid = false;
151 return retval;
152 }
153
154 retval = dap_run(ap->dap);
155 if (retval != ERROR_OK) {
156 ap->tar_valid = false;
157 return retval;
158 }
159
160 *tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower;
161
162 ap->tar_value = *tar;
163 ap->tar_valid = true;
164 return ERROR_OK;
165 }
166
167 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
168 {
169 switch (ap->csw_value & CSW_ADDRINC_MASK) {
170 case CSW_ADDRINC_SINGLE:
171 switch (ap->csw_value & CSW_SIZE_MASK) {
172 case CSW_8BIT:
173 return 1;
174 case CSW_16BIT:
175 return 2;
176 case CSW_32BIT:
177 return 4;
178 default:
179 return 0;
180 }
181 case CSW_ADDRINC_PACKED:
182 return 4;
183 }
184 return 0;
185 }
186
187 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
188 */
189 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
190 {
191 if (!ap->tar_valid)
192 return;
193
194 uint32_t inc = mem_ap_get_tar_increment(ap);
195 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
196 ap->tar_valid = false;
197 else
198 ap->tar_value += inc;
199 }
200
201 /**
202 * Queue transactions setting up transfer parameters for the
203 * currently selected MEM-AP.
204 *
205 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
206 * initiate data reads or writes using memory or peripheral addresses.
207 * If the CSW is configured for it, the TAR may be automatically
208 * incremented after each transfer.
209 *
210 * @param ap The MEM-AP.
211 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
212 * matches the cached value, the register is not changed.
213 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
214 * matches the cached address, the register is not changed.
215 *
216 * @return ERROR_OK if the transaction was properly queued, else a fault code.
217 */
218 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
219 {
220 int retval;
221 retval = mem_ap_setup_csw(ap, csw);
222 if (retval != ERROR_OK)
223 return retval;
224 retval = mem_ap_setup_tar(ap, tar);
225 if (retval != ERROR_OK)
226 return retval;
227 return ERROR_OK;
228 }
229
230 /**
231 * Asynchronous (queued) read of a word from memory or a system register.
232 *
233 * @param ap The MEM-AP to access.
234 * @param address Address of the 32-bit word to read; it must be
235 * readable by the currently selected MEM-AP.
236 * @param value points to where the word will be stored when the
237 * transaction queue is flushed (assuming no errors).
238 *
239 * @return ERROR_OK for success. Otherwise a fault code.
240 */
241 int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
242 uint32_t *value)
243 {
244 int retval;
245
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when reading several consecutive addresses.
248 */
249 retval = mem_ap_setup_transfer(ap,
250 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
251 address & 0xFFFFFFFFFFFFFFF0ull);
252 if (retval != ERROR_OK)
253 return retval;
254
255 return dap_queue_ap_read(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC), value);
256 }
257
258 /**
259 * Synchronous read of a word from memory or a system register.
260 * As a side effect, this flushes any queued transactions.
261 *
262 * @param ap The MEM-AP to access.
263 * @param address Address of the 32-bit word to read; it must be
264 * readable by the currently selected MEM-AP.
265 * @param value points to where the result will be stored.
266 *
267 * @return ERROR_OK for success; *value holds the result.
268 * Otherwise a fault code.
269 */
270 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
271 uint32_t *value)
272 {
273 int retval;
274
275 retval = mem_ap_read_u32(ap, address, value);
276 if (retval != ERROR_OK)
277 return retval;
278
279 return dap_run(ap->dap);
280 }
281
282 /**
283 * Asynchronous (queued) write of a word to memory or a system register.
284 *
285 * @param ap The MEM-AP to access.
286 * @param address Address to be written; it must be writable by
287 * the currently selected MEM-AP.
288 * @param value Word that will be written to the address when transaction
289 * queue is flushed (assuming no errors).
290 *
291 * @return ERROR_OK for success. Otherwise a fault code.
292 */
293 int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
294 uint32_t value)
295 {
296 int retval;
297
298 /* Use banked addressing (REG_BDx) to avoid some link traffic
299 * (updating TAR) when writing several consecutive addresses.
300 */
301 retval = mem_ap_setup_transfer(ap,
302 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
303 address & 0xFFFFFFFFFFFFFFF0ull);
304 if (retval != ERROR_OK)
305 return retval;
306
307 return dap_queue_ap_write(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC),
308 value);
309 }
310
311 /**
312 * Synchronous write of a word to memory or a system register.
313 * As a side effect, this flushes any queued transactions.
314 *
315 * @param ap The MEM-AP to access.
316 * @param address Address to be written; it must be writable by
317 * the currently selected MEM-AP.
318 * @param value Word that will be written.
319 *
320 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
321 */
322 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
323 uint32_t value)
324 {
325 int retval = mem_ap_write_u32(ap, address, value);
326
327 if (retval != ERROR_OK)
328 return retval;
329
330 return dap_run(ap->dap);
331 }
332
333 /**
334 * Synchronous write of a block of memory, using a specific access size.
335 *
336 * @param ap The MEM-AP to access.
337 * @param buffer The data buffer to write. No particular alignment is assumed.
338 * @param size Which access size to use, in bytes. 1, 2 or 4.
339 * @param count The number of writes to do (in size units, not bytes).
340 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
341 * @param addrinc Whether the target address should be increased for each write or not. This
342 * should normally be true, except when writing to e.g. a FIFO.
343 * @return ERROR_OK on success, otherwise an error code.
344 */
345 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
346 target_addr_t address, bool addrinc)
347 {
348 struct adiv5_dap *dap = ap->dap;
349 size_t nbytes = size * count;
350 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
351 uint32_t csw_size;
352 target_addr_t addr_xor;
353 int retval = ERROR_OK;
354
355 /* TI BE-32 Quirks mode:
356 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
357 * size write address bytes written in order
358 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
359 * 2 TAR ^ 2 (val >> 8), (val)
360 * 1 TAR ^ 3 (val)
361 * For example, if you attempt to write a single byte to address 0, the processor
362 * will actually write a byte to address 3.
363 *
364 * To make writes of size < 4 work as expected, we xor a value with the address before
365 * setting the TAP, and we set the TAP after every transfer rather then relying on
366 * address increment. */
367
368 if (size == 4) {
369 csw_size = CSW_32BIT;
370 addr_xor = 0;
371 } else if (size == 2) {
372 csw_size = CSW_16BIT;
373 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
374 } else if (size == 1) {
375 csw_size = CSW_8BIT;
376 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
377 } else {
378 return ERROR_TARGET_UNALIGNED_ACCESS;
379 }
380
381 if (ap->unaligned_access_bad && (address % size != 0))
382 return ERROR_TARGET_UNALIGNED_ACCESS;
383
384 while (nbytes > 0) {
385 uint32_t this_size = size;
386
387 /* Select packed transfer if possible */
388 if (addrinc && ap->packed_transfers && nbytes >= 4
389 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
390 this_size = 4;
391 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
392 } else {
393 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
394 }
395
396 if (retval != ERROR_OK)
397 break;
398
399 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
400 if (retval != ERROR_OK)
401 return retval;
402
403 /* How many source bytes each transfer will consume, and their location in the DRW,
404 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
405 uint32_t outvalue = 0;
406 uint32_t drw_byte_idx = address;
407 if (dap->ti_be_32_quirks) {
408 switch (this_size) {
409 case 4:
410 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
411 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
412 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
413 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
414 break;
415 case 2:
416 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
417 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
418 break;
419 case 1:
420 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
421 break;
422 }
423 } else {
424 switch (this_size) {
425 case 4:
426 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
427 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
428 /* fallthrough */
429 case 2:
430 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
431 /* fallthrough */
432 case 1:
433 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
434 }
435 }
436
437 nbytes -= this_size;
438
439 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW(dap), outvalue);
440 if (retval != ERROR_OK)
441 break;
442
443 mem_ap_update_tar_cache(ap);
444 if (addrinc)
445 address += this_size;
446 }
447
448 /* REVISIT: Might want to have a queued version of this function that does not run. */
449 if (retval == ERROR_OK)
450 retval = dap_run(dap);
451
452 if (retval != ERROR_OK) {
453 target_addr_t tar;
454 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
455 LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
456 else
457 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
458 }
459
460 return retval;
461 }
462
463 /**
464 * Synchronous read of a block of memory, using a specific access size.
465 *
466 * @param ap The MEM-AP to access.
467 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
468 * @param size Which access size to use, in bytes. 1, 2 or 4.
469 * @param count The number of reads to do (in size units, not bytes).
470 * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
471 * @param addrinc Whether the target address should be increased after each read or not. This
472 * should normally be true, except when reading from e.g. a FIFO.
473 * @return ERROR_OK on success, otherwise an error code.
474 */
475 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
476 target_addr_t adr, bool addrinc)
477 {
478 struct adiv5_dap *dap = ap->dap;
479 size_t nbytes = size * count;
480 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
481 uint32_t csw_size;
482 target_addr_t address = adr;
483 int retval = ERROR_OK;
484
485 /* TI BE-32 Quirks mode:
486 * Reads on big-endian TMS570 behave strangely differently than writes.
487 * They read from the physical address requested, but with DRW byte-reversed.
488 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
489 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
490 * so avoid them. */
491
492 if (size == 4)
493 csw_size = CSW_32BIT;
494 else if (size == 2)
495 csw_size = CSW_16BIT;
496 else if (size == 1)
497 csw_size = CSW_8BIT;
498 else
499 return ERROR_TARGET_UNALIGNED_ACCESS;
500
501 if (ap->unaligned_access_bad && (adr % size != 0))
502 return ERROR_TARGET_UNALIGNED_ACCESS;
503
504 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
505 * over-allocation if packed transfers are going to be used, but determining the real need at
506 * this point would be messy. */
507 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
508 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
509 uint32_t *read_ptr = read_buf;
510 if (!read_buf) {
511 LOG_ERROR("Failed to allocate read buffer");
512 return ERROR_FAIL;
513 }
514
515 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
516 * useful bytes it contains, and their location in the word, depends on the type of transfer
517 * and alignment. */
518 while (nbytes > 0) {
519 uint32_t this_size = size;
520
521 /* Select packed transfer if possible */
522 if (addrinc && ap->packed_transfers && nbytes >= 4
523 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
524 this_size = 4;
525 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
526 } else {
527 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
528 }
529 if (retval != ERROR_OK)
530 break;
531
532 retval = mem_ap_setup_tar(ap, address);
533 if (retval != ERROR_OK)
534 break;
535
536 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW(dap), read_ptr++);
537 if (retval != ERROR_OK)
538 break;
539
540 nbytes -= this_size;
541 if (addrinc)
542 address += this_size;
543
544 mem_ap_update_tar_cache(ap);
545 }
546
547 if (retval == ERROR_OK)
548 retval = dap_run(dap);
549
550 /* Restore state */
551 address = adr;
552 nbytes = size * count;
553 read_ptr = read_buf;
554
555 /* If something failed, read TAR to find out how much data was successfully read, so we can
556 * at least give the caller what we have. */
557 if (retval != ERROR_OK) {
558 target_addr_t tar;
559 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
560 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
561 LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
562 if (nbytes > tar - address)
563 nbytes = tar - address;
564 } else {
565 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
566 nbytes = 0;
567 }
568 }
569
570 /* Replay loop to populate caller's buffer from the correct word and byte lane */
571 while (nbytes > 0) {
572 uint32_t this_size = size;
573
574 if (addrinc && ap->packed_transfers && nbytes >= 4
575 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
576 this_size = 4;
577 }
578
579 if (dap->ti_be_32_quirks) {
580 switch (this_size) {
581 case 4:
582 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
583 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
584 /* fallthrough */
585 case 2:
586 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
587 /* fallthrough */
588 case 1:
589 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
590 }
591 } else {
592 switch (this_size) {
593 case 4:
594 *buffer++ = *read_ptr >> 8 * (address++ & 3);
595 *buffer++ = *read_ptr >> 8 * (address++ & 3);
596 /* fallthrough */
597 case 2:
598 *buffer++ = *read_ptr >> 8 * (address++ & 3);
599 /* fallthrough */
600 case 1:
601 *buffer++ = *read_ptr >> 8 * (address++ & 3);
602 }
603 }
604
605 read_ptr++;
606 nbytes -= this_size;
607 }
608
609 free(read_buf);
610 return retval;
611 }
612
613 int mem_ap_read_buf(struct adiv5_ap *ap,
614 uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
615 {
616 return mem_ap_read(ap, buffer, size, count, address, true);
617 }
618
619 int mem_ap_write_buf(struct adiv5_ap *ap,
620 const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
621 {
622 return mem_ap_write(ap, buffer, size, count, address, true);
623 }
624
625 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
626 uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
627 {
628 return mem_ap_read(ap, buffer, size, count, address, false);
629 }
630
631 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
632 const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
633 {
634 return mem_ap_write(ap, buffer, size, count, address, false);
635 }
636
637 /*--------------------------------------------------------------------------*/
638
639
640 #define DAP_POWER_DOMAIN_TIMEOUT (10)
641
642 /*--------------------------------------------------------------------------*/
643
644 /**
645 * Invalidate cached DP select and cached TAR and CSW of all APs
646 */
647 void dap_invalidate_cache(struct adiv5_dap *dap)
648 {
649 dap->select = DP_SELECT_INVALID;
650 dap->last_read = NULL;
651
652 int i;
653 for (i = 0; i <= DP_APSEL_MAX; i++) {
654 /* force csw and tar write on the next mem-ap access */
655 dap->ap[i].tar_valid = false;
656 dap->ap[i].csw_value = 0;
657 }
658 }
659
660 /**
661 * Initialize a DAP. This sets up the power domains, prepares the DP
662 * for further use and activates overrun checking.
663 *
664 * @param dap The DAP being initialized.
665 */
666 int dap_dp_init(struct adiv5_dap *dap)
667 {
668 int retval;
669
670 LOG_DEBUG("%s", adiv5_dap_name(dap));
671
672 dap->do_reconnect = false;
673 dap_invalidate_cache(dap);
674
675 /*
676 * Early initialize dap->dp_ctrl_stat.
677 * In jtag mode only, if the following queue run (in dap_dp_poll_register)
678 * fails and sets the sticky error, it will trigger the clearing
679 * of the sticky. Without this initialization system and debug power
680 * would be disabled while clearing the sticky error bit.
681 */
682 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
683
684 /*
685 * This write operation clears the sticky error bit in jtag mode only and
686 * is ignored in swd mode. It also powers-up system and debug domains in
687 * both jtag and swd modes, if not done before.
688 */
689 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
690 if (retval != ERROR_OK)
691 return retval;
692
693 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
694 if (retval != ERROR_OK)
695 return retval;
696
697 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
698 if (retval != ERROR_OK)
699 return retval;
700
701 /* Check that we have debug power domains activated */
702 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
703 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
704 CDBGPWRUPACK, CDBGPWRUPACK,
705 DAP_POWER_DOMAIN_TIMEOUT);
706 if (retval != ERROR_OK)
707 return retval;
708
709 if (!dap->ignore_syspwrupack) {
710 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
711 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
712 CSYSPWRUPACK, CSYSPWRUPACK,
713 DAP_POWER_DOMAIN_TIMEOUT);
714 if (retval != ERROR_OK)
715 return retval;
716 }
717
718 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
719 if (retval != ERROR_OK)
720 return retval;
721
722 /* With debug power on we can activate OVERRUN checking */
723 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
724 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
725 if (retval != ERROR_OK)
726 return retval;
727 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
728 if (retval != ERROR_OK)
729 return retval;
730
731 retval = dap_run(dap);
732 if (retval != ERROR_OK)
733 return retval;
734
735 return retval;
736 }
737
738 /**
739 * Initialize a DAP or do reconnect if DAP is not accessible.
740 *
741 * @param dap The DAP being initialized.
742 */
743 int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
744 {
745 LOG_DEBUG("%s", adiv5_dap_name(dap));
746
747 /*
748 * Early initialize dap->dp_ctrl_stat.
749 * In jtag mode only, if the following atomic reads fail and set the
750 * sticky error, it will trigger the clearing of the sticky. Without this
751 * initialization system and debug power would be disabled while clearing
752 * the sticky error bit.
753 */
754 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
755
756 dap->do_reconnect = false;
757
758 dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
759 if (dap->do_reconnect) {
760 /* dap connect calls dap_dp_init() after transport dependent initialization */
761 return dap->ops->connect(dap);
762 } else {
763 return dap_dp_init(dap);
764 }
765 }
766
767 /**
768 * Initialize a DAP. This sets up the power domains, prepares the DP
769 * for further use, and arranges to use AP #0 for all AP operations
770 * until dap_ap-select() changes that policy.
771 *
772 * @param ap The MEM-AP being initialized.
773 */
774 int mem_ap_init(struct adiv5_ap *ap)
775 {
776 /* check that we support packed transfers */
777 uint32_t csw, cfg;
778 int retval;
779 struct adiv5_dap *dap = ap->dap;
780
781 /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
782 /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
783 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &cfg);
784 if (retval != ERROR_OK)
785 return retval;
786
787 retval = dap_run(dap);
788 if (retval != ERROR_OK)
789 return retval;
790
791 ap->cfg_reg = cfg;
792 ap->tar_valid = false;
793 ap->csw_value = 0; /* force csw and tar write */
794 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
795 if (retval != ERROR_OK)
796 return retval;
797
798 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW(dap), &csw);
799 if (retval != ERROR_OK)
800 return retval;
801
802 retval = dap_run(dap);
803 if (retval != ERROR_OK)
804 return retval;
805
806 if (csw & CSW_ADDRINC_PACKED)
807 ap->packed_transfers = true;
808 else
809 ap->packed_transfers = false;
810
811 /* Packed transfers on TI BE-32 processors do not work correctly in
812 * many cases. */
813 if (dap->ti_be_32_quirks)
814 ap->packed_transfers = false;
815
816 LOG_DEBUG("MEM_AP Packed Transfers: %s",
817 ap->packed_transfers ? "enabled" : "disabled");
818
819 /* The ARM ADI spec leaves implementation-defined whether unaligned
820 * memory accesses work, only work partially, or cause a sticky error.
821 * On TI BE-32 processors, reads seem to return garbage in some bytes
822 * and unaligned writes seem to cause a sticky error.
823 * TODO: it would be nice to have a way to detect whether unaligned
824 * operations are supported on other processors. */
825 ap->unaligned_access_bad = dap->ti_be_32_quirks;
826
827 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
828 !!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE));
829
830 return ERROR_OK;
831 }
832
833 /**
834 * Put the debug link into SWD mode, if the target supports it.
835 * The link's initial mode may be either JTAG (for example,
836 * with SWJ-DP after reset) or SWD.
837 *
838 * Note that targets using the JTAG-DP do not support SWD, and that
839 * some targets which could otherwise support it may have been
840 * configured to disable SWD signaling
841 *
842 * @param dap The DAP used
843 * @return ERROR_OK or else a fault code.
844 */
845 int dap_to_swd(struct adiv5_dap *dap)
846 {
847 LOG_DEBUG("Enter SWD mode");
848
849 return dap_send_sequence(dap, JTAG_TO_SWD);
850 }
851
852 /**
853 * Put the debug link into JTAG mode, if the target supports it.
854 * The link's initial mode may be either SWD or JTAG.
855 *
856 * Note that targets implemented with SW-DP do not support JTAG, and
857 * that some targets which could otherwise support it may have been
858 * configured to disable JTAG signaling
859 *
860 * @param dap The DAP used
861 * @return ERROR_OK or else a fault code.
862 */
863 int dap_to_jtag(struct adiv5_dap *dap)
864 {
865 LOG_DEBUG("Enter JTAG mode");
866
867 return dap_send_sequence(dap, SWD_TO_JTAG);
868 }
869
870 /* CID interpretation -- see ARM IHI 0029E table B2-7
871 * and ARM IHI 0031E table D1-2.
872 *
873 * From 2009/11/25 commit 21378f58b604:
874 * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
875 * Let's keep it as is, for the time being
876 */
877 static const char *class_description[16] = {
878 [0x0] = "Generic verification component",
879 [0x1] = "ROM table",
880 [0x2] = "Reserved",
881 [0x3] = "Reserved",
882 [0x4] = "Reserved",
883 [0x5] = "Reserved",
884 [0x6] = "Reserved",
885 [0x7] = "Reserved",
886 [0x8] = "Reserved",
887 [0x9] = "CoreSight component",
888 [0xA] = "Reserved",
889 [0xB] = "Peripheral Test Block",
890 [0xC] = "Reserved",
891 [0xD] = "OptimoDE DESS", /* see above */
892 [0xE] = "Generic IP component",
893 [0xF] = "CoreLink, PrimeCell or System component",
894 };
895
896 #define ARCH_ID(architect, archid) ( \
897 (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
898 (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
899 )
900
901 static const struct {
902 uint32_t arch_id;
903 const char *description;
904 } class0x9_devarch[] = {
905 /* keep same unsorted order as in ARM IHI0029E */
906 { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
907 { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
908 { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
909 { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
910 { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
911 { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
912 { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
913 { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
914 { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
915 { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
916 { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
917 { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
918 { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
919 { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
920 { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
921 { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
922 { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
923 { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
924 { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
925 { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
926 { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
927 { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
928 };
929
930 #define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
931 #define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
932
933 static const char *class0x9_devarch_description(uint32_t devarch)
934 {
935 if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
936 return "not present";
937
938 for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++)
939 if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id)
940 return class0x9_devarch[i].description;
941
942 return "unknown";
943 }
944
945 static const struct {
946 enum ap_type type;
947 const char *description;
948 } ap_types[] = {
949 { AP_TYPE_JTAG_AP, "JTAG-AP" },
950 { AP_TYPE_COM_AP, "COM-AP" },
951 { AP_TYPE_AHB3_AP, "MEM-AP AHB3" },
952 { AP_TYPE_APB_AP, "MEM-AP APB2 or APB3" },
953 { AP_TYPE_AXI_AP, "MEM-AP AXI3 or AXI4" },
954 { AP_TYPE_AHB5_AP, "MEM-AP AHB5" },
955 { AP_TYPE_APB4_AP, "MEM-AP APB4" },
956 { AP_TYPE_AXI5_AP, "MEM-AP AXI5" },
957 { AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
958 };
959
960 static const char *ap_type_to_description(enum ap_type type)
961 {
962 for (unsigned int i = 0; i < ARRAY_SIZE(ap_types); i++)
963 if (type == ap_types[i].type)
964 return ap_types[i].description;
965
966 return "Unknown";
967 }
968
969 bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num)
970 {
971 if (!dap)
972 return false;
973
974 /* no autodetection, by now, so uninitialized is equivalent to ADIv5 for
975 * backward compatibility */
976 if (!is_adiv6(dap)) {
977 if (ap_num > DP_APSEL_MAX)
978 return false;
979 return true;
980 }
981
982 if (is_adiv6(dap)) {
983 if (ap_num & 0x0fffULL)
984 return false;
985 if (dap->asize != 0)
986 if (ap_num & ((~0ULL) << dap->asize))
987 return false;
988 return true;
989 }
990
991 return false;
992 }
993
994 /*
995 * This function checks the ID for each access port to find the requested Access Port type
996 * It also calls dap_get_ap() to increment the AP refcount
997 */
998 int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
999 {
1000 if (is_adiv6(dap)) {
1001 /* TODO: scan the ROM table and detect the AP available */
1002 LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
1003 return ERROR_FAIL;
1004 }
1005
1006 /* Maximum AP number is 255 since the SELECT register is 8 bits */
1007 for (unsigned int ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
1008 struct adiv5_ap *ap = dap_get_ap(dap, ap_num);
1009 if (!ap)
1010 continue;
1011
1012 /* read the IDR register of the Access Port */
1013 uint32_t id_val = 0;
1014
1015 int retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), &id_val);
1016 if (retval != ERROR_OK) {
1017 dap_put_ap(ap);
1018 return retval;
1019 }
1020
1021 retval = dap_run(dap);
1022
1023 /* Reading register for a non-existent AP should not cause an error,
1024 * but just to be sure, try to continue searching if an error does happen.
1025 */
1026 if (retval == ERROR_OK && (id_val & AP_TYPE_MASK) == type_to_find) {
1027 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
1028 ap_type_to_description(type_to_find),
1029 ap_num, id_val);
1030
1031 *ap_out = ap;
1032 return ERROR_OK;
1033 }
1034 dap_put_ap(ap);
1035 }
1036
1037 LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
1038 return ERROR_FAIL;
1039 }
1040
1041 static inline bool is_ap_in_use(struct adiv5_ap *ap)
1042 {
1043 return ap->refcount > 0 || ap->config_ap_never_release;
1044 }
1045
1046 static struct adiv5_ap *_dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
1047 {
1048 if (!is_ap_num_valid(dap, ap_num)) {
1049 LOG_ERROR("Invalid AP#0x%" PRIx64, ap_num);
1050 return NULL;
1051 }
1052 if (is_adiv6(dap)) {
1053 for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
1054 struct adiv5_ap *ap = &dap->ap[i];
1055 if (is_ap_in_use(ap) && ap->ap_num == ap_num) {
1056 ++ap->refcount;
1057 return ap;
1058 }
1059 }
1060 for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
1061 struct adiv5_ap *ap = &dap->ap[i];
1062 if (!is_ap_in_use(ap)) {
1063 ap->ap_num = ap_num;
1064 ++ap->refcount;
1065 return ap;
1066 }
1067 }
1068 LOG_ERROR("No more AP available!");
1069 return NULL;
1070 }
1071
1072 /* ADIv5 */
1073 struct adiv5_ap *ap = &dap->ap[ap_num];
1074 ap->ap_num = ap_num;
1075 ++ap->refcount;
1076 return ap;
1077 }
1078
1079 /* Return AP with specified ap_num. Increment AP refcount */
1080 struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
1081 {
1082 struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
1083 if (ap)
1084 LOG_DEBUG("refcount AP#0x%" PRIx64 " get %u", ap_num, ap->refcount);
1085 return ap;
1086 }
1087
1088 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
1089 struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num)
1090 {
1091 struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
1092 if (ap) {
1093 ap->config_ap_never_release = true;
1094 LOG_DEBUG("refcount AP#0x%" PRIx64 " get_config %u", ap_num, ap->refcount);
1095 }
1096 return ap;
1097 }
1098
1099 /* Decrement AP refcount and release the AP when refcount reaches zero */
1100 int dap_put_ap(struct adiv5_ap *ap)
1101 {
1102 if (ap->refcount == 0) {
1103 LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " put underflow", ap->ap_num);
1104 return ERROR_FAIL;
1105 }
1106
1107 --ap->refcount;
1108
1109 LOG_DEBUG("refcount AP#0x%" PRIx64 " put %u", ap->ap_num, ap->refcount);
1110 if (!is_ap_in_use(ap)) {
1111 /* defaults from dap_instance_init() */
1112 ap->ap_num = DP_APSEL_INVALID;
1113 ap->memaccess_tck = 255;
1114 ap->tar_autoincr_block = (1 << 10);
1115 ap->csw_default = CSW_AHB_DEFAULT;
1116 ap->cfg_reg = MEM_AP_REG_CFG_INVALID;
1117 }
1118 return ERROR_OK;
1119 }
1120
1121 static int dap_get_debugbase(struct adiv5_ap *ap,
1122 target_addr_t *dbgbase, uint32_t *apid)
1123 {
1124 struct adiv5_dap *dap = ap->dap;
1125 int retval;
1126 uint32_t baseptr_upper, baseptr_lower;
1127
1128 if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
1129 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &ap->cfg_reg);
1130 if (retval != ERROR_OK)
1131 return retval;
1132 }
1133 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE(dap), &baseptr_lower);
1134 if (retval != ERROR_OK)
1135 return retval;
1136 retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), apid);
1137 if (retval != ERROR_OK)
1138 return retval;
1139 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1140 if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
1141 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64(dap), &baseptr_upper);
1142 if (retval != ERROR_OK)
1143 return retval;
1144 }
1145
1146 retval = dap_run(dap);
1147 if (retval != ERROR_OK)
1148 return retval;
1149
1150 if (!is_64bit_ap(ap))
1151 baseptr_upper = 0;
1152 *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
1153
1154 return ERROR_OK;
1155 }
1156
1157 int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, uint64_t *baseptr)
1158 {
1159 uint32_t baseptr_lower, baseptr_upper = 0;
1160 int retval;
1161
1162 if (dap->asize > 32) {
1163 retval = dap_queue_dp_read(dap, DP_BASEPTR1, &baseptr_upper);
1164 if (retval != ERROR_OK)
1165 return retval;
1166 }
1167
1168 retval = dap_dp_read_atomic(dap, DP_BASEPTR0, &baseptr_lower);
1169 if (retval != ERROR_OK)
1170 return retval;
1171
1172 if ((baseptr_lower & DP_BASEPTR0_VALID) != DP_BASEPTR0_VALID) {
1173 command_print(cmd, "System root table not present");
1174 return ERROR_FAIL;
1175 }
1176
1177 baseptr_lower &= ~0x0fff;
1178 *baseptr = (((uint64_t)baseptr_upper) << 32) | baseptr_lower;
1179
1180 return ERROR_OK;
1181 }
1182
1183 /** Holds registers and coordinates of a CoreSight component */
1184 struct cs_component_vals {
1185 struct adiv5_ap *ap;
1186 target_addr_t component_base;
1187 uint64_t pid;
1188 uint32_t cid;
1189 uint32_t devarch;
1190 uint32_t devid;
1191 uint32_t devtype_memtype;
1192 };
1193
1194 /**
1195 * Read the CoreSight registers needed during ROM Table Parsing (RTP).
1196 *
1197 * @param ap Pointer to AP containing the component.
1198 * @param component_base On MEM-AP access method, base address of the component.
1199 * @param v Pointer to the struct holding the value of registers.
1200 *
1201 * @return ERROR_OK on success, else a fault code.
1202 */
1203 static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
1204 struct cs_component_vals *v)
1205 {
1206 assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
1207 assert(ap && v);
1208
1209 uint32_t cid0, cid1, cid2, cid3;
1210 uint32_t pid0, pid1, pid2, pid3, pid4;
1211 int retval = ERROR_OK;
1212
1213 v->ap = ap;
1214 v->component_base = component_base;
1215
1216 /* sort by offset to gain speed */
1217
1218 /*
1219 * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices
1220 * only, but are at offset above 0xf00, so can be read on any device
1221 * without triggering error. Read them for eventual use on Class 0x9.
1222 */
1223 if (retval == ERROR_OK)
1224 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVARCH, &v->devarch);
1225
1226 if (retval == ERROR_OK)
1227 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVID, &v->devid);
1228
1229 /* Same address as ARM_CS_C1_MEMTYPE */
1230 if (retval == ERROR_OK)
1231 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
1232
1233 if (retval == ERROR_OK)
1234 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
1235
1236 if (retval == ERROR_OK)
1237 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
1238 if (retval == ERROR_OK)
1239 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
1240 if (retval == ERROR_OK)
1241 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
1242 if (retval == ERROR_OK)
1243 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
1244
1245 if (retval == ERROR_OK)
1246 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
1247 if (retval == ERROR_OK)
1248 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
1249 if (retval == ERROR_OK)
1250 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
1251 if (retval == ERROR_OK)
1252 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
1253
1254 if (retval == ERROR_OK)
1255 retval = dap_run(ap->dap);
1256 if (retval != ERROR_OK) {
1257 LOG_DEBUG("Failed read CoreSight registers");
1258 return retval;
1259 }
1260
1261 v->cid = (cid3 & 0xff) << 24
1262 | (cid2 & 0xff) << 16
1263 | (cid1 & 0xff) << 8
1264 | (cid0 & 0xff);
1265 v->pid = (uint64_t)(pid4 & 0xff) << 32
1266 | (pid3 & 0xff) << 24
1267 | (pid2 & 0xff) << 16
1268 | (pid1 & 0xff) << 8
1269 | (pid0 & 0xff);
1270
1271 return ERROR_OK;
1272 }
1273
1274 /* Part number interpretations are from Cortex
1275 * core specs, the CoreSight components TRM
1276 * (ARM DDI 0314H), CoreSight System Design
1277 * Guide (ARM DGI 0012D) and ETM specs; also
1278 * from chip observation (e.g. TI SDTI).
1279 */
1280
1281 static const struct dap_part_nums {
1282 uint16_t designer_id;
1283 uint16_t part_num;
1284 const char *type;
1285 const char *full;
1286 } dap_part_nums[] = {
1287 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1288 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1289 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1290 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1291 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1292 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1293 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1294 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1295 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1296 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1297 { ARM_ID, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
1298 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1299 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1300 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1301 { ARM_ID, 0x492, "Cortex-R52 GICD", "(Distributor)", },
1302 { ARM_ID, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
1303 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1304 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1305 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1306 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1307 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1308 { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1309 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1310 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1311 { ARM_ID, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
1312 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1313 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1314 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1315 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1316 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1317 { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1318 { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
1319 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1320 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1321 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1322 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1323 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1324 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1325 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1326 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1327 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1328 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1329 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1330 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1331 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1332 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1333 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1334 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1335 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1336 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1337 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1338 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1339 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1340 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1341 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1342 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1343 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1344 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1345 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1346 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1347 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1348 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1349 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1350 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1351 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1352 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1353 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1354 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1355 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1356 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1357 { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1358 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1359 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1360 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1361 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1362 { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1363 { ARM_ID, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
1364 { ARM_ID, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
1365 { ARM_ID, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
1366 { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
1367 { ARM_ID, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
1368 { ARM_ID, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
1369 { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
1370 { ARM_ID, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
1371 { ARM_ID, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
1372 { ARM_ID, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
1373 { ARM_ID, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
1374 { ARM_ID, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
1375 { ARM_ID, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
1376 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1377 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1378 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1379 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1380 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1381 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1382 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1383 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1384 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1385 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1386 { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1387 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1388 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1389 { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
1390 { ARM_ID, 0xd0c, "Neoverse N1", "(Debug Unit)", },
1391 { ARM_ID, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
1392 { ARM_ID, 0xd49, "Neoverse N2", "(Debug Unit)", },
1393 { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1394 { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1395 { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
1396 { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1397 { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1398 { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1399 { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1400 { 0x065, 0x000, "SHARC+/Blackfin+", "", },
1401 { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1402 { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
1403 { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
1404 { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
1405 { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
1406 { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1407 { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1408 { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1409 { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
1410 { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1411 };
1412
1413 static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
1414 {
1415 static const struct dap_part_nums unknown = {
1416 .type = "Unrecognized",
1417 .full = "",
1418 };
1419
1420 for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
1421 if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
1422 return &dap_part_nums[i];
1423
1424 return &unknown;
1425 }
1426
1427 static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
1428 {
1429 const char *major = "Reserved", *subtype = "Reserved";
1430 const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
1431 const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
1432 switch (devtype_major) {
1433 case 0:
1434 major = "Miscellaneous";
1435 switch (minor) {
1436 case 0:
1437 subtype = "other";
1438 break;
1439 case 4:
1440 subtype = "Validation component";
1441 break;
1442 }
1443 break;
1444 case 1:
1445 major = "Trace Sink";
1446 switch (minor) {
1447 case 0:
1448 subtype = "other";
1449 break;
1450 case 1:
1451 subtype = "Port";
1452 break;
1453 case 2:
1454 subtype = "Buffer";
1455 break;
1456 case 3:
1457 subtype = "Router";
1458 break;
1459 }
1460 break;
1461 case 2:
1462 major = "Trace Link";
1463 switch (minor) {
1464 case 0:
1465 subtype = "other";
1466 break;
1467 case 1:
1468 subtype = "Funnel, router";
1469 break;
1470 case 2:
1471 subtype = "Filter";
1472 break;
1473 case 3:
1474 subtype = "FIFO, buffer";
1475 break;
1476 }
1477 break;
1478 case 3:
1479 major = "Trace Source";
1480 switch (minor) {
1481 case 0:
1482 subtype = "other";
1483 break;
1484 case 1:
1485 subtype = "Processor";
1486 break;
1487 case 2:
1488 subtype = "DSP";
1489 break;
1490 case 3:
1491 subtype = "Engine/Coprocessor";
1492 break;
1493 case 4:
1494 subtype = "Bus";
1495 break;
1496 case 6:
1497 subtype = "Software";
1498 break;
1499 }
1500 break;
1501 case 4:
1502 major = "Debug Control";
1503 switch (minor) {
1504 case 0:
1505 subtype = "other";
1506 break;
1507 case 1:
1508 subtype = "Trigger Matrix";
1509 break;
1510 case 2:
1511 subtype = "Debug Auth";
1512 break;
1513 case 3:
1514 subtype = "Power Requestor";
1515 break;
1516 }
1517 break;
1518 case 5:
1519 major = "Debug Logic";
1520 switch (minor) {
1521 case 0:
1522 subtype = "other";
1523 break;
1524 case 1:
1525 subtype = "Processor";
1526 break;
1527 case 2:
1528 subtype = "DSP";
1529 break;
1530 case 3:
1531 subtype = "Engine/Coprocessor";
1532 break;
1533 case 4:
1534 subtype = "Bus";
1535 break;
1536 case 5:
1537 subtype = "Memory";
1538 break;
1539 }
1540 break;
1541 case 6:
1542 major = "Performance Monitor";
1543 switch (minor) {
1544 case 0:
1545 subtype = "other";
1546 break;
1547 case 1:
1548 subtype = "Processor";
1549 break;
1550 case 2:
1551 subtype = "DSP";
1552 break;
1553 case 3:
1554 subtype = "Engine/Coprocessor";
1555 break;
1556 case 4:
1557 subtype = "Bus";
1558 break;
1559 case 5:
1560 subtype = "Memory";
1561 break;
1562 }
1563 break;
1564 }
1565 command_print(cmd, "\t\tType is 0x%02x, %s, %s",
1566 devtype & ARM_CS_C9_DEVTYPE_MASK,
1567 major, subtype);
1568 return ERROR_OK;
1569 }
1570
1571 /**
1572 * Actions/operations to be executed while parsing ROM tables.
1573 */
1574 struct rtp_ops {
1575 /**
1576 * Executed at the start of a new MEM-AP, typically to print the MEM-AP header.
1577 * @param retval Error encountered while reading AP.
1578 * @param ap Pointer to AP.
1579 * @param dbgbase Value of MEM-AP Debug Base Address register.
1580 * @param apid Value of MEM-AP IDR Identification Register.
1581 * @param priv Pointer to private data.
1582 * @return ERROR_OK on success, else a fault code.
1583 */
1584 int (*mem_ap_header)(int retval, struct adiv5_ap *ap, uint64_t dbgbase,
1585 uint32_t apid, void *priv);
1586 /**
1587 * Executed when a CoreSight component is parsed, typically to print
1588 * information on the component.
1589 * @param retval Error encountered while reading component's registers.
1590 * @param v Pointer to a container of the component's registers.
1591 * @param depth The current depth level of ROM table.
1592 * @param priv Pointer to private data.
1593 * @return ERROR_OK on success, else a fault code.
1594 */
1595 int (*cs_component)(int retval, struct cs_component_vals *v, int depth, void *priv);
1596 /**
1597 * Executed for each entry of a ROM table, typically to print the entry
1598 * and information about validity or end-of-table mark.
1599 * @param retval Error encountered while reading the ROM table entry.
1600 * @param depth The current depth level of ROM table.
1601 * @param offset The offset of the entry in the ROM table.
1602 * @param romentry The value of the ROM table entry.
1603 * @param priv Pointer to private data.
1604 * @return ERROR_OK on success, else a fault code.
1605 */
1606 int (*rom_table_entry)(int retval, int depth, unsigned int offset, uint64_t romentry,
1607 void *priv);
1608 /**
1609 * Private data
1610 */
1611 void *priv;
1612 };
1613
1614 /**
1615 * Wrapper around struct rtp_ops::mem_ap_header.
1616 * Input parameter @a retval is propagated.
1617 */
1618 static int rtp_ops_mem_ap_header(const struct rtp_ops *ops,
1619 int retval, struct adiv5_ap *ap, uint64_t dbgbase, uint32_t apid)
1620 {
1621 if (!ops->mem_ap_header)
1622 return retval;
1623
1624 int retval1 = ops->mem_ap_header(retval, ap, dbgbase, apid, ops->priv);
1625 if (retval != ERROR_OK)
1626 return retval;
1627 return retval1;
1628 }
1629
1630 /**
1631 * Wrapper around struct rtp_ops::cs_component.
1632 * Input parameter @a retval is propagated.
1633 */
1634 static int rtp_ops_cs_component(const struct rtp_ops *ops,
1635 int retval, struct cs_component_vals *v, int depth)
1636 {
1637 if (!ops->cs_component)
1638 return retval;
1639
1640 int retval1 = ops->cs_component(retval, v, depth, ops->priv);
1641 if (retval != ERROR_OK)
1642 return retval;
1643 return retval1;
1644 }
1645
1646 /**
1647 * Wrapper around struct rtp_ops::rom_table_entry.
1648 * Input parameter @a retval is propagated.
1649 */
1650 static int rtp_ops_rom_table_entry(const struct rtp_ops *ops,
1651 int retval, int depth, unsigned int offset, uint64_t romentry)
1652 {
1653 if (!ops->rom_table_entry)
1654 return retval;
1655
1656 int retval1 = ops->rom_table_entry(retval, depth, offset, romentry, ops->priv);
1657 if (retval != ERROR_OK)
1658 return retval;
1659 return retval1;
1660 }
1661
1662 /* Broken ROM tables can have circular references. Stop after a while */
1663 #define ROM_TABLE_MAX_DEPTH (16)
1664
1665 /**
1666 * Value used only during lookup of a CoreSight component in ROM table.
1667 * Return CORESIGHT_COMPONENT_FOUND when component is found.
1668 * Return ERROR_OK when component is not found yet.
1669 * Return any other ERROR_* in case of error.
1670 */
1671 #define CORESIGHT_COMPONENT_FOUND (1)
1672
1673 static int rtp_cs_component(const struct rtp_ops *ops,
1674 struct adiv5_ap *ap, target_addr_t dbgbase, int depth);
1675
1676 static int rtp_rom_loop(const struct rtp_ops *ops,
1677 struct adiv5_ap *ap, target_addr_t base_address, int depth,
1678 unsigned int width, unsigned int max_entries)
1679 {
1680 assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1681
1682 unsigned int offset = 0;
1683 while (max_entries--) {
1684 uint64_t romentry;
1685 uint32_t romentry_low, romentry_high;
1686 target_addr_t component_base;
1687 unsigned int saved_offset = offset;
1688
1689 int retval = mem_ap_read_u32(ap, base_address + offset, &romentry_low);
1690 offset += 4;
1691 if (retval == ERROR_OK && width == 64) {
1692 retval = mem_ap_read_u32(ap, base_address + offset, &romentry_high);
1693 offset += 4;
1694 }
1695 if (retval == ERROR_OK)
1696 retval = dap_run(ap->dap);
1697 if (retval != ERROR_OK) {
1698 LOG_DEBUG("Failed read ROM table entry");
1699 return retval;
1700 }
1701
1702 if (width == 64) {
1703 romentry = (((uint64_t)romentry_high) << 32) | romentry_low;
1704 component_base = base_address +
1705 ((((uint64_t)romentry_high) << 32) | (romentry_low & ARM_CS_ROMENTRY_OFFSET_MASK));
1706 } else {
1707 romentry = romentry_low;
1708 /* "romentry" is signed */
1709 component_base = base_address + (int32_t)(romentry_low & ARM_CS_ROMENTRY_OFFSET_MASK);
1710 if (!is_64bit_ap(ap))
1711 component_base = (uint32_t)component_base;
1712 }
1713 retval = rtp_ops_rom_table_entry(ops, retval, depth, saved_offset, romentry);
1714 if (retval != ERROR_OK)
1715 return retval;
1716
1717 if (romentry == 0) {
1718 /* End of ROM table */
1719 break;
1720 }
1721
1722 if (!(romentry & ARM_CS_ROMENTRY_PRESENT))
1723 continue;
1724
1725 /* Recurse */
1726 retval = rtp_cs_component(ops, ap, component_base, depth + 1);
1727 if (retval == CORESIGHT_COMPONENT_FOUND)
1728 return CORESIGHT_COMPONENT_FOUND;
1729 if (retval != ERROR_OK) {
1730 /* TODO: do we need to send an ABORT before continuing? */
1731 LOG_DEBUG("Ignore error parsing CoreSight component");
1732 continue;
1733 }
1734 }
1735
1736 return ERROR_OK;
1737 }
1738
1739 static int rtp_cs_component(const struct rtp_ops *ops,
1740 struct adiv5_ap *ap, target_addr_t base_address, int depth)
1741 {
1742 struct cs_component_vals v;
1743 int retval;
1744
1745 assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1746
1747 if (depth > ROM_TABLE_MAX_DEPTH)
1748 retval = ERROR_FAIL;
1749 else
1750 retval = rtp_read_cs_regs(ap, base_address, &v);
1751
1752 retval = rtp_ops_cs_component(ops, retval, &v, depth);
1753 if (retval == CORESIGHT_COMPONENT_FOUND)
1754 return CORESIGHT_COMPONENT_FOUND;
1755 if (retval != ERROR_OK)
1756 return ERROR_OK; /* Don't abort recursion */
1757
1758 if (!is_valid_arm_cs_cidr(v.cid))
1759 return ERROR_OK; /* Don't abort recursion */
1760
1761 const unsigned int class = ARM_CS_CIDR_CLASS(v.cid);
1762
1763 if (class == ARM_CS_CLASS_0X1_ROM_TABLE)
1764 return rtp_rom_loop(ops, ap, base_address, depth, 32, 960);
1765
1766 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
1767 if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
1768 return ERROR_OK;
1769
1770 /* quit if not ROM table */
1771 if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
1772 return ERROR_OK;
1773
1774 if ((v.devid & ARM_CS_C9_DEVID_FORMAT_MASK) == ARM_CS_C9_DEVID_FORMAT_64BIT)
1775 return rtp_rom_loop(ops, ap, base_address, depth, 64, 256);
1776 else
1777 return rtp_rom_loop(ops, ap, base_address, depth, 32, 512);
1778 }
1779
1780 /* Class other than 0x1 and 0x9 */
1781 return ERROR_OK;
1782 }
1783
1784 static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap)
1785 {
1786 int retval;
1787 uint32_t apid;
1788 target_addr_t dbgbase, invalid_entry;
1789
1790 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1791 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1792 if (retval != ERROR_OK)
1793 return retval;
1794 retval = rtp_ops_mem_ap_header(ops, retval, ap, dbgbase, apid);
1795 if (retval != ERROR_OK)
1796 return retval;
1797
1798 if (apid == 0)
1799 return ERROR_FAIL;
1800
1801 /* NOTE: a MEM-AP may have a single CoreSight component that's
1802 * not a ROM table ... or have no such components at all.
1803 */
1804 const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
1805
1806 if (class == AP_REG_IDR_CLASS_MEM_AP) {
1807 if (is_64bit_ap(ap))
1808 invalid_entry = 0xFFFFFFFFFFFFFFFFull;
1809 else
1810 invalid_entry = 0xFFFFFFFFul;
1811
1812 if (dbgbase != invalid_entry && (dbgbase & 0x3) != 0x2) {
1813 retval = rtp_cs_component(ops, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0);
1814 if (retval == CORESIGHT_COMPONENT_FOUND)
1815 return CORESIGHT_COMPONENT_FOUND;
1816 }
1817 }
1818
1819 return ERROR_OK;
1820 }
1821
1822 /* Actions for command "dap info" */
1823
1824 static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
1825 target_addr_t dbgbase, uint32_t apid, void *priv)
1826 {
1827 struct command_invocation *cmd = priv;
1828 target_addr_t invalid_entry;
1829
1830 if (retval != ERROR_OK) {
1831 command_print(cmd, "\t\tCan't read MEM-AP, the corresponding core might be turned off");
1832 return retval;
1833 }
1834
1835 command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
1836 if (apid == 0) {
1837 command_print(cmd, "No AP found at this AP#0x%" PRIx64, ap->ap_num);
1838 return ERROR_FAIL;
1839 }
1840
1841 command_print(cmd, "\tType is %s", ap_type_to_description(apid & AP_TYPE_MASK));
1842
1843 /* NOTE: a MEM-AP may have a single CoreSight component that's
1844 * not a ROM table ... or have no such components at all.
1845 */
1846 const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
1847
1848 if (class == AP_REG_IDR_CLASS_MEM_AP) {
1849 if (is_64bit_ap(ap))
1850 invalid_entry = 0xFFFFFFFFFFFFFFFFull;
1851 else
1852 invalid_entry = 0xFFFFFFFFul;
1853
1854 command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase);
1855
1856 if (dbgbase == invalid_entry || (dbgbase & 0x3) == 0x2) {
1857 command_print(cmd, "\tNo ROM table present");
1858 } else {
1859 if (dbgbase & 0x01)
1860 command_print(cmd, "\tValid ROM table present");
1861 else
1862 command_print(cmd, "\tROM table in legacy format");
1863 }
1864 }
1865
1866 return ERROR_OK;
1867 }
1868
1869 static int dap_info_cs_component(int retval, struct cs_component_vals *v, int depth, void *priv)
1870 {
1871 struct command_invocation *cmd = priv;
1872
1873 if (depth > ROM_TABLE_MAX_DEPTH) {
1874 command_print(cmd, "\tTables too deep");
1875 return ERROR_FAIL;
1876 }
1877
1878 command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
1879
1880 if (retval != ERROR_OK) {
1881 command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
1882 return retval;
1883 }
1884
1885 if (!is_valid_arm_cs_cidr(v->cid)) {
1886 command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, v->cid);
1887 return ERROR_OK; /* Don't abort recursion */
1888 }
1889
1890 /* component may take multiple 4K pages */
1891 uint32_t size = ARM_CS_PIDR_SIZE(v->pid);
1892 if (size > 0)
1893 command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, v->component_base - 0x1000 * size);
1894
1895 command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, v->pid);
1896
1897 const unsigned int part_num = ARM_CS_PIDR_PART(v->pid);
1898 unsigned int designer_id = ARM_CS_PIDR_DESIGNER(v->pid);
1899
1900 if (v->pid & ARM_CS_PIDR_JEDEC) {
1901 /* JEP106 code */
1902 command_print(cmd, "\t\tDesigner is 0x%03x, %s",
1903 designer_id, jep106_manufacturer(designer_id));
1904 } else {
1905 /* Legacy ASCII ID, clear invalid bits */
1906 designer_id &= 0x7f;
1907 command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s",
1908 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1909 }
1910
1911 const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num);
1912 command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full);
1913
1914 const unsigned int class = ARM_CS_CIDR_CLASS(v->cid);
1915 command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]);
1916
1917 if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
1918 if (v->devtype_memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
1919 command_print(cmd, "\t\tMEMTYPE system memory present on bus");
1920 else
1921 command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1922 return ERROR_OK;
1923 }
1924
1925 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
1926 dap_devtype_display(cmd, v->devtype_memtype);
1927
1928 /* REVISIT also show ARM_CS_C9_DEVID */
1929
1930 if ((v->devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
1931 return ERROR_OK;
1932
1933 unsigned int architect_id = ARM_CS_C9_DEVARCH_ARCHITECT(v->devarch);
1934 unsigned int revision = ARM_CS_C9_DEVARCH_REVISION(v->devarch);
1935 command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", v->devarch,
1936 jep106_manufacturer(architect_id), class0x9_devarch_description(v->devarch),
1937 revision);
1938
1939 if ((v->devarch & DEVARCH_ID_MASK) == DEVARCH_ROM_C_0X9) {
1940 command_print(cmd, "\t\tType is ROM table");
1941
1942 if (v->devid & ARM_CS_C9_DEVID_SYSMEM_MASK)
1943 command_print(cmd, "\t\tMEMTYPE system memory present on bus");
1944 else
1945 command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1946 }
1947 return ERROR_OK;
1948 }
1949
1950 /* Class other than 0x1 and 0x9 */
1951 return ERROR_OK;
1952 }
1953
1954 static int dap_info_rom_table_entry(int retval, int depth,
1955 unsigned int offset, uint64_t romentry, void *priv)
1956 {
1957 struct command_invocation *cmd = priv;
1958 char tabs[16] = "";
1959
1960 if (depth)
1961 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1962
1963 if (retval != ERROR_OK) {
1964 command_print(cmd, "\t%sROMTABLE[0x%x] Read error", tabs, offset);
1965 command_print(cmd, "\t\tUnable to continue");
1966 command_print(cmd, "\t%s\tStop parsing of ROM table", tabs);
1967 return retval;
1968 }
1969
1970 command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%08" PRIx64,
1971 tabs, offset, romentry);
1972
1973 if (romentry == 0) {
1974 command_print(cmd, "\t%s\tEnd of ROM table", tabs);
1975 return ERROR_OK;
1976 }
1977
1978 if (!(romentry & ARM_CS_ROMENTRY_PRESENT)) {
1979 command_print(cmd, "\t\tComponent not present");
1980 return ERROR_OK;
1981 }
1982
1983 return ERROR_OK;
1984 }
1985
1986 int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
1987 {
1988 struct rtp_ops dap_info_ops = {
1989 .mem_ap_header = dap_info_mem_ap_header,
1990 .cs_component = dap_info_cs_component,
1991 .rom_table_entry = dap_info_rom_table_entry,
1992 .priv = cmd,
1993 };
1994
1995 return rtp_ap(&dap_info_ops, ap);
1996 }
1997
1998 /* Actions for dap_lookup_cs_component() */
1999
2000 struct dap_lookup_data {
2001 /* input */
2002 unsigned int idx;
2003 unsigned int type;
2004 /* output */
2005 uint64_t component_base;
2006 };
2007
2008 static int dap_lookup_cs_component_cs_component(int retval,
2009 struct cs_component_vals *v, int depth, void *priv)
2010 {
2011 struct dap_lookup_data *lookup = priv;
2012
2013 if (retval != ERROR_OK)
2014 return retval;
2015
2016 if (!is_valid_arm_cs_cidr(v->cid))
2017 return ERROR_OK;
2018
2019 const unsigned int class = ARM_CS_CIDR_CLASS(v->cid);
2020 if (class != ARM_CS_CLASS_0X9_CS_COMPONENT)
2021 return ERROR_OK;
2022
2023 if ((v->devtype_memtype & ARM_CS_C9_DEVTYPE_MASK) != lookup->type)
2024 return ERROR_OK;
2025
2026 if (lookup->idx) {
2027 /* search for next one */
2028 --lookup->idx;
2029 return ERROR_OK;
2030 }
2031
2032 /* Found! */
2033 lookup->component_base = v->component_base;
2034 return CORESIGHT_COMPONENT_FOUND;
2035 }
2036
2037 int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type,
2038 target_addr_t *addr, int32_t core_id)
2039 {
2040 struct dap_lookup_data lookup = {
2041 .type = type,
2042 .idx = core_id,
2043 };
2044 struct rtp_ops dap_lookup_cs_component_ops = {
2045 .mem_ap_header = NULL,
2046 .cs_component = dap_lookup_cs_component_cs_component,
2047 .rom_table_entry = NULL,
2048 .priv = &lookup,
2049 };
2050
2051 int retval = rtp_ap(&dap_lookup_cs_component_ops, ap);
2052 if (retval == CORESIGHT_COMPONENT_FOUND) {
2053 LOG_DEBUG("CS lookup found at 0x%" PRIx64, lookup.component_base);
2054 *addr = lookup.component_base;
2055 return ERROR_OK;
2056 }
2057 if (retval != ERROR_OK) {
2058 LOG_DEBUG("CS lookup error %d", retval);
2059 return retval;
2060 }
2061 LOG_DEBUG("CS lookup not found");
2062 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2063 }
2064
2065 enum adiv5_cfg_param {
2066 CFG_DAP,
2067 CFG_AP_NUM,
2068 CFG_BASEADDR,
2069 CFG_CTIBASE, /* DEPRECATED */
2070 };
2071
2072 static const struct jim_nvp nvp_config_opts[] = {
2073 { .name = "-dap", .value = CFG_DAP },
2074 { .name = "-ap-num", .value = CFG_AP_NUM },
2075 { .name = "-baseaddr", .value = CFG_BASEADDR },
2076 { .name = "-ctibase", .value = CFG_CTIBASE }, /* DEPRECATED */
2077 { .name = NULL, .value = -1 }
2078 };
2079
2080 static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
2081 struct adiv5_dap **dap_p, uint64_t *ap_num_p, uint32_t *base_p)
2082 {
2083 assert(dap_p && ap_num_p);
2084
2085 if (!goi->argc)
2086 return JIM_OK;
2087
2088 Jim_SetEmptyResult(goi->interp);
2089
2090 struct jim_nvp *n;
2091 int e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
2092 goi->argv[0], &n);
2093 if (e != JIM_OK)
2094 return JIM_CONTINUE;
2095
2096 /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
2097 if (!base_p && (n->value == CFG_BASEADDR || n->value == CFG_CTIBASE))
2098 return JIM_CONTINUE;
2099
2100 e = jim_getopt_obj(goi, NULL);
2101 if (e != JIM_OK)
2102 return e;
2103
2104 switch (n->value) {
2105 case CFG_DAP:
2106 if (goi->isconfigure) {
2107 Jim_Obj *o_t;
2108 struct adiv5_dap *dap;
2109 e = jim_getopt_obj(goi, &o_t);
2110 if (e != JIM_OK)
2111 return e;
2112 dap = dap_instance_by_jim_obj(goi->interp, o_t);
2113 if (!dap) {
2114 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
2115 return JIM_ERR;
2116 }
2117 if (*dap_p && *dap_p != dap) {
2118 Jim_SetResultString(goi->interp,
2119 "DAP assignment cannot be changed!", -1);
2120 return JIM_ERR;
2121 }
2122 *dap_p = dap;
2123 } else {
2124 if (goi->argc)
2125 goto err_no_param;
2126 if (!*dap_p) {
2127 Jim_SetResultString(goi->interp, "DAP not configured", -1);
2128 return JIM_ERR;
2129 }
2130 Jim_SetResultString(goi->interp, adiv5_dap_name(*dap_p), -1);
2131 }
2132 break;
2133
2134 case CFG_AP_NUM:
2135 if (goi->isconfigure) {
2136 /* jim_wide is a signed 64 bits int, ap_num is unsigned with max 52 bits */
2137 jim_wide ap_num;
2138 e = jim_getopt_wide(goi, &ap_num);
2139 if (e != JIM_OK)
2140 return e;
2141 /* we still don't know dap->adi_version */
2142 if (ap_num < 0 || (ap_num > DP_APSEL_MAX && (ap_num & 0xfff))) {
2143 Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
2144 return JIM_ERR;
2145 }
2146 *ap_num_p = ap_num;
2147 } else {
2148 if (goi->argc)
2149 goto err_no_param;
2150 if (*ap_num_p == DP_APSEL_INVALID) {
2151 Jim_SetResultString(goi->interp, "AP number not configured", -1);
2152 return JIM_ERR;
2153 }
2154 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *ap_num_p));
2155 }
2156 break;
2157
2158 case CFG_CTIBASE:
2159 LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
2160 /* fall through */
2161 case CFG_BASEADDR:
2162 if (goi->isconfigure) {
2163 jim_wide base;
2164 e = jim_getopt_wide(goi, &base);
2165 if (e != JIM_OK)
2166 return e;
2167 *base_p = (uint32_t)base;
2168 } else {
2169 if (goi->argc)
2170 goto err_no_param;
2171 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *base_p));
2172 }
2173 break;
2174 };
2175
2176 return JIM_OK;
2177
2178 err_no_param:
2179 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "NO PARAMS");
2180 return JIM_ERR;
2181 }
2182
2183 int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
2184 {
2185 struct adiv5_private_config *pc;
2186 int e;
2187
2188 pc = (struct adiv5_private_config *)target->private_config;
2189 if (!pc) {
2190 pc = calloc(1, sizeof(struct adiv5_private_config));
2191 if (!pc) {
2192 LOG_ERROR("Out of memory");
2193 return JIM_ERR;
2194 }
2195 pc->ap_num = DP_APSEL_INVALID;
2196 target->private_config = pc;
2197 }
2198
2199 target->has_dap = true;
2200
2201 e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL);
2202 if (e != JIM_OK)
2203 return e;
2204
2205 if (pc->dap && !target->dap_configured) {
2206 if (target->tap_configured) {
2207 pc->dap = NULL;
2208 Jim_SetResultString(goi->interp,
2209 "-chain-position and -dap configparams are mutually exclusive!", -1);
2210 return JIM_ERR;
2211 }
2212 target->tap = pc->dap->tap;
2213 target->dap_configured = true;
2214 }
2215
2216 return JIM_OK;
2217 }
2218
2219 int adiv5_verify_config(struct adiv5_private_config *pc)
2220 {
2221 if (!pc)
2222 return ERROR_FAIL;
2223
2224 if (!pc->dap)
2225 return ERROR_FAIL;
2226
2227 return ERROR_OK;
2228 }
2229
2230 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
2231 struct jim_getopt_info *goi)
2232 {
2233 return adiv5_jim_spot_configure(goi, &cfg->dap, &cfg->ap_num, &cfg->base);
2234 }
2235
2236 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
2237 {
2238 p->dap = NULL;
2239 p->ap_num = DP_APSEL_INVALID;
2240 p->base = 0;
2241 return ERROR_OK;
2242 }
2243
2244 COMMAND_HANDLER(handle_dap_info_command)
2245 {
2246 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2247 uint64_t apsel;
2248
2249 switch (CMD_ARGC) {
2250 case 0:
2251 apsel = dap->apsel;
2252 break;
2253 case 1:
2254 if (!strcmp(CMD_ARGV[0], "root")) {
2255 if (!is_adiv6(dap)) {
2256 command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP");
2257 return ERROR_COMMAND_ARGUMENT_INVALID;
2258 }
2259 int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel);
2260 if (retval != ERROR_OK) {
2261 command_print(CMD, "Failed reading DAP baseptr");
2262 return retval;
2263 }
2264 break;
2265 }
2266 COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2267 if (!is_ap_num_valid(dap, apsel)) {
2268 command_print(CMD, "Invalid AP number");
2269 return ERROR_COMMAND_ARGUMENT_INVALID;
2270 }
2271 break;
2272 default:
2273 return ERROR_COMMAND_SYNTAX_ERROR;
2274 }
2275
2276 struct adiv5_ap *ap = dap_get_ap(dap, apsel);
2277 if (!ap) {
2278 command_print(CMD, "Cannot get AP");
2279 return ERROR_FAIL;
2280 }
2281
2282 int retval = dap_info_command(CMD, ap);
2283 dap_put_ap(ap);
2284 return retval;
2285 }
2286
2287 COMMAND_HANDLER(dap_baseaddr_command)
2288 {
2289 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2290 uint64_t apsel;
2291 uint32_t baseaddr_lower, baseaddr_upper;
2292 struct adiv5_ap *ap;
2293 target_addr_t baseaddr;
2294 int retval;
2295
2296 baseaddr_upper = 0;
2297
2298 switch (CMD_ARGC) {
2299 case 0:
2300 apsel = dap->apsel;
2301 break;
2302 case 1:
2303 COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2304 if (!is_ap_num_valid(dap, apsel)) {
2305 command_print(CMD, "Invalid AP number");
2306 return ERROR_COMMAND_ARGUMENT_INVALID;
2307 }
2308 break;
2309 default:
2310 return ERROR_COMMAND_SYNTAX_ERROR;
2311 }
2312
2313 /* NOTE: assumes we're talking to a MEM-AP, which
2314 * has a base address. There are other kinds of AP,
2315 * though they're not common for now. This should
2316 * use the ID register to verify it's a MEM-AP.
2317 */
2318
2319 ap = dap_get_ap(dap, apsel);
2320 if (!ap) {
2321 command_print(CMD, "Cannot get AP");
2322 return ERROR_FAIL;
2323 }
2324
2325 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE(dap), &baseaddr_lower);
2326
2327 if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
2328 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &ap->cfg_reg);
2329
2330 if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
2331 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
2332 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64(dap), &baseaddr_upper);
2333 }
2334
2335 if (retval == ERROR_OK)
2336 retval = dap_run(dap);
2337 dap_put_ap(ap);
2338 if (retval != ERROR_OK)
2339 return retval;
2340
2341 if (is_64bit_ap(ap)) {
2342 baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
2343 command_print(CMD, "0x%016" PRIx64, baseaddr);
2344 } else
2345 command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
2346
2347 return ERROR_OK;
2348 }
2349
2350 COMMAND_HANDLER(dap_memaccess_command)
2351 {
2352 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2353 struct adiv5_ap *ap;
2354 uint32_t memaccess_tck;
2355
2356 switch (CMD_ARGC) {
2357 case 0:
2358 ap = dap_get_ap(dap, dap->apsel);
2359 if (!ap) {
2360 command_print(CMD, "Cannot get AP");
2361 return ERROR_FAIL;
2362 }
2363 memaccess_tck = ap->memaccess_tck;
2364 break;
2365 case 1:
2366 ap = dap_get_config_ap(dap, dap->apsel);
2367 if (!ap) {
2368 command_print(CMD, "Cannot get AP");
2369 return ERROR_FAIL;
2370 }
2371 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
2372 ap->memaccess_tck = memaccess_tck;
2373 break;
2374 default:
2375 return ERROR_COMMAND_SYNTAX_ERROR;
2376 }
2377
2378 dap_put_ap(ap);
2379
2380 command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
2381 memaccess_tck);
2382
2383 return ERROR_OK;
2384 }
2385
2386 COMMAND_HANDLER(dap_apsel_command)
2387 {
2388 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2389 uint64_t apsel;
2390
2391 switch (CMD_ARGC) {
2392 case 0:
2393 command_print(CMD, "0x%" PRIx64, dap->apsel);
2394 return ERROR_OK;
2395 case 1:
2396 COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2397 if (!is_ap_num_valid(dap, apsel)) {
2398 command_print(CMD, "Invalid AP number");
2399 return ERROR_COMMAND_ARGUMENT_INVALID;
2400 }
2401 break;
2402 default:
2403 return ERROR_COMMAND_SYNTAX_ERROR;
2404 }
2405
2406 dap->apsel = apsel;
2407 return ERROR_OK;
2408 }
2409
2410 COMMAND_HANDLER(dap_apcsw_command)
2411 {
2412 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2413 struct adiv5_ap *ap;
2414 uint32_t csw_val, csw_mask;
2415
2416 switch (CMD_ARGC) {
2417 case 0:
2418 ap = dap_get_ap(dap, dap->apsel);
2419 if (!ap) {
2420 command_print(CMD, "Cannot get AP");
2421 return ERROR_FAIL;
2422 }
2423 command_print(CMD, "AP#0x%" PRIx64 " selected, csw 0x%8.8" PRIx32,
2424 dap->apsel, ap->csw_default);
2425 break;
2426 case 1:
2427 if (strcmp(CMD_ARGV[0], "default") == 0)
2428 csw_val = CSW_AHB_DEFAULT;
2429 else
2430 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
2431
2432 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
2433 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
2434 return ERROR_COMMAND_ARGUMENT_INVALID;
2435 }
2436 ap = dap_get_config_ap(dap, dap->apsel);
2437 if (!ap) {
2438 command_print(CMD, "Cannot get AP");
2439 return ERROR_FAIL;
2440 }
2441 ap->csw_default = csw_val;
2442 break;
2443 case 2:
2444 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
2445 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
2446 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
2447 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
2448 return ERROR_COMMAND_ARGUMENT_INVALID;
2449 }
2450 ap = dap_get_config_ap(dap, dap->apsel);
2451 if (!ap) {
2452 command_print(CMD, "Cannot get AP");
2453 return ERROR_FAIL;
2454 }
2455 ap->csw_default = (ap->csw_default & ~csw_mask) | (csw_val & csw_mask);
2456 break;
2457 default:
2458 return ERROR_COMMAND_SYNTAX_ERROR;
2459 }
2460 dap_put_ap(ap);
2461
2462 return ERROR_OK;
2463 }
2464
2465
2466
2467 COMMAND_HANDLER(dap_apid_command)
2468 {
2469 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2470 uint64_t apsel;
2471 uint32_t apid;
2472 int retval;
2473
2474 switch (CMD_ARGC) {
2475 case 0:
2476 apsel = dap->apsel;
2477 break;
2478 case 1:
2479 COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2480 if (!is_ap_num_valid(dap, apsel)) {
2481 command_print(CMD, "Invalid AP number");
2482 return ERROR_COMMAND_ARGUMENT_INVALID;
2483 }
2484 break;
2485 default:
2486 return ERROR_COMMAND_SYNTAX_ERROR;
2487 }
2488
2489 struct adiv5_ap *ap = dap_get_ap(dap, apsel);
2490 if (!ap) {
2491 command_print(CMD, "Cannot get AP");
2492 return ERROR_FAIL;
2493 }
2494 retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), &apid);
2495 if (retval != ERROR_OK) {
2496 dap_put_ap(ap);
2497 return retval;
2498 }
2499 retval = dap_run(dap);
2500 dap_put_ap(ap);
2501 if (retval != ERROR_OK)
2502 return retval;
2503
2504 command_print(CMD, "0x%8.8" PRIx32, apid);
2505
2506 return retval;
2507 }
2508
2509 COMMAND_HANDLER(dap_apreg_command)
2510 {
2511 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2512 uint64_t apsel;
2513 uint32_t reg, value;
2514 int retval;
2515
2516 if (CMD_ARGC < 2 || CMD_ARGC > 3)
2517 return ERROR_COMMAND_SYNTAX_ERROR;
2518
2519 COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2520 if (!is_ap_num_valid(dap, apsel)) {
2521 command_print(CMD, "Invalid AP number");
2522 return ERROR_COMMAND_ARGUMENT_INVALID;
2523 }
2524
2525 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
2526 if (is_adiv6(dap)) {
2527 if (reg >= 4096 || (reg & 3)) {
2528 command_print(CMD, "Invalid reg value (should be less than 4096 and 4 bytes aligned)");
2529 return ERROR_COMMAND_ARGUMENT_INVALID;
2530 }
2531 } else { /* ADI version 5 */
2532 if (reg >= 256 || (reg & 3)) {
2533 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2534 return ERROR_COMMAND_ARGUMENT_INVALID;
2535 }
2536 }
2537
2538 struct adiv5_ap *ap = dap_get_ap(dap, apsel);
2539 if (!ap) {
2540 command_print(CMD, "Cannot get AP");
2541 return ERROR_FAIL;
2542 }
2543
2544 if (CMD_ARGC == 3) {
2545 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2546 /* see if user supplied register address is a match for the CSW or TAR register */
2547 if (reg == MEM_AP_REG_CSW(dap)) {
2548 ap->csw_value = 0; /* invalid, in case write fails */
2549 retval = dap_queue_ap_write(ap, reg, value);
2550 if (retval == ERROR_OK)
2551 ap->csw_value = value;
2552 } else if (reg == MEM_AP_REG_TAR(dap)) {
2553 retval = dap_queue_ap_write(ap, reg, value);
2554 if (retval == ERROR_OK)
2555 ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value;
2556 else {
2557 /* To track independent writes to TAR and TAR64, two tar_valid flags */
2558 /* should be used. To keep it simple, tar_valid is only invalidated on a */
2559 /* write fail. This approach causes a later re-write of the TAR and TAR64 */
2560 /* if tar_valid is false. */
2561 ap->tar_valid = false;
2562 }
2563 } else if (reg == MEM_AP_REG_TAR64(dap)) {
2564 retval = dap_queue_ap_write(ap, reg, value);
2565 if (retval == ERROR_OK)
2566 ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32);
2567 else {
2568 /* See above comment for the MEM_AP_REG_TAR failed write case */
2569 ap->tar_valid = false;
2570 }
2571 } else {
2572 retval = dap_queue_ap_write(ap, reg, value);
2573 }
2574 } else {
2575 retval = dap_queue_ap_read(ap, reg, &value);
2576 }
2577 if (retval == ERROR_OK)
2578 retval = dap_run(dap);
2579
2580 dap_put_ap(ap);
2581
2582 if (retval != ERROR_OK)
2583 return retval;
2584
2585 if (CMD_ARGC == 2)
2586 command_print(CMD, "0x%08" PRIx32, value);
2587
2588 return retval;
2589 }
2590
2591 COMMAND_HANDLER(dap_dpreg_command)
2592 {
2593 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2594 uint32_t reg, value;
2595 int retval;
2596
2597 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2598 return ERROR_COMMAND_SYNTAX_ERROR;
2599
2600 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
2601 if (reg >= 256 || (reg & 3)) {
2602 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2603 return ERROR_COMMAND_ARGUMENT_INVALID;
2604 }
2605
2606 if (CMD_ARGC == 2) {
2607 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2608 retval = dap_queue_dp_write(dap, reg, value);
2609 } else {
2610 retval = dap_queue_dp_read(dap, reg, &value);
2611 }
2612 if (retval == ERROR_OK)
2613 retval = dap_run(dap);
2614
2615 if (retval != ERROR_OK)
2616 return retval;
2617
2618 if (CMD_ARGC == 1)
2619 command_print(CMD, "0x%08" PRIx32, value);
2620
2621 return retval;
2622 }
2623
2624 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
2625 {
2626 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2627 return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
2628 "TI BE-32 quirks mode");
2629 }
2630
2631 const struct command_registration dap_instance_commands[] = {
2632 {
2633 .name = "info",
2634 .handler = handle_dap_info_command,
2635 .mode = COMMAND_EXEC,
2636 .help = "display ROM table for specified MEM-AP (default currently selected AP) "
2637 "or the ADIv6 root ROM table",
2638 .usage = "[ap_num | 'root']",
2639 },
2640 {
2641 .name = "apsel",
2642 .handler = dap_apsel_command,
2643 .mode = COMMAND_ANY,
2644 .help = "Set the currently selected AP (default 0) "
2645 "and display the result",
2646 .usage = "[ap_num]",
2647 },
2648 {
2649 .name = "apcsw",
2650 .handler = dap_apcsw_command,
2651 .mode = COMMAND_ANY,
2652 .help = "Set CSW default bits",
2653 .usage = "[value [mask]]",
2654 },
2655
2656 {
2657 .name = "apid",
2658 .handler = dap_apid_command,
2659 .mode = COMMAND_EXEC,
2660 .help = "return ID register from AP "
2661 "(default currently selected AP)",
2662 .usage = "[ap_num]",
2663 },
2664 {
2665 .name = "apreg",
2666 .handler = dap_apreg_command,
2667 .mode = COMMAND_EXEC,
2668 .help = "read/write a register from AP "
2669 "(reg is byte address of a word register, like 0 4 8...)",
2670 .usage = "ap_num reg [value]",
2671 },
2672 {
2673 .name = "dpreg",
2674 .handler = dap_dpreg_command,
2675 .mode = COMMAND_EXEC,
2676 .help = "read/write a register from DP "
2677 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
2678 .usage = "reg [value]",
2679 },
2680 {
2681 .name = "baseaddr",
2682 .handler = dap_baseaddr_command,
2683 .mode = COMMAND_EXEC,
2684 .help = "return debug base address from MEM-AP "
2685 "(default currently selected AP)",
2686 .usage = "[ap_num]",
2687 },
2688 {
2689 .name = "memaccess",
2690 .handler = dap_memaccess_command,
2691 .mode = COMMAND_EXEC,
2692 .help = "set/get number of extra tck for MEM-AP memory "
2693 "bus access [0-255]",
2694 .usage = "[cycles]",
2695 },
2696 {
2697 .name = "ti_be_32_quirks",
2698 .handler = dap_ti_be_32_quirks_command,
2699 .mode = COMMAND_CONFIG,
2700 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
2701 .usage = "[enable]",
2702 },
2703 COMMAND_REGISTRATION_DONE
2704 };
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