1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2006 by Magnus Lundin *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
10 * Copyright (C) 2009-2010 by Oyvind Harboe *
11 * oyvind.harboe@zylin.com *
13 * Copyright (C) 2009-2010 by David Brownell *
15 * Copyright (C) 2013 by Andreas Fritiofson *
16 * andreas.fritiofson@gmail.com *
18 * Copyright (C) 2019-2021, Ampere Computing LLC *
19 ***************************************************************************/
23 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
24 * debugging architecture. Compared with previous versions, this includes
25 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
26 * transport, and focuses on memory mapped resources as defined by the
27 * CoreSight architecture.
29 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
30 * basic components: a Debug Port (DP) transporting messages to and from a
31 * debugger, and an Access Port (AP) accessing resources. Three types of DP
32 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
33 * One uses only SWD for communication, and is called SW-DP. The third can
34 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
35 * is used to access memory mapped resources and is called a MEM-AP. Also a
36 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
38 * This programming interface allows DAP pipelined operations through a
39 * transaction queue. This primarily affects AP operations (such as using
40 * a MEM-AP to access memory or registers). If the current transaction has
41 * not finished by the time the next one must begin, and the ORUNDETECT bit
42 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
43 * further AP operations will fail. There are two basic methods to avoid
44 * such overrun errors. One involves polling for status instead of using
45 * transaction pipelining. The other involves adding delays to ensure the
46 * AP has enough time to complete one operation before starting the next
47 * one. (For JTAG these delays are controlled by memaccess_tck.)
51 * Relevant specifications from ARM include:
53 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
54 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
56 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
57 * Cortex-M3(tm) TRM, ARM DDI 0337G
64 #include "jtag/interface.h"
66 #include "arm_adi_v5.h"
67 #include "arm_coresight.h"
69 #include "transport/transport.h"
70 #include <helper/align.h>
71 #include <helper/jep106.h>
72 #include <helper/time_support.h>
73 #include <helper/list.h>
74 #include <helper/jim-nvp.h>
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
79 uint32_t tar_block_size(uint32_t address)
80 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, target_addr_t address
)
84 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
87 /***************************************************************************
89 * DP and MEM-AP register access through APACC and DPACC *
91 ***************************************************************************/
93 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
95 csw
|= ap
->csw_default
;
97 if (csw
!= ap
->csw_value
) {
98 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
99 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_CSW(ap
->dap
), csw
);
100 if (retval
!= ERROR_OK
) {
109 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, target_addr_t tar
)
111 if (!ap
->tar_valid
|| tar
!= ap
->tar_value
) {
112 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
113 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR(ap
->dap
), (uint32_t)(tar
& 0xffffffffUL
));
114 if (retval
== ERROR_OK
&& is_64bit_ap(ap
)) {
115 /* See if bits 63:32 of tar is different from last setting */
116 if ((ap
->tar_value
>> 32) != (tar
>> 32))
117 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR64(ap
->dap
), (uint32_t)(tar
>> 32));
119 if (retval
!= ERROR_OK
) {
120 ap
->tar_valid
= false;
124 ap
->tar_valid
= true;
129 static int mem_ap_read_tar(struct adiv5_ap
*ap
, target_addr_t
*tar
)
134 int retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR(ap
->dap
), &lower
);
135 if (retval
== ERROR_OK
&& is_64bit_ap(ap
))
136 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR64(ap
->dap
), &upper
);
138 if (retval
!= ERROR_OK
) {
139 ap
->tar_valid
= false;
143 retval
= dap_run(ap
->dap
);
144 if (retval
!= ERROR_OK
) {
145 ap
->tar_valid
= false;
149 *tar
= (((target_addr_t
)upper
) << 32) | (target_addr_t
)lower
;
151 ap
->tar_value
= *tar
;
152 ap
->tar_valid
= true;
156 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap
*ap
)
158 switch (ap
->csw_value
& CSW_ADDRINC_MASK
) {
159 case CSW_ADDRINC_SINGLE
:
160 switch (ap
->csw_value
& CSW_SIZE_MASK
) {
170 case CSW_ADDRINC_PACKED
:
176 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
178 static void mem_ap_update_tar_cache(struct adiv5_ap
*ap
)
183 uint32_t inc
= mem_ap_get_tar_increment(ap
);
184 if (inc
>= max_tar_block_size(ap
->tar_autoincr_block
, ap
->tar_value
))
185 ap
->tar_valid
= false;
187 ap
->tar_value
+= inc
;
191 * Queue transactions setting up transfer parameters for the
192 * currently selected MEM-AP.
194 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
195 * initiate data reads or writes using memory or peripheral addresses.
196 * If the CSW is configured for it, the TAR may be automatically
197 * incremented after each transfer.
199 * @param ap The MEM-AP.
200 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
201 * matches the cached value, the register is not changed.
202 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
203 * matches the cached address, the register is not changed.
205 * @return ERROR_OK if the transaction was properly queued, else a fault code.
207 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, target_addr_t tar
)
210 retval
= mem_ap_setup_csw(ap
, csw
);
211 if (retval
!= ERROR_OK
)
213 retval
= mem_ap_setup_tar(ap
, tar
);
214 if (retval
!= ERROR_OK
)
220 * Asynchronous (queued) read of a word from memory or a system register.
222 * @param ap The MEM-AP to access.
223 * @param address Address of the 32-bit word to read; it must be
224 * readable by the currently selected MEM-AP.
225 * @param value points to where the word will be stored when the
226 * transaction queue is flushed (assuming no errors).
228 * @return ERROR_OK for success. Otherwise a fault code.
230 int mem_ap_read_u32(struct adiv5_ap
*ap
, target_addr_t address
,
235 /* Use banked addressing (REG_BDx) to avoid some link traffic
236 * (updating TAR) when reading several consecutive addresses.
238 retval
= mem_ap_setup_transfer(ap
,
239 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
240 address
& 0xFFFFFFFFFFFFFFF0ull
);
241 if (retval
!= ERROR_OK
)
244 return dap_queue_ap_read(ap
, MEM_AP_REG_BD0(ap
->dap
) | (address
& 0xC), value
);
248 * Synchronous read of a word from memory or a system register.
249 * As a side effect, this flushes any queued transactions.
251 * @param ap The MEM-AP to access.
252 * @param address Address of the 32-bit word to read; it must be
253 * readable by the currently selected MEM-AP.
254 * @param value points to where the result will be stored.
256 * @return ERROR_OK for success; *value holds the result.
257 * Otherwise a fault code.
259 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, target_addr_t address
,
264 retval
= mem_ap_read_u32(ap
, address
, value
);
265 if (retval
!= ERROR_OK
)
268 return dap_run(ap
->dap
);
272 * Asynchronous (queued) write of a word to memory or a system register.
274 * @param ap The MEM-AP to access.
275 * @param address Address to be written; it must be writable by
276 * the currently selected MEM-AP.
277 * @param value Word that will be written to the address when transaction
278 * queue is flushed (assuming no errors).
280 * @return ERROR_OK for success. Otherwise a fault code.
282 int mem_ap_write_u32(struct adiv5_ap
*ap
, target_addr_t address
,
287 /* Use banked addressing (REG_BDx) to avoid some link traffic
288 * (updating TAR) when writing several consecutive addresses.
290 retval
= mem_ap_setup_transfer(ap
,
291 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
292 address
& 0xFFFFFFFFFFFFFFF0ull
);
293 if (retval
!= ERROR_OK
)
296 return dap_queue_ap_write(ap
, MEM_AP_REG_BD0(ap
->dap
) | (address
& 0xC),
301 * Synchronous write of a word to memory or a system register.
302 * As a side effect, this flushes any queued transactions.
304 * @param ap The MEM-AP to access.
305 * @param address Address to be written; it must be writable by
306 * the currently selected MEM-AP.
307 * @param value Word that will be written.
309 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
311 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, target_addr_t address
,
314 int retval
= mem_ap_write_u32(ap
, address
, value
);
316 if (retval
!= ERROR_OK
)
319 return dap_run(ap
->dap
);
323 * Synchronous write of a block of memory, using a specific access size.
325 * @param ap The MEM-AP to access.
326 * @param buffer The data buffer to write. No particular alignment is assumed.
327 * @param size Which access size to use, in bytes. 1, 2 or 4.
328 * @param count The number of writes to do (in size units, not bytes).
329 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
330 * @param addrinc Whether the target address should be increased for each write or not. This
331 * should normally be true, except when writing to e.g. a FIFO.
332 * @return ERROR_OK on success, otherwise an error code.
334 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
335 target_addr_t address
, bool addrinc
)
337 struct adiv5_dap
*dap
= ap
->dap
;
338 size_t nbytes
= size
* count
;
339 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
341 target_addr_t addr_xor
;
342 int retval
= ERROR_OK
;
344 /* TI BE-32 Quirks mode:
345 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
346 * size write address bytes written in order
347 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
348 * 2 TAR ^ 2 (val >> 8), (val)
350 * For example, if you attempt to write a single byte to address 0, the processor
351 * will actually write a byte to address 3.
353 * To make writes of size < 4 work as expected, we xor a value with the address before
354 * setting the TAP, and we set the TAP after every transfer rather then relying on
355 * address increment. */
358 csw_size
= CSW_32BIT
;
360 } else if (size
== 2) {
361 csw_size
= CSW_16BIT
;
362 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
363 } else if (size
== 1) {
365 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
367 return ERROR_TARGET_UNALIGNED_ACCESS
;
370 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
371 return ERROR_TARGET_UNALIGNED_ACCESS
;
374 uint32_t this_size
= size
;
376 /* Select packed transfer if possible */
377 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
378 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
380 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
382 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
385 if (retval
!= ERROR_OK
)
388 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
389 if (retval
!= ERROR_OK
)
392 /* How many source bytes each transfer will consume, and their location in the DRW,
393 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
394 uint32_t outvalue
= 0;
395 uint32_t drw_byte_idx
= address
;
396 if (dap
->ti_be_32_quirks
) {
399 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
400 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
401 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
402 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
& 3) ^ addr_xor
);
405 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
406 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
& 3) ^ addr_xor
);
409 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (drw_byte_idx
& 3) ^ addr_xor
);
415 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
416 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
419 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
422 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
& 3);
428 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_DRW(dap
), outvalue
);
429 if (retval
!= ERROR_OK
)
432 mem_ap_update_tar_cache(ap
);
434 address
+= this_size
;
437 /* REVISIT: Might want to have a queued version of this function that does not run. */
438 if (retval
== ERROR_OK
)
439 retval
= dap_run(dap
);
441 if (retval
!= ERROR_OK
) {
443 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
)
444 LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT
, tar
);
446 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
453 * Synchronous read of a block of memory, using a specific access size.
455 * @param ap The MEM-AP to access.
456 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
457 * @param size Which access size to use, in bytes. 1, 2 or 4.
458 * @param count The number of reads to do (in size units, not bytes).
459 * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
460 * @param addrinc Whether the target address should be increased after each read or not. This
461 * should normally be true, except when reading from e.g. a FIFO.
462 * @return ERROR_OK on success, otherwise an error code.
464 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
465 target_addr_t adr
, bool addrinc
)
467 struct adiv5_dap
*dap
= ap
->dap
;
468 size_t nbytes
= size
* count
;
469 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
471 target_addr_t address
= adr
;
472 int retval
= ERROR_OK
;
474 /* TI BE-32 Quirks mode:
475 * Reads on big-endian TMS570 behave strangely differently than writes.
476 * They read from the physical address requested, but with DRW byte-reversed.
477 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
478 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
482 csw_size
= CSW_32BIT
;
484 csw_size
= CSW_16BIT
;
488 return ERROR_TARGET_UNALIGNED_ACCESS
;
490 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
491 return ERROR_TARGET_UNALIGNED_ACCESS
;
493 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
494 * over-allocation if packed transfers are going to be used, but determining the real need at
495 * this point would be messy. */
496 uint32_t *read_buf
= calloc(count
, sizeof(uint32_t));
497 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
498 uint32_t *read_ptr
= read_buf
;
500 LOG_ERROR("Failed to allocate read buffer");
504 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
505 * useful bytes it contains, and their location in the word, depends on the type of transfer
508 uint32_t this_size
= size
;
510 /* Select packed transfer if possible */
511 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
512 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
514 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
516 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
518 if (retval
!= ERROR_OK
)
521 retval
= mem_ap_setup_tar(ap
, address
);
522 if (retval
!= ERROR_OK
)
525 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_DRW(dap
), read_ptr
++);
526 if (retval
!= ERROR_OK
)
531 address
+= this_size
;
533 mem_ap_update_tar_cache(ap
);
536 if (retval
== ERROR_OK
)
537 retval
= dap_run(dap
);
541 nbytes
= size
* count
;
544 /* If something failed, read TAR to find out how much data was successfully read, so we can
545 * at least give the caller what we have. */
546 if (retval
!= ERROR_OK
) {
548 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
) {
549 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
550 LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT
, tar
);
551 if (nbytes
> tar
- address
)
552 nbytes
= tar
- address
;
554 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
559 /* Replay loop to populate caller's buffer from the correct word and byte lane */
561 uint32_t this_size
= size
;
563 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
564 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
568 if (dap
->ti_be_32_quirks
) {
571 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
572 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
575 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
578 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
583 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
584 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
587 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
590 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
602 int mem_ap_read_buf(struct adiv5_ap
*ap
,
603 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
605 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
608 int mem_ap_write_buf(struct adiv5_ap
*ap
,
609 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
611 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
614 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
615 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
617 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
620 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
621 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
623 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
626 /*--------------------------------------------------------------------------*/
629 #define DAP_POWER_DOMAIN_TIMEOUT (10)
631 /*--------------------------------------------------------------------------*/
634 * Invalidate cached DP select and cached TAR and CSW of all APs
636 void dap_invalidate_cache(struct adiv5_dap
*dap
)
638 dap
->select
= DP_SELECT_INVALID
;
639 dap
->last_read
= NULL
;
642 for (i
= 0; i
<= DP_APSEL_MAX
; i
++) {
643 /* force csw and tar write on the next mem-ap access */
644 dap
->ap
[i
].tar_valid
= false;
645 dap
->ap
[i
].csw_value
= 0;
650 * Initialize a DAP. This sets up the power domains, prepares the DP
651 * for further use and activates overrun checking.
653 * @param dap The DAP being initialized.
655 int dap_dp_init(struct adiv5_dap
*dap
)
659 LOG_DEBUG("%s", adiv5_dap_name(dap
));
661 dap
->do_reconnect
= false;
662 dap_invalidate_cache(dap
);
665 * Early initialize dap->dp_ctrl_stat.
666 * In jtag mode only, if the following queue run (in dap_dp_poll_register)
667 * fails and sets the sticky error, it will trigger the clearing
668 * of the sticky. Without this initialization system and debug power
669 * would be disabled while clearing the sticky error bit.
671 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
674 * This write operation clears the sticky error bit in jtag mode only and
675 * is ignored in swd mode. It also powers-up system and debug domains in
676 * both jtag and swd modes, if not done before.
678 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
| SSTICKYERR
);
679 if (retval
!= ERROR_OK
)
682 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
683 if (retval
!= ERROR_OK
)
686 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
687 if (retval
!= ERROR_OK
)
690 /* Check that we have debug power domains activated */
691 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
692 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
693 CDBGPWRUPACK
, CDBGPWRUPACK
,
694 DAP_POWER_DOMAIN_TIMEOUT
);
695 if (retval
!= ERROR_OK
)
698 if (!dap
->ignore_syspwrupack
) {
699 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
700 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
701 CSYSPWRUPACK
, CSYSPWRUPACK
,
702 DAP_POWER_DOMAIN_TIMEOUT
);
703 if (retval
!= ERROR_OK
)
707 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
708 if (retval
!= ERROR_OK
)
711 /* With debug power on we can activate OVERRUN checking */
712 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
713 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
714 if (retval
!= ERROR_OK
)
716 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
717 if (retval
!= ERROR_OK
)
720 retval
= dap_run(dap
);
721 if (retval
!= ERROR_OK
)
728 * Initialize a DAP or do reconnect if DAP is not accessible.
730 * @param dap The DAP being initialized.
732 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
)
734 LOG_DEBUG("%s", adiv5_dap_name(dap
));
737 * Early initialize dap->dp_ctrl_stat.
738 * In jtag mode only, if the following atomic reads fail and set the
739 * sticky error, it will trigger the clearing of the sticky. Without this
740 * initialization system and debug power would be disabled while clearing
741 * the sticky error bit.
743 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
745 dap
->do_reconnect
= false;
747 dap_dp_read_atomic(dap
, DP_CTRL_STAT
, NULL
);
748 if (dap
->do_reconnect
) {
749 /* dap connect calls dap_dp_init() after transport dependent initialization */
750 return dap
->ops
->connect(dap
);
752 return dap_dp_init(dap
);
757 * Initialize a DAP. This sets up the power domains, prepares the DP
758 * for further use, and arranges to use AP #0 for all AP operations
759 * until dap_ap-select() changes that policy.
761 * @param ap The MEM-AP being initialized.
763 int mem_ap_init(struct adiv5_ap
*ap
)
765 /* check that we support packed transfers */
768 struct adiv5_dap
*dap
= ap
->dap
;
770 /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
771 /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
772 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG(dap
), &cfg
);
773 if (retval
!= ERROR_OK
)
776 retval
= dap_run(dap
);
777 if (retval
!= ERROR_OK
)
781 ap
->tar_valid
= false;
782 ap
->csw_value
= 0; /* force csw and tar write */
783 retval
= mem_ap_setup_transfer(ap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
784 if (retval
!= ERROR_OK
)
787 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CSW(dap
), &csw
);
788 if (retval
!= ERROR_OK
)
791 retval
= dap_run(dap
);
792 if (retval
!= ERROR_OK
)
795 if (csw
& CSW_ADDRINC_PACKED
)
796 ap
->packed_transfers
= true;
798 ap
->packed_transfers
= false;
800 /* Packed transfers on TI BE-32 processors do not work correctly in
802 if (dap
->ti_be_32_quirks
)
803 ap
->packed_transfers
= false;
805 LOG_DEBUG("MEM_AP Packed Transfers: %s",
806 ap
->packed_transfers
? "enabled" : "disabled");
808 /* The ARM ADI spec leaves implementation-defined whether unaligned
809 * memory accesses work, only work partially, or cause a sticky error.
810 * On TI BE-32 processors, reads seem to return garbage in some bytes
811 * and unaligned writes seem to cause a sticky error.
812 * TODO: it would be nice to have a way to detect whether unaligned
813 * operations are supported on other processors. */
814 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
816 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
817 !!(cfg
& MEM_AP_REG_CFG_LD
), !!(cfg
& MEM_AP_REG_CFG_LA
), !!(cfg
& MEM_AP_REG_CFG_BE
));
823 * Put the debug link into SWD mode, if the target supports it.
824 * The link's initial mode may be either JTAG (for example,
825 * with SWJ-DP after reset) or SWD.
827 * Note that targets using the JTAG-DP do not support SWD, and that
828 * some targets which could otherwise support it may have been
829 * configured to disable SWD signaling
831 * @param dap The DAP used
832 * @return ERROR_OK or else a fault code.
834 int dap_to_swd(struct adiv5_dap
*dap
)
836 LOG_DEBUG("Enter SWD mode");
838 return dap_send_sequence(dap
, JTAG_TO_SWD
);
842 * Put the debug link into JTAG mode, if the target supports it.
843 * The link's initial mode may be either SWD or JTAG.
845 * Note that targets implemented with SW-DP do not support JTAG, and
846 * that some targets which could otherwise support it may have been
847 * configured to disable JTAG signaling
849 * @param dap The DAP used
850 * @return ERROR_OK or else a fault code.
852 int dap_to_jtag(struct adiv5_dap
*dap
)
854 LOG_DEBUG("Enter JTAG mode");
856 return dap_send_sequence(dap
, SWD_TO_JTAG
);
859 /* CID interpretation -- see ARM IHI 0029E table B2-7
860 * and ARM IHI 0031E table D1-2.
862 * From 2009/11/25 commit 21378f58b604:
863 * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
864 * Let's keep it as is, for the time being
866 static const char *class_description
[16] = {
867 [0x0] = "Generic verification component",
876 [0x9] = "CoreSight component",
878 [0xB] = "Peripheral Test Block",
880 [0xD] = "OptimoDE DESS", /* see above */
881 [0xE] = "Generic IP component",
882 [0xF] = "CoreLink, PrimeCell or System component",
885 #define ARCH_ID(architect, archid) ( \
886 (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
887 (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
890 static const struct {
892 const char *description
;
893 } class0x9_devarch
[] = {
894 /* keep same unsorted order as in ARM IHI0029E */
895 { ARCH_ID(ARM_ID
, 0x0A00), "RAS architecture" },
896 { ARCH_ID(ARM_ID
, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
897 { ARCH_ID(ARM_ID
, 0x1A02), "DWT architecture" },
898 { ARCH_ID(ARM_ID
, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
899 { ARCH_ID(ARM_ID
, 0x2A04), "Processor debug architecture (ARMv8-M)" },
900 { ARCH_ID(ARM_ID
, 0x6A05), "Processor debug architecture (ARMv8-R)" },
901 { ARCH_ID(ARM_ID
, 0x0A10), "PC sample-based profiling" },
902 { ARCH_ID(ARM_ID
, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
903 { ARCH_ID(ARM_ID
, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
904 { ARCH_ID(ARM_ID
, 0x6A15), "Processor debug architecture (v8.0-A)" },
905 { ARCH_ID(ARM_ID
, 0x7A15), "Processor debug architecture (v8.1-A)" },
906 { ARCH_ID(ARM_ID
, 0x8A15), "Processor debug architecture (v8.2-A)" },
907 { ARCH_ID(ARM_ID
, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
908 { ARCH_ID(ARM_ID
, 0x0A17), "Memory Access Port v2 architecture" },
909 { ARCH_ID(ARM_ID
, 0x0A27), "JTAG Access Port v2 architecture" },
910 { ARCH_ID(ARM_ID
, 0x0A31), "Basic trace router" },
911 { ARCH_ID(ARM_ID
, 0x0A37), "Power requestor" },
912 { ARCH_ID(ARM_ID
, 0x0A47), "Unknown Access Port v2 architecture" },
913 { ARCH_ID(ARM_ID
, 0x0A50), "HSSTP architecture" },
914 { ARCH_ID(ARM_ID
, 0x0A63), "System Trace Macrocell (STM) architecture" },
915 { ARCH_ID(ARM_ID
, 0x0A75), "CoreSight ELA architecture" },
916 { ARCH_ID(ARM_ID
, 0x0AF7), "CoreSight ROM architecture" },
919 #define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
920 #define DEVARCH_MEM_AP ARCH_ID(ARM_ID, 0x0A17)
921 #define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
922 #define DEVARCH_UNKNOWN_V2 ARCH_ID(ARM_ID, 0x0A47)
924 static const char *class0x9_devarch_description(uint32_t devarch
)
926 if (!(devarch
& ARM_CS_C9_DEVARCH_PRESENT
))
927 return "not present";
929 for (unsigned int i
= 0; i
< ARRAY_SIZE(class0x9_devarch
); i
++)
930 if ((devarch
& DEVARCH_ID_MASK
) == class0x9_devarch
[i
].arch_id
)
931 return class0x9_devarch
[i
].description
;
936 static const struct {
938 const char *description
;
940 { AP_TYPE_JTAG_AP
, "JTAG-AP" },
941 { AP_TYPE_COM_AP
, "COM-AP" },
942 { AP_TYPE_AHB3_AP
, "MEM-AP AHB3" },
943 { AP_TYPE_APB_AP
, "MEM-AP APB2 or APB3" },
944 { AP_TYPE_AXI_AP
, "MEM-AP AXI3 or AXI4" },
945 { AP_TYPE_AHB5_AP
, "MEM-AP AHB5" },
946 { AP_TYPE_APB4_AP
, "MEM-AP APB4" },
947 { AP_TYPE_AXI5_AP
, "MEM-AP AXI5" },
948 { AP_TYPE_AHB5H_AP
, "MEM-AP AHB5 with enhanced HPROT" },
951 static const char *ap_type_to_description(enum ap_type type
)
953 for (unsigned int i
= 0; i
< ARRAY_SIZE(ap_types
); i
++)
954 if (type
== ap_types
[i
].type
)
955 return ap_types
[i
].description
;
960 bool is_ap_num_valid(struct adiv5_dap
*dap
, uint64_t ap_num
)
965 /* no autodetection, by now, so uninitialized is equivalent to ADIv5 for
966 * backward compatibility */
967 if (!is_adiv6(dap
)) {
968 if (ap_num
> DP_APSEL_MAX
)
974 if (ap_num
& 0x0fffULL
)
977 if (ap_num
& ((~0ULL) << dap
->asize
))
986 * This function checks the ID for each access port to find the requested Access Port type
987 * It also calls dap_get_ap() to increment the AP refcount
989 int dap_find_get_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
992 /* TODO: scan the ROM table and detect the AP available */
993 LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
997 /* Maximum AP number is 255 since the SELECT register is 8 bits */
998 for (unsigned int ap_num
= 0; ap_num
<= DP_APSEL_MAX
; ap_num
++) {
999 struct adiv5_ap
*ap
= dap_get_ap(dap
, ap_num
);
1003 /* read the IDR register of the Access Port */
1004 uint32_t id_val
= 0;
1006 int retval
= dap_queue_ap_read(ap
, AP_REG_IDR(dap
), &id_val
);
1007 if (retval
!= ERROR_OK
) {
1012 retval
= dap_run(dap
);
1014 /* Reading register for a non-existent AP should not cause an error,
1015 * but just to be sure, try to continue searching if an error does happen.
1017 if (retval
== ERROR_OK
&& (id_val
& AP_TYPE_MASK
) == type_to_find
) {
1018 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
1019 ap_type_to_description(type_to_find
),
1028 LOG_DEBUG("No %s found", ap_type_to_description(type_to_find
));
1032 static inline bool is_ap_in_use(struct adiv5_ap
*ap
)
1034 return ap
->refcount
> 0 || ap
->config_ap_never_release
;
1037 static struct adiv5_ap
*_dap_get_ap(struct adiv5_dap
*dap
, uint64_t ap_num
)
1039 if (!is_ap_num_valid(dap
, ap_num
)) {
1040 LOG_ERROR("Invalid AP#0x%" PRIx64
, ap_num
);
1043 if (is_adiv6(dap
)) {
1044 for (unsigned int i
= 0; i
<= DP_APSEL_MAX
; i
++) {
1045 struct adiv5_ap
*ap
= &dap
->ap
[i
];
1046 if (is_ap_in_use(ap
) && ap
->ap_num
== ap_num
) {
1051 for (unsigned int i
= 0; i
<= DP_APSEL_MAX
; i
++) {
1052 struct adiv5_ap
*ap
= &dap
->ap
[i
];
1053 if (!is_ap_in_use(ap
)) {
1054 ap
->ap_num
= ap_num
;
1059 LOG_ERROR("No more AP available!");
1064 struct adiv5_ap
*ap
= &dap
->ap
[ap_num
];
1065 ap
->ap_num
= ap_num
;
1070 /* Return AP with specified ap_num. Increment AP refcount */
1071 struct adiv5_ap
*dap_get_ap(struct adiv5_dap
*dap
, uint64_t ap_num
)
1073 struct adiv5_ap
*ap
= _dap_get_ap(dap
, ap_num
);
1075 LOG_DEBUG("refcount AP#0x%" PRIx64
" get %u", ap_num
, ap
->refcount
);
1079 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
1080 struct adiv5_ap
*dap_get_config_ap(struct adiv5_dap
*dap
, uint64_t ap_num
)
1082 struct adiv5_ap
*ap
= _dap_get_ap(dap
, ap_num
);
1084 ap
->config_ap_never_release
= true;
1085 LOG_DEBUG("refcount AP#0x%" PRIx64
" get_config %u", ap_num
, ap
->refcount
);
1090 /* Decrement AP refcount and release the AP when refcount reaches zero */
1091 int dap_put_ap(struct adiv5_ap
*ap
)
1093 if (ap
->refcount
== 0) {
1094 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" put underflow", ap
->ap_num
);
1100 LOG_DEBUG("refcount AP#0x%" PRIx64
" put %u", ap
->ap_num
, ap
->refcount
);
1101 if (!is_ap_in_use(ap
)) {
1102 /* defaults from dap_instance_init() */
1103 ap
->ap_num
= DP_APSEL_INVALID
;
1104 ap
->memaccess_tck
= 255;
1105 ap
->tar_autoincr_block
= (1 << 10);
1106 ap
->csw_default
= CSW_AHB_DEFAULT
;
1107 ap
->cfg_reg
= MEM_AP_REG_CFG_INVALID
;
1112 static int dap_get_debugbase(struct adiv5_ap
*ap
,
1113 target_addr_t
*dbgbase
, uint32_t *apid
)
1115 struct adiv5_dap
*dap
= ap
->dap
;
1117 uint32_t baseptr_upper
, baseptr_lower
;
1119 if (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
) {
1120 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG(dap
), &ap
->cfg_reg
);
1121 if (retval
!= ERROR_OK
)
1124 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE(dap
), &baseptr_lower
);
1125 if (retval
!= ERROR_OK
)
1127 retval
= dap_queue_ap_read(ap
, AP_REG_IDR(dap
), apid
);
1128 if (retval
!= ERROR_OK
)
1130 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1131 if (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
|| is_64bit_ap(ap
)) {
1132 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE64(dap
), &baseptr_upper
);
1133 if (retval
!= ERROR_OK
)
1137 retval
= dap_run(dap
);
1138 if (retval
!= ERROR_OK
)
1141 if (!is_64bit_ap(ap
))
1143 *dbgbase
= (((target_addr_t
)baseptr_upper
) << 32) | baseptr_lower
;
1148 int adiv6_dap_read_baseptr(struct command_invocation
*cmd
, struct adiv5_dap
*dap
, uint64_t *baseptr
)
1150 uint32_t baseptr_lower
, baseptr_upper
= 0;
1153 if (dap
->asize
> 32) {
1154 retval
= dap_queue_dp_read(dap
, DP_BASEPTR1
, &baseptr_upper
);
1155 if (retval
!= ERROR_OK
)
1159 retval
= dap_dp_read_atomic(dap
, DP_BASEPTR0
, &baseptr_lower
);
1160 if (retval
!= ERROR_OK
)
1163 if ((baseptr_lower
& DP_BASEPTR0_VALID
) != DP_BASEPTR0_VALID
) {
1164 command_print(cmd
, "System root table not present");
1168 baseptr_lower
&= ~0x0fff;
1169 *baseptr
= (((uint64_t)baseptr_upper
) << 32) | baseptr_lower
;
1175 * Method to access the CoreSight component.
1176 * On ADIv5, CoreSight components are on the bus behind a MEM-AP.
1177 * On ADIv6, CoreSight components can either be on the bus behind a MEM-AP
1178 * or directly in the AP.
1180 enum coresight_access_mode
{
1185 /** Holds registers and coordinates of a CoreSight component */
1186 struct cs_component_vals
{
1187 struct adiv5_ap
*ap
;
1188 target_addr_t component_base
;
1193 uint32_t devtype_memtype
;
1194 enum coresight_access_mode mode
;
1198 * Helper to read CoreSight component's registers, either on the bus
1199 * behind a MEM-AP or directly in the AP.
1201 * @param mode Method to access the component (AP or MEM-AP).
1202 * @param ap Pointer to AP containing the component.
1203 * @param component_base On MEM-AP access method, base address of the component.
1204 * @param reg Offset of the component's register to read.
1205 * @param value Pointer to the store the read value.
1207 * @return ERROR_OK on success, else a fault code.
1209 static int dap_queue_read_reg(enum coresight_access_mode mode
, struct adiv5_ap
*ap
,
1210 uint64_t component_base
, unsigned int reg
, uint32_t *value
)
1212 if (mode
== CS_ACCESS_AP
)
1213 return dap_queue_ap_read(ap
, reg
, value
);
1215 /* mode == CS_ACCESS_MEM_AP */
1216 return mem_ap_read_u32(ap
, component_base
+ reg
, value
);
1220 * Read the CoreSight registers needed during ROM Table Parsing (RTP).
1222 * @param mode Method to access the component (AP or MEM-AP).
1223 * @param ap Pointer to AP containing the component.
1224 * @param component_base On MEM-AP access method, base address of the component.
1225 * @param v Pointer to the struct holding the value of registers.
1227 * @return ERROR_OK on success, else a fault code.
1229 static int rtp_read_cs_regs(enum coresight_access_mode mode
, struct adiv5_ap
*ap
,
1230 target_addr_t component_base
, struct cs_component_vals
*v
)
1232 assert(IS_ALIGNED(component_base
, ARM_CS_ALIGN
));
1235 uint32_t cid0
, cid1
, cid2
, cid3
;
1236 uint32_t pid0
, pid1
, pid2
, pid3
, pid4
;
1237 int retval
= ERROR_OK
;
1240 v
->component_base
= component_base
;
1243 /* sort by offset to gain speed */
1246 * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices
1247 * only, but are at offset above 0xf00, so can be read on any device
1248 * without triggering error. Read them for eventual use on Class 0x9.
1250 if (retval
== ERROR_OK
)
1251 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_C9_DEVARCH
, &v
->devarch
);
1253 if (retval
== ERROR_OK
)
1254 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_C9_DEVID
, &v
->devid
);
1256 /* Same address as ARM_CS_C1_MEMTYPE */
1257 if (retval
== ERROR_OK
)
1258 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_C9_DEVTYPE
, &v
->devtype_memtype
);
1260 if (retval
== ERROR_OK
)
1261 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR4
, &pid4
);
1263 if (retval
== ERROR_OK
)
1264 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR0
, &pid0
);
1265 if (retval
== ERROR_OK
)
1266 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR1
, &pid1
);
1267 if (retval
== ERROR_OK
)
1268 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR2
, &pid2
);
1269 if (retval
== ERROR_OK
)
1270 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR3
, &pid3
);
1272 if (retval
== ERROR_OK
)
1273 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR0
, &cid0
);
1274 if (retval
== ERROR_OK
)
1275 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR1
, &cid1
);
1276 if (retval
== ERROR_OK
)
1277 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR2
, &cid2
);
1278 if (retval
== ERROR_OK
)
1279 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR3
, &cid3
);
1281 if (retval
== ERROR_OK
)
1282 retval
= dap_run(ap
->dap
);
1283 if (retval
!= ERROR_OK
) {
1284 LOG_DEBUG("Failed read CoreSight registers");
1288 v
->cid
= (cid3
& 0xff) << 24
1289 | (cid2
& 0xff) << 16
1290 | (cid1
& 0xff) << 8
1292 v
->pid
= (uint64_t)(pid4
& 0xff) << 32
1293 | (pid3
& 0xff) << 24
1294 | (pid2
& 0xff) << 16
1295 | (pid1
& 0xff) << 8
1301 /* Part number interpretations are from Cortex
1302 * core specs, the CoreSight components TRM
1303 * (ARM DDI 0314H), CoreSight System Design
1304 * Guide (ARM DGI 0012D) and ETM specs; also
1305 * from chip observation (e.g. TI SDTI).
1308 static const struct dap_part_nums
{
1309 uint16_t designer_id
;
1313 } dap_part_nums
[] = {
1314 { ARM_ID
, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1315 { ARM_ID
, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1316 { ARM_ID
, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1317 { ARM_ID
, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1318 { ARM_ID
, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1319 { ARM_ID
, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1320 { ARM_ID
, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1321 { ARM_ID
, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1322 { ARM_ID
, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1323 { ARM_ID
, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1324 { ARM_ID
, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
1325 { ARM_ID
, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1326 { ARM_ID
, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1327 { ARM_ID
, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1328 { ARM_ID
, 0x492, "Cortex-R52 GICD", "(Distributor)", },
1329 { ARM_ID
, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
1330 { ARM_ID
, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1331 { ARM_ID
, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1332 { ARM_ID
, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1333 { ARM_ID
, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1334 { ARM_ID
, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1335 { ARM_ID
, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1336 { ARM_ID
, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1337 { ARM_ID
, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1338 { ARM_ID
, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
1339 { ARM_ID
, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1340 { ARM_ID
, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1341 { ARM_ID
, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1342 { ARM_ID
, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1343 { ARM_ID
, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1344 { ARM_ID
, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1345 { ARM_ID
, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
1346 { ARM_ID
, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1347 { ARM_ID
, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1348 { ARM_ID
, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1349 { ARM_ID
, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1350 { ARM_ID
, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1351 { ARM_ID
, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1352 { ARM_ID
, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1353 { ARM_ID
, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1354 { ARM_ID
, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1355 { ARM_ID
, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1356 { ARM_ID
, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1357 { ARM_ID
, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1358 { ARM_ID
, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1359 { ARM_ID
, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1360 { ARM_ID
, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1361 { ARM_ID
, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1362 { ARM_ID
, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1363 { ARM_ID
, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1364 { ARM_ID
, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1365 { ARM_ID
, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1366 { ARM_ID
, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1367 { ARM_ID
, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1368 { ARM_ID
, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1369 { ARM_ID
, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1370 { ARM_ID
, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1371 { ARM_ID
, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1372 { ARM_ID
, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1373 { ARM_ID
, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1374 { ARM_ID
, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1375 { ARM_ID
, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1376 { ARM_ID
, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1377 { ARM_ID
, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1378 { ARM_ID
, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1379 { ARM_ID
, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1380 { ARM_ID
, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1381 { ARM_ID
, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1382 { ARM_ID
, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1383 { ARM_ID
, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1384 { ARM_ID
, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1385 { ARM_ID
, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1386 { ARM_ID
, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1387 { ARM_ID
, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1388 { ARM_ID
, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1389 { ARM_ID
, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1390 { ARM_ID
, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
1391 { ARM_ID
, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
1392 { ARM_ID
, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
1393 { ARM_ID
, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
1394 { ARM_ID
, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
1395 { ARM_ID
, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
1396 { ARM_ID
, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
1397 { ARM_ID
, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
1398 { ARM_ID
, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
1399 { ARM_ID
, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
1400 { ARM_ID
, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
1401 { ARM_ID
, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
1402 { ARM_ID
, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
1403 { ARM_ID
, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1404 { ARM_ID
, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1405 { ARM_ID
, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1406 { ARM_ID
, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1407 { ARM_ID
, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1408 { ARM_ID
, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1409 { ARM_ID
, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1410 { ARM_ID
, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1411 { ARM_ID
, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1412 { ARM_ID
, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1413 { ARM_ID
, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1414 { ARM_ID
, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1415 { ARM_ID
, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1416 { ARM_ID
, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
1417 { ARM_ID
, 0xd0c, "Neoverse N1", "(Debug Unit)", },
1418 { ARM_ID
, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
1419 { ARM_ID
, 0xd49, "Neoverse N2", "(Debug Unit)", },
1420 { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1421 { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1422 { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
1423 { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1424 { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1425 { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1426 { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1427 { 0x065, 0x000, "SHARC+/Blackfin+", "", },
1428 { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1429 { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
1430 { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
1431 { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
1432 { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
1433 { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1434 { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1435 { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1436 { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
1437 { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1440 static const struct dap_part_nums
*pidr_to_part_num(unsigned int designer_id
, unsigned int part_num
)
1442 static const struct dap_part_nums unknown
= {
1443 .type
= "Unrecognized",
1447 for (unsigned int i
= 0; i
< ARRAY_SIZE(dap_part_nums
); i
++)
1448 if (dap_part_nums
[i
].designer_id
== designer_id
&& dap_part_nums
[i
].part_num
== part_num
)
1449 return &dap_part_nums
[i
];
1454 static int dap_devtype_display(struct command_invocation
*cmd
, uint32_t devtype
)
1456 const char *major
= "Reserved", *subtype
= "Reserved";
1457 const unsigned int minor
= (devtype
& ARM_CS_C9_DEVTYPE_SUB_MASK
) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT
;
1458 const unsigned int devtype_major
= (devtype
& ARM_CS_C9_DEVTYPE_MAJOR_MASK
) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT
;
1459 switch (devtype_major
) {
1461 major
= "Miscellaneous";
1467 subtype
= "Validation component";
1472 major
= "Trace Sink";
1489 major
= "Trace Link";
1495 subtype
= "Funnel, router";
1501 subtype
= "FIFO, buffer";
1506 major
= "Trace Source";
1512 subtype
= "Processor";
1518 subtype
= "Engine/Coprocessor";
1524 subtype
= "Software";
1529 major
= "Debug Control";
1535 subtype
= "Trigger Matrix";
1538 subtype
= "Debug Auth";
1541 subtype
= "Power Requestor";
1546 major
= "Debug Logic";
1552 subtype
= "Processor";
1558 subtype
= "Engine/Coprocessor";
1569 major
= "Performance Monitor";
1575 subtype
= "Processor";
1581 subtype
= "Engine/Coprocessor";
1592 command_print(cmd
, "\t\tType is 0x%02x, %s, %s",
1593 devtype
& ARM_CS_C9_DEVTYPE_MASK
,
1599 * Actions/operations to be executed while parsing ROM tables.
1603 * Executed at the start of a new AP, typically to print the AP header.
1604 * @param ap Pointer to AP.
1605 * @param depth The current depth level of ROM table.
1606 * @param priv Pointer to private data.
1607 * @return ERROR_OK on success, else a fault code.
1609 int (*ap_header
)(struct adiv5_ap
*ap
, int depth
, void *priv
);
1611 * Executed at the start of a new MEM-AP, typically to print the MEM-AP header.
1612 * @param retval Error encountered while reading AP.
1613 * @param ap Pointer to AP.
1614 * @param dbgbase Value of MEM-AP Debug Base Address register.
1615 * @param apid Value of MEM-AP IDR Identification Register.
1616 * @param depth The current depth level of ROM table.
1617 * @param priv Pointer to private data.
1618 * @return ERROR_OK on success, else a fault code.
1620 int (*mem_ap_header
)(int retval
, struct adiv5_ap
*ap
, uint64_t dbgbase
,
1621 uint32_t apid
, int depth
, void *priv
);
1623 * Executed when a CoreSight component is parsed, typically to print
1624 * information on the component.
1625 * @param retval Error encountered while reading component's registers.
1626 * @param v Pointer to a container of the component's registers.
1627 * @param depth The current depth level of ROM table.
1628 * @param priv Pointer to private data.
1629 * @return ERROR_OK on success, else a fault code.
1631 int (*cs_component
)(int retval
, struct cs_component_vals
*v
, int depth
, void *priv
);
1633 * Executed for each entry of a ROM table, typically to print the entry
1634 * and information about validity or end-of-table mark.
1635 * @param retval Error encountered while reading the ROM table entry.
1636 * @param depth The current depth level of ROM table.
1637 * @param offset The offset of the entry in the ROM table.
1638 * @param romentry The value of the ROM table entry.
1639 * @param priv Pointer to private data.
1640 * @return ERROR_OK on success, else a fault code.
1642 int (*rom_table_entry
)(int retval
, int depth
, unsigned int offset
, uint64_t romentry
,
1651 * Wrapper around struct rtp_ops::ap_header.
1653 static int rtp_ops_ap_header(const struct rtp_ops
*ops
,
1654 struct adiv5_ap
*ap
, int depth
)
1657 return ops
->ap_header(ap
, depth
, ops
->priv
);
1663 * Wrapper around struct rtp_ops::mem_ap_header.
1664 * Input parameter @a retval is propagated.
1666 static int rtp_ops_mem_ap_header(const struct rtp_ops
*ops
,
1667 int retval
, struct adiv5_ap
*ap
, uint64_t dbgbase
, uint32_t apid
, int depth
)
1669 if (!ops
->mem_ap_header
)
1672 int retval1
= ops
->mem_ap_header(retval
, ap
, dbgbase
, apid
, depth
, ops
->priv
);
1673 if (retval
!= ERROR_OK
)
1679 * Wrapper around struct rtp_ops::cs_component.
1680 * Input parameter @a retval is propagated.
1682 static int rtp_ops_cs_component(const struct rtp_ops
*ops
,
1683 int retval
, struct cs_component_vals
*v
, int depth
)
1685 if (!ops
->cs_component
)
1688 int retval1
= ops
->cs_component(retval
, v
, depth
, ops
->priv
);
1689 if (retval
!= ERROR_OK
)
1695 * Wrapper around struct rtp_ops::rom_table_entry.
1696 * Input parameter @a retval is propagated.
1698 static int rtp_ops_rom_table_entry(const struct rtp_ops
*ops
,
1699 int retval
, int depth
, unsigned int offset
, uint64_t romentry
)
1701 if (!ops
->rom_table_entry
)
1704 int retval1
= ops
->rom_table_entry(retval
, depth
, offset
, romentry
, ops
->priv
);
1705 if (retval
!= ERROR_OK
)
1710 /* Broken ROM tables can have circular references. Stop after a while */
1711 #define ROM_TABLE_MAX_DEPTH (16)
1714 * Value used only during lookup of a CoreSight component in ROM table.
1715 * Return CORESIGHT_COMPONENT_FOUND when component is found.
1716 * Return ERROR_OK when component is not found yet.
1717 * Return any other ERROR_* in case of error.
1719 #define CORESIGHT_COMPONENT_FOUND (1)
1721 static int rtp_ap(const struct rtp_ops
*ops
, struct adiv5_ap
*ap
, int depth
);
1722 static int rtp_cs_component(enum coresight_access_mode mode
, const struct rtp_ops
*ops
,
1723 struct adiv5_ap
*ap
, target_addr_t dbgbase
, bool *is_mem_ap
, int depth
);
1725 static int rtp_rom_loop(enum coresight_access_mode mode
, const struct rtp_ops
*ops
,
1726 struct adiv5_ap
*ap
, target_addr_t base_address
, int depth
,
1727 unsigned int width
, unsigned int max_entries
)
1729 /* ADIv6 AP ROM table provide offset from current AP */
1730 if (mode
== CS_ACCESS_AP
)
1731 base_address
= ap
->ap_num
;
1733 assert(IS_ALIGNED(base_address
, ARM_CS_ALIGN
));
1735 unsigned int offset
= 0;
1736 while (max_entries
--) {
1738 uint32_t romentry_low
, romentry_high
;
1739 target_addr_t component_base
;
1740 unsigned int saved_offset
= offset
;
1742 int retval
= dap_queue_read_reg(mode
, ap
, base_address
, offset
, &romentry_low
);
1744 if (retval
== ERROR_OK
&& width
== 64) {
1745 retval
= dap_queue_read_reg(mode
, ap
, base_address
, offset
, &romentry_high
);
1748 if (retval
== ERROR_OK
)
1749 retval
= dap_run(ap
->dap
);
1750 if (retval
!= ERROR_OK
) {
1751 LOG_DEBUG("Failed read ROM table entry");
1756 romentry
= (((uint64_t)romentry_high
) << 32) | romentry_low
;
1757 component_base
= base_address
+
1758 ((((uint64_t)romentry_high
) << 32) | (romentry_low
& ARM_CS_ROMENTRY_OFFSET_MASK
));
1760 romentry
= romentry_low
;
1761 /* "romentry" is signed */
1762 component_base
= base_address
+ (int32_t)(romentry_low
& ARM_CS_ROMENTRY_OFFSET_MASK
);
1763 if (!is_64bit_ap(ap
))
1764 component_base
= (uint32_t)component_base
;
1766 retval
= rtp_ops_rom_table_entry(ops
, retval
, depth
, saved_offset
, romentry
);
1767 if (retval
!= ERROR_OK
)
1770 if (romentry
== 0) {
1771 /* End of ROM table */
1775 if (!(romentry
& ARM_CS_ROMENTRY_PRESENT
))
1779 if (mode
== CS_ACCESS_AP
) {
1780 struct adiv5_ap
*next_ap
= dap_get_ap(ap
->dap
, component_base
);
1782 LOG_DEBUG("Wrong AP # 0x%" PRIx64
, component_base
);
1785 retval
= rtp_ap(ops
, next_ap
, depth
+ 1);
1786 dap_put_ap(next_ap
);
1788 /* mode == CS_ACCESS_MEM_AP */
1789 retval
= rtp_cs_component(mode
, ops
, ap
, component_base
, NULL
, depth
+ 1);
1791 if (retval
== CORESIGHT_COMPONENT_FOUND
)
1792 return CORESIGHT_COMPONENT_FOUND
;
1793 if (retval
!= ERROR_OK
) {
1794 /* TODO: do we need to send an ABORT before continuing? */
1795 LOG_DEBUG("Ignore error parsing CoreSight component");
1803 static int rtp_cs_component(enum coresight_access_mode mode
, const struct rtp_ops
*ops
,
1804 struct adiv5_ap
*ap
, target_addr_t base_address
, bool *is_mem_ap
, int depth
)
1806 struct cs_component_vals v
;
1809 assert(IS_ALIGNED(base_address
, ARM_CS_ALIGN
));
1814 if (depth
> ROM_TABLE_MAX_DEPTH
)
1815 retval
= ERROR_FAIL
;
1817 retval
= rtp_read_cs_regs(mode
, ap
, base_address
, &v
);
1819 retval
= rtp_ops_cs_component(ops
, retval
, &v
, depth
);
1820 if (retval
== CORESIGHT_COMPONENT_FOUND
)
1821 return CORESIGHT_COMPONENT_FOUND
;
1822 if (retval
!= ERROR_OK
)
1823 return ERROR_OK
; /* Don't abort recursion */
1825 if (!is_valid_arm_cs_cidr(v
.cid
))
1826 return ERROR_OK
; /* Don't abort recursion */
1828 const unsigned int class = ARM_CS_CIDR_CLASS(v
.cid
);
1830 if (class == ARM_CS_CLASS_0X1_ROM_TABLE
)
1831 return rtp_rom_loop(mode
, ops
, ap
, base_address
, depth
, 32, 960);
1833 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT
) {
1834 if ((v
.devarch
& ARM_CS_C9_DEVARCH_PRESENT
) == 0)
1838 if ((v
.devarch
& DEVARCH_ID_MASK
) == DEVARCH_MEM_AP
)
1841 /* SoC-600 APv1 Adapter */
1842 if ((v
.devarch
& DEVARCH_ID_MASK
) == DEVARCH_UNKNOWN_V2
&&
1843 ARM_CS_PIDR_DESIGNER(v
.pid
) == ARM_ID
&&
1844 ARM_CS_PIDR_PART(v
.pid
) == 0x9e5)
1848 /* quit if not ROM table */
1849 if ((v
.devarch
& DEVARCH_ID_MASK
) != DEVARCH_ROM_C_0X9
)
1852 if ((v
.devid
& ARM_CS_C9_DEVID_FORMAT_MASK
) == ARM_CS_C9_DEVID_FORMAT_64BIT
)
1853 return rtp_rom_loop(mode
, ops
, ap
, base_address
, depth
, 64, 256);
1855 return rtp_rom_loop(mode
, ops
, ap
, base_address
, depth
, 32, 512);
1858 /* Class other than 0x1 and 0x9 */
1862 static int rtp_ap(const struct rtp_ops
*ops
, struct adiv5_ap
*ap
, int depth
)
1865 target_addr_t dbgbase
, invalid_entry
;
1867 int retval
= rtp_ops_ap_header(ops
, ap
, depth
);
1868 if (retval
!= ERROR_OK
|| depth
> ROM_TABLE_MAX_DEPTH
)
1869 return ERROR_OK
; /* Don't abort recursion */
1871 if (is_adiv6(ap
->dap
)) {
1873 retval
= rtp_cs_component(CS_ACCESS_AP
, ops
, ap
, 0, &is_mem_ap
, depth
);
1874 if (retval
== CORESIGHT_COMPONENT_FOUND
)
1875 return CORESIGHT_COMPONENT_FOUND
;
1876 if (retval
!= ERROR_OK
)
1877 return ERROR_OK
; /* Don't abort recursion */
1881 /* Continue for an ADIv6 MEM-AP or SoC-600 APv1 Adapter */
1884 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1885 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
1886 if (retval
!= ERROR_OK
)
1888 retval
= rtp_ops_mem_ap_header(ops
, retval
, ap
, dbgbase
, apid
, depth
);
1889 if (retval
!= ERROR_OK
)
1895 /* NOTE: a MEM-AP may have a single CoreSight component that's
1896 * not a ROM table ... or have no such components at all.
1898 const unsigned int class = (apid
& AP_REG_IDR_CLASS_MASK
) >> AP_REG_IDR_CLASS_SHIFT
;
1900 if (class == AP_REG_IDR_CLASS_MEM_AP
) {
1901 if (is_64bit_ap(ap
))
1902 invalid_entry
= 0xFFFFFFFFFFFFFFFFull
;
1904 invalid_entry
= 0xFFFFFFFFul
;
1906 if (dbgbase
!= invalid_entry
&& (dbgbase
& 0x3) != 0x2) {
1907 retval
= rtp_cs_component(CS_ACCESS_MEM_AP
, ops
, ap
,
1908 dbgbase
& 0xFFFFFFFFFFFFF000ull
, NULL
, depth
);
1909 if (retval
== CORESIGHT_COMPONENT_FOUND
)
1910 return CORESIGHT_COMPONENT_FOUND
;
1917 /* Actions for command "dap info" */
1919 static int dap_info_ap_header(struct adiv5_ap
*ap
, int depth
, void *priv
)
1921 struct command_invocation
*cmd
= priv
;
1923 if (depth
> ROM_TABLE_MAX_DEPTH
) {
1924 command_print(cmd
, "\tTables too deep");
1928 command_print(cmd
, "%sAP # 0x%" PRIx64
, (depth
) ? "\t\t" : "", ap
->ap_num
);
1932 static int dap_info_mem_ap_header(int retval
, struct adiv5_ap
*ap
,
1933 target_addr_t dbgbase
, uint32_t apid
, int depth
, void *priv
)
1935 struct command_invocation
*cmd
= priv
;
1936 target_addr_t invalid_entry
;
1939 if (retval
!= ERROR_OK
) {
1940 command_print(cmd
, "\t\tCan't read MEM-AP, the corresponding core might be turned off");
1944 if (depth
> ROM_TABLE_MAX_DEPTH
) {
1945 command_print(cmd
, "\tTables too deep");
1950 snprintf(tabs
, sizeof(tabs
), "\t[L%02d] ", depth
);
1952 command_print(cmd
, "\t\tAP ID register 0x%8.8" PRIx32
, apid
);
1954 command_print(cmd
, "\t\tNo AP found at this AP#0x%" PRIx64
, ap
->ap_num
);
1958 command_print(cmd
, "\t\tType is %s", ap_type_to_description(apid
& AP_TYPE_MASK
));
1960 /* NOTE: a MEM-AP may have a single CoreSight component that's
1961 * not a ROM table ... or have no such components at all.
1963 const unsigned int class = (apid
& AP_REG_IDR_CLASS_MASK
) >> AP_REG_IDR_CLASS_SHIFT
;
1965 if (class == AP_REG_IDR_CLASS_MEM_AP
) {
1966 if (is_64bit_ap(ap
))
1967 invalid_entry
= 0xFFFFFFFFFFFFFFFFull
;
1969 invalid_entry
= 0xFFFFFFFFul
;
1971 command_print(cmd
, "%sMEM-AP BASE " TARGET_ADDR_FMT
, tabs
, dbgbase
);
1973 if (dbgbase
== invalid_entry
|| (dbgbase
& 0x3) == 0x2) {
1974 command_print(cmd
, "\t\tNo ROM table present");
1977 command_print(cmd
, "\t\tValid ROM table present");
1979 command_print(cmd
, "\t\tROM table in legacy format");
1986 static int dap_info_cs_component(int retval
, struct cs_component_vals
*v
, int depth
, void *priv
)
1988 struct command_invocation
*cmd
= priv
;
1990 if (depth
> ROM_TABLE_MAX_DEPTH
) {
1991 command_print(cmd
, "\tTables too deep");
1995 if (v
->mode
== CS_ACCESS_MEM_AP
)
1996 command_print(cmd
, "\t\tComponent base address " TARGET_ADDR_FMT
, v
->component_base
);
1998 if (retval
!= ERROR_OK
) {
1999 command_print(cmd
, "\t\tCan't read component, the corresponding core might be turned off");
2003 if (!is_valid_arm_cs_cidr(v
->cid
)) {
2004 command_print(cmd
, "\t\tInvalid CID 0x%08" PRIx32
, v
->cid
);
2005 return ERROR_OK
; /* Don't abort recursion */
2008 /* component may take multiple 4K pages */
2009 uint32_t size
= ARM_CS_PIDR_SIZE(v
->pid
);
2011 command_print(cmd
, "\t\tStart address " TARGET_ADDR_FMT
, v
->component_base
- 0x1000 * size
);
2013 command_print(cmd
, "\t\tPeripheral ID 0x%010" PRIx64
, v
->pid
);
2015 const unsigned int part_num
= ARM_CS_PIDR_PART(v
->pid
);
2016 unsigned int designer_id
= ARM_CS_PIDR_DESIGNER(v
->pid
);
2018 if (v
->pid
& ARM_CS_PIDR_JEDEC
) {
2020 command_print(cmd
, "\t\tDesigner is 0x%03x, %s",
2021 designer_id
, jep106_manufacturer(designer_id
));
2023 /* Legacy ASCII ID, clear invalid bits */
2024 designer_id
&= 0x7f;
2025 command_print(cmd
, "\t\tDesigner ASCII code 0x%02x, %s",
2026 designer_id
, designer_id
== 0x41 ? "ARM" : "<unknown>");
2029 const struct dap_part_nums
*partnum
= pidr_to_part_num(designer_id
, part_num
);
2030 command_print(cmd
, "\t\tPart is 0x%03x, %s %s", part_num
, partnum
->type
, partnum
->full
);
2032 const unsigned int class = ARM_CS_CIDR_CLASS(v
->cid
);
2033 command_print(cmd
, "\t\tComponent class is 0x%x, %s", class, class_description
[class]);
2035 if (class == ARM_CS_CLASS_0X1_ROM_TABLE
) {
2036 if (v
->devtype_memtype
& ARM_CS_C1_MEMTYPE_SYSMEM_MASK
)
2037 command_print(cmd
, "\t\tMEMTYPE system memory present on bus");
2039 command_print(cmd
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
2043 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT
) {
2044 dap_devtype_display(cmd
, v
->devtype_memtype
);
2046 /* REVISIT also show ARM_CS_C9_DEVID */
2048 if ((v
->devarch
& ARM_CS_C9_DEVARCH_PRESENT
) == 0)
2051 unsigned int architect_id
= ARM_CS_C9_DEVARCH_ARCHITECT(v
->devarch
);
2052 unsigned int revision
= ARM_CS_C9_DEVARCH_REVISION(v
->devarch
);
2053 command_print(cmd
, "\t\tDev Arch is 0x%08" PRIx32
", %s \"%s\" rev.%u", v
->devarch
,
2054 jep106_manufacturer(architect_id
), class0x9_devarch_description(v
->devarch
),
2057 if ((v
->devarch
& DEVARCH_ID_MASK
) == DEVARCH_ROM_C_0X9
) {
2058 command_print(cmd
, "\t\tType is ROM table");
2060 if (v
->devid
& ARM_CS_C9_DEVID_SYSMEM_MASK
)
2061 command_print(cmd
, "\t\tMEMTYPE system memory present on bus");
2063 command_print(cmd
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
2068 /* Class other than 0x1 and 0x9 */
2072 static int dap_info_rom_table_entry(int retval
, int depth
,
2073 unsigned int offset
, uint64_t romentry
, void *priv
)
2075 struct command_invocation
*cmd
= priv
;
2079 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
2081 if (retval
!= ERROR_OK
) {
2082 command_print(cmd
, "\t%sROMTABLE[0x%x] Read error", tabs
, offset
);
2083 command_print(cmd
, "\t\tUnable to continue");
2084 command_print(cmd
, "\t%s\tStop parsing of ROM table", tabs
);
2088 command_print(cmd
, "\t%sROMTABLE[0x%x] = 0x%08" PRIx64
,
2089 tabs
, offset
, romentry
);
2091 if (romentry
== 0) {
2092 command_print(cmd
, "\t%s\tEnd of ROM table", tabs
);
2096 if (!(romentry
& ARM_CS_ROMENTRY_PRESENT
)) {
2097 command_print(cmd
, "\t\tComponent not present");
2104 int dap_info_command(struct command_invocation
*cmd
, struct adiv5_ap
*ap
)
2106 struct rtp_ops dap_info_ops
= {
2107 .ap_header
= dap_info_ap_header
,
2108 .mem_ap_header
= dap_info_mem_ap_header
,
2109 .cs_component
= dap_info_cs_component
,
2110 .rom_table_entry
= dap_info_rom_table_entry
,
2114 return rtp_ap(&dap_info_ops
, ap
, 0);
2117 /* Actions for dap_lookup_cs_component() */
2119 struct dap_lookup_data
{
2124 uint64_t component_base
;
2128 static int dap_lookup_cs_component_cs_component(int retval
,
2129 struct cs_component_vals
*v
, int depth
, void *priv
)
2131 struct dap_lookup_data
*lookup
= priv
;
2133 if (retval
!= ERROR_OK
)
2136 if (!is_valid_arm_cs_cidr(v
->cid
))
2139 const unsigned int class = ARM_CS_CIDR_CLASS(v
->cid
);
2140 if (class != ARM_CS_CLASS_0X9_CS_COMPONENT
)
2143 if ((v
->devtype_memtype
& ARM_CS_C9_DEVTYPE_MASK
) != lookup
->type
)
2147 /* search for next one */
2153 lookup
->component_base
= v
->component_base
;
2154 lookup
->ap_num
= v
->ap
->ap_num
;
2155 return CORESIGHT_COMPONENT_FOUND
;
2158 int dap_lookup_cs_component(struct adiv5_ap
*ap
, uint8_t type
,
2159 target_addr_t
*addr
, int32_t core_id
)
2161 struct dap_lookup_data lookup
= {
2165 struct rtp_ops dap_lookup_cs_component_ops
= {
2167 .mem_ap_header
= NULL
,
2168 .cs_component
= dap_lookup_cs_component_cs_component
,
2169 .rom_table_entry
= NULL
,
2173 int retval
= rtp_ap(&dap_lookup_cs_component_ops
, ap
, 0);
2174 if (retval
== CORESIGHT_COMPONENT_FOUND
) {
2175 if (lookup
.ap_num
!= ap
->ap_num
) {
2176 /* TODO: handle search from root ROM table */
2177 LOG_DEBUG("CS lookup ended in AP # 0x%" PRIx64
". Ignore it", lookup
.ap_num
);
2178 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2180 LOG_DEBUG("CS lookup found at 0x%" PRIx64
, lookup
.component_base
);
2181 *addr
= lookup
.component_base
;
2184 if (retval
!= ERROR_OK
) {
2185 LOG_DEBUG("CS lookup error %d", retval
);
2188 LOG_DEBUG("CS lookup not found");
2189 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2192 enum adiv5_cfg_param
{
2196 CFG_CTIBASE
, /* DEPRECATED */
2199 static const struct jim_nvp nvp_config_opts
[] = {
2200 { .name
= "-dap", .value
= CFG_DAP
},
2201 { .name
= "-ap-num", .value
= CFG_AP_NUM
},
2202 { .name
= "-baseaddr", .value
= CFG_BASEADDR
},
2203 { .name
= "-ctibase", .value
= CFG_CTIBASE
}, /* DEPRECATED */
2204 { .name
= NULL
, .value
= -1 }
2207 static int adiv5_jim_spot_configure(struct jim_getopt_info
*goi
,
2208 struct adiv5_dap
**dap_p
, uint64_t *ap_num_p
, uint32_t *base_p
)
2210 assert(dap_p
&& ap_num_p
);
2215 Jim_SetEmptyResult(goi
->interp
);
2218 int e
= jim_nvp_name2value_obj(goi
->interp
, nvp_config_opts
,
2221 return JIM_CONTINUE
;
2223 /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
2224 if (!base_p
&& (n
->value
== CFG_BASEADDR
|| n
->value
== CFG_CTIBASE
))
2225 return JIM_CONTINUE
;
2227 e
= jim_getopt_obj(goi
, NULL
);
2233 if (goi
->isconfigure
) {
2235 struct adiv5_dap
*dap
;
2236 e
= jim_getopt_obj(goi
, &o_t
);
2239 dap
= dap_instance_by_jim_obj(goi
->interp
, o_t
);
2241 Jim_SetResultString(goi
->interp
, "DAP name invalid!", -1);
2244 if (*dap_p
&& *dap_p
!= dap
) {
2245 Jim_SetResultString(goi
->interp
,
2246 "DAP assignment cannot be changed!", -1);
2254 Jim_SetResultString(goi
->interp
, "DAP not configured", -1);
2257 Jim_SetResultString(goi
->interp
, adiv5_dap_name(*dap_p
), -1);
2262 if (goi
->isconfigure
) {
2263 /* jim_wide is a signed 64 bits int, ap_num is unsigned with max 52 bits */
2265 e
= jim_getopt_wide(goi
, &ap_num
);
2268 /* we still don't know dap->adi_version */
2269 if (ap_num
< 0 || (ap_num
> DP_APSEL_MAX
&& (ap_num
& 0xfff))) {
2270 Jim_SetResultString(goi
->interp
, "Invalid AP number!", -1);
2277 if (*ap_num_p
== DP_APSEL_INVALID
) {
2278 Jim_SetResultString(goi
->interp
, "AP number not configured", -1);
2281 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, *ap_num_p
));
2286 LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
2289 if (goi
->isconfigure
) {
2291 e
= jim_getopt_wide(goi
, &base
);
2294 *base_p
= (uint32_t)base
;
2298 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, *base_p
));
2306 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
, "NO PARAMS");
2310 int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
)
2312 struct adiv5_private_config
*pc
;
2315 pc
= (struct adiv5_private_config
*)target
->private_config
;
2317 pc
= calloc(1, sizeof(struct adiv5_private_config
));
2319 LOG_ERROR("Out of memory");
2322 pc
->ap_num
= DP_APSEL_INVALID
;
2323 target
->private_config
= pc
;
2326 target
->has_dap
= true;
2328 e
= adiv5_jim_spot_configure(goi
, &pc
->dap
, &pc
->ap_num
, NULL
);
2332 if (pc
->dap
&& !target
->dap_configured
) {
2333 if (target
->tap_configured
) {
2335 Jim_SetResultString(goi
->interp
,
2336 "-chain-position and -dap configparams are mutually exclusive!", -1);
2339 target
->tap
= pc
->dap
->tap
;
2340 target
->dap_configured
= true;
2346 int adiv5_verify_config(struct adiv5_private_config
*pc
)
2357 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
2358 struct jim_getopt_info
*goi
)
2360 return adiv5_jim_spot_configure(goi
, &cfg
->dap
, &cfg
->ap_num
, &cfg
->base
);
2363 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
)
2366 p
->ap_num
= DP_APSEL_INVALID
;
2371 COMMAND_HANDLER(handle_dap_info_command
)
2373 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2381 if (!strcmp(CMD_ARGV
[0], "root")) {
2382 if (!is_adiv6(dap
)) {
2383 command_print(CMD
, "Option \"root\" not allowed with ADIv5 DAP");
2384 return ERROR_COMMAND_ARGUMENT_INVALID
;
2386 int retval
= adiv6_dap_read_baseptr(CMD
, dap
, &apsel
);
2387 if (retval
!= ERROR_OK
) {
2388 command_print(CMD
, "Failed reading DAP baseptr");
2393 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2394 if (!is_ap_num_valid(dap
, apsel
)) {
2395 command_print(CMD
, "Invalid AP number");
2396 return ERROR_COMMAND_ARGUMENT_INVALID
;
2400 return ERROR_COMMAND_SYNTAX_ERROR
;
2403 struct adiv5_ap
*ap
= dap_get_ap(dap
, apsel
);
2405 command_print(CMD
, "Cannot get AP");
2409 int retval
= dap_info_command(CMD
, ap
);
2414 COMMAND_HANDLER(dap_baseaddr_command
)
2416 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2418 uint32_t baseaddr_lower
, baseaddr_upper
;
2419 struct adiv5_ap
*ap
;
2420 target_addr_t baseaddr
;
2430 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2431 if (!is_ap_num_valid(dap
, apsel
)) {
2432 command_print(CMD
, "Invalid AP number");
2433 return ERROR_COMMAND_ARGUMENT_INVALID
;
2437 return ERROR_COMMAND_SYNTAX_ERROR
;
2440 /* NOTE: assumes we're talking to a MEM-AP, which
2441 * has a base address. There are other kinds of AP,
2442 * though they're not common for now. This should
2443 * use the ID register to verify it's a MEM-AP.
2446 ap
= dap_get_ap(dap
, apsel
);
2448 command_print(CMD
, "Cannot get AP");
2452 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE(dap
), &baseaddr_lower
);
2454 if (retval
== ERROR_OK
&& ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
)
2455 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG(dap
), &ap
->cfg_reg
);
2457 if (retval
== ERROR_OK
&& (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
|| is_64bit_ap(ap
))) {
2458 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
2459 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE64(dap
), &baseaddr_upper
);
2462 if (retval
== ERROR_OK
)
2463 retval
= dap_run(dap
);
2465 if (retval
!= ERROR_OK
)
2468 if (is_64bit_ap(ap
)) {
2469 baseaddr
= (((target_addr_t
)baseaddr_upper
) << 32) | baseaddr_lower
;
2470 command_print(CMD
, "0x%016" PRIx64
, baseaddr
);
2472 command_print(CMD
, "0x%08" PRIx32
, baseaddr_lower
);
2477 COMMAND_HANDLER(dap_memaccess_command
)
2479 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2480 struct adiv5_ap
*ap
;
2481 uint32_t memaccess_tck
;
2485 ap
= dap_get_ap(dap
, dap
->apsel
);
2487 command_print(CMD
, "Cannot get AP");
2490 memaccess_tck
= ap
->memaccess_tck
;
2493 ap
= dap_get_config_ap(dap
, dap
->apsel
);
2495 command_print(CMD
, "Cannot get AP");
2498 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
2499 ap
->memaccess_tck
= memaccess_tck
;
2502 return ERROR_COMMAND_SYNTAX_ERROR
;
2507 command_print(CMD
, "memory bus access delay set to %" PRIu32
" tck",
2513 COMMAND_HANDLER(dap_apsel_command
)
2515 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2520 command_print(CMD
, "0x%" PRIx64
, dap
->apsel
);
2523 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2524 if (!is_ap_num_valid(dap
, apsel
)) {
2525 command_print(CMD
, "Invalid AP number");
2526 return ERROR_COMMAND_ARGUMENT_INVALID
;
2530 return ERROR_COMMAND_SYNTAX_ERROR
;
2537 COMMAND_HANDLER(dap_apcsw_command
)
2539 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2540 struct adiv5_ap
*ap
;
2541 uint32_t csw_val
, csw_mask
;
2545 ap
= dap_get_ap(dap
, dap
->apsel
);
2547 command_print(CMD
, "Cannot get AP");
2550 command_print(CMD
, "AP#0x%" PRIx64
" selected, csw 0x%8.8" PRIx32
,
2551 dap
->apsel
, ap
->csw_default
);
2554 if (strcmp(CMD_ARGV
[0], "default") == 0)
2555 csw_val
= CSW_AHB_DEFAULT
;
2557 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
2559 if (csw_val
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
2560 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
2561 return ERROR_COMMAND_ARGUMENT_INVALID
;
2563 ap
= dap_get_config_ap(dap
, dap
->apsel
);
2565 command_print(CMD
, "Cannot get AP");
2568 ap
->csw_default
= csw_val
;
2571 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
2572 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], csw_mask
);
2573 if (csw_mask
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
2574 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
2575 return ERROR_COMMAND_ARGUMENT_INVALID
;
2577 ap
= dap_get_config_ap(dap
, dap
->apsel
);
2579 command_print(CMD
, "Cannot get AP");
2582 ap
->csw_default
= (ap
->csw_default
& ~csw_mask
) | (csw_val
& csw_mask
);
2585 return ERROR_COMMAND_SYNTAX_ERROR
;
2594 COMMAND_HANDLER(dap_apid_command
)
2596 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2606 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2607 if (!is_ap_num_valid(dap
, apsel
)) {
2608 command_print(CMD
, "Invalid AP number");
2609 return ERROR_COMMAND_ARGUMENT_INVALID
;
2613 return ERROR_COMMAND_SYNTAX_ERROR
;
2616 struct adiv5_ap
*ap
= dap_get_ap(dap
, apsel
);
2618 command_print(CMD
, "Cannot get AP");
2621 retval
= dap_queue_ap_read(ap
, AP_REG_IDR(dap
), &apid
);
2622 if (retval
!= ERROR_OK
) {
2626 retval
= dap_run(dap
);
2628 if (retval
!= ERROR_OK
)
2631 command_print(CMD
, "0x%8.8" PRIx32
, apid
);
2636 COMMAND_HANDLER(dap_apreg_command
)
2638 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2640 uint32_t reg
, value
;
2643 if (CMD_ARGC
< 2 || CMD_ARGC
> 3)
2644 return ERROR_COMMAND_SYNTAX_ERROR
;
2646 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2647 if (!is_ap_num_valid(dap
, apsel
)) {
2648 command_print(CMD
, "Invalid AP number");
2649 return ERROR_COMMAND_ARGUMENT_INVALID
;
2652 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg
);
2653 if (is_adiv6(dap
)) {
2654 if (reg
>= 4096 || (reg
& 3)) {
2655 command_print(CMD
, "Invalid reg value (should be less than 4096 and 4 bytes aligned)");
2656 return ERROR_COMMAND_ARGUMENT_INVALID
;
2658 } else { /* ADI version 5 */
2659 if (reg
>= 256 || (reg
& 3)) {
2660 command_print(CMD
, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2661 return ERROR_COMMAND_ARGUMENT_INVALID
;
2665 struct adiv5_ap
*ap
= dap_get_ap(dap
, apsel
);
2667 command_print(CMD
, "Cannot get AP");
2671 if (CMD_ARGC
== 3) {
2672 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
2673 /* see if user supplied register address is a match for the CSW or TAR register */
2674 if (reg
== MEM_AP_REG_CSW(dap
)) {
2675 ap
->csw_value
= 0; /* invalid, in case write fails */
2676 retval
= dap_queue_ap_write(ap
, reg
, value
);
2677 if (retval
== ERROR_OK
)
2678 ap
->csw_value
= value
;
2679 } else if (reg
== MEM_AP_REG_TAR(dap
)) {
2680 retval
= dap_queue_ap_write(ap
, reg
, value
);
2681 if (retval
== ERROR_OK
)
2682 ap
->tar_value
= (ap
->tar_value
& ~0xFFFFFFFFull
) | value
;
2684 /* To track independent writes to TAR and TAR64, two tar_valid flags */
2685 /* should be used. To keep it simple, tar_valid is only invalidated on a */
2686 /* write fail. This approach causes a later re-write of the TAR and TAR64 */
2687 /* if tar_valid is false. */
2688 ap
->tar_valid
= false;
2690 } else if (reg
== MEM_AP_REG_TAR64(dap
)) {
2691 retval
= dap_queue_ap_write(ap
, reg
, value
);
2692 if (retval
== ERROR_OK
)
2693 ap
->tar_value
= (ap
->tar_value
& 0xFFFFFFFFull
) | (((target_addr_t
)value
) << 32);
2695 /* See above comment for the MEM_AP_REG_TAR failed write case */
2696 ap
->tar_valid
= false;
2699 retval
= dap_queue_ap_write(ap
, reg
, value
);
2702 retval
= dap_queue_ap_read(ap
, reg
, &value
);
2704 if (retval
== ERROR_OK
)
2705 retval
= dap_run(dap
);
2709 if (retval
!= ERROR_OK
)
2713 command_print(CMD
, "0x%08" PRIx32
, value
);
2718 COMMAND_HANDLER(dap_dpreg_command
)
2720 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2721 uint32_t reg
, value
;
2724 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2725 return ERROR_COMMAND_SYNTAX_ERROR
;
2727 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg
);
2728 if (reg
>= 256 || (reg
& 3)) {
2729 command_print(CMD
, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2730 return ERROR_COMMAND_ARGUMENT_INVALID
;
2733 if (CMD_ARGC
== 2) {
2734 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2735 retval
= dap_queue_dp_write(dap
, reg
, value
);
2737 retval
= dap_queue_dp_read(dap
, reg
, &value
);
2739 if (retval
== ERROR_OK
)
2740 retval
= dap_run(dap
);
2742 if (retval
!= ERROR_OK
)
2746 command_print(CMD
, "0x%08" PRIx32
, value
);
2751 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
2753 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2754 return CALL_COMMAND_HANDLER(handle_command_parse_bool
, &dap
->ti_be_32_quirks
,
2755 "TI BE-32 quirks mode");
2758 const struct command_registration dap_instance_commands
[] = {
2761 .handler
= handle_dap_info_command
,
2762 .mode
= COMMAND_EXEC
,
2763 .help
= "display ROM table for specified MEM-AP (default currently selected AP) "
2764 "or the ADIv6 root ROM table",
2765 .usage
= "[ap_num | 'root']",
2769 .handler
= dap_apsel_command
,
2770 .mode
= COMMAND_ANY
,
2771 .help
= "Set the currently selected AP (default 0) "
2772 "and display the result",
2773 .usage
= "[ap_num]",
2777 .handler
= dap_apcsw_command
,
2778 .mode
= COMMAND_ANY
,
2779 .help
= "Set CSW default bits",
2780 .usage
= "[value [mask]]",
2785 .handler
= dap_apid_command
,
2786 .mode
= COMMAND_EXEC
,
2787 .help
= "return ID register from AP "
2788 "(default currently selected AP)",
2789 .usage
= "[ap_num]",
2793 .handler
= dap_apreg_command
,
2794 .mode
= COMMAND_EXEC
,
2795 .help
= "read/write a register from AP "
2796 "(reg is byte address of a word register, like 0 4 8...)",
2797 .usage
= "ap_num reg [value]",
2801 .handler
= dap_dpreg_command
,
2802 .mode
= COMMAND_EXEC
,
2803 .help
= "read/write a register from DP "
2804 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
2805 .usage
= "reg [value]",
2809 .handler
= dap_baseaddr_command
,
2810 .mode
= COMMAND_EXEC
,
2811 .help
= "return debug base address from MEM-AP "
2812 "(default currently selected AP)",
2813 .usage
= "[ap_num]",
2816 .name
= "memaccess",
2817 .handler
= dap_memaccess_command
,
2818 .mode
= COMMAND_EXEC
,
2819 .help
= "set/get number of extra tck for MEM-AP memory "
2820 "bus access [0-255]",
2821 .usage
= "[cycles]",
2824 .name
= "ti_be_32_quirks",
2825 .handler
= dap_ti_be_32_quirks_command
,
2826 .mode
= COMMAND_CONFIG
,
2827 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
2828 .usage
= "[enable]",
2830 COMMAND_REGISTRATION_DONE