1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
29 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
30 * debugging architecture. Compared with previous versions, this includes
31 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
32 * transport, and focusses on memory mapped resources as defined by the
33 * CoreSight architecture.
35 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
36 * basic components: a Debug Port (DP) transporting messages to and from a
37 * debugger, and an Access Port (AP) accessing resources. Three types of DP
38 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
39 * One uses only SWD for communication, and is called SW-DP. The third can
40 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
41 * is used to access memory mapped resources and is called a MEM-AP. Also a
42 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * Relevant specifications from ARM include:
48 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
49 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
51 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
52 * Cortex-M3(tm) TRM, ARM DDI 0337G
59 #include "arm_adi_v5.h"
60 #include <helper/time_support.h>
64 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
65 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
66 * result checking until swjdp_end_transaction()
67 * This must be done before using or deallocating any return variables.
68 * swjdp->trans_mode == TRANS_MODE_ATOMIC
69 * All reads and writes to the AHB bus are checked for valid completion, and return values
70 * are immediatley available.
74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
77 uint32_t tar_block_size(uint32_t address)
78 Return the largest block starting at address that does not cross a tar block size alignment boundary
80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
82 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
85 /***************************************************************************
87 * DPACC and APACC scanchain access through JTAG-DP *
89 ***************************************************************************/
91 /* Scan out and in from target ordered uint8_t buffers */
92 static int adi_jtag_dp_scan(struct swjdp_common
*swjdp
,
93 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
94 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
96 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
97 struct scan_field fields
[2];
100 jtag_set_end_state(TAP_IDLE
);
101 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
103 /* Add specified number of tck clocks before accessing memory bus */
104 if ((instr
== JTAG_DP_APACC
)
105 && ((reg_addr
== AP_REG_DRW
)
106 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
107 && (swjdp
->memaccess_tck
!= 0))
108 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
110 fields
[0].tap
= jtag_info
->tap
;
111 fields
[0].num_bits
= 3;
112 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
113 fields
[0].out_value
= &out_addr_buf
;
114 fields
[0].in_value
= ack
;
116 fields
[1].tap
= jtag_info
->tap
;
117 fields
[1].num_bits
= 32;
118 fields
[1].out_value
= outvalue
;
119 fields
[1].in_value
= invalue
;
121 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
126 /* Scan out and in from host ordered uint32_t variables */
127 static int adi_jtag_dp_scan_u32(struct swjdp_common
*swjdp
,
128 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
129 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
131 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
132 struct scan_field fields
[2];
133 uint8_t out_value_buf
[4];
134 uint8_t out_addr_buf
;
136 jtag_set_end_state(TAP_IDLE
);
137 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
139 /* Add specified number of tck clocks before accessing memory bus */
140 if ((instr
== JTAG_DP_APACC
)
141 && ((reg_addr
== AP_REG_DRW
)
142 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
143 && (swjdp
->memaccess_tck
!= 0))
144 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
146 fields
[0].tap
= jtag_info
->tap
;
147 fields
[0].num_bits
= 3;
148 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
149 fields
[0].out_value
= &out_addr_buf
;
150 fields
[0].in_value
= ack
;
152 fields
[1].tap
= jtag_info
->tap
;
153 fields
[1].num_bits
= 32;
154 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
155 fields
[1].out_value
= out_value_buf
;
156 fields
[1].in_value
= NULL
;
160 fields
[1].in_value
= (uint8_t *)invalue
;
161 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
163 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
) invalue
);
167 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
173 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
174 static int scan_inout_check(struct swjdp_common
*swjdp
,
175 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
176 uint8_t *outvalue
, uint8_t *invalue
)
178 adi_jtag_dp_scan(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
180 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
181 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
,
182 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
184 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
185 * ack = OK/FAULT and the check CTRL_STAT
187 if ((instr
== JTAG_DP_APACC
)
188 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
189 return swjdp_transaction_endcheck(swjdp
);
194 static int scan_inout_check_u32(struct swjdp_common
*swjdp
,
195 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
196 uint32_t outvalue
, uint32_t *invalue
)
198 /* Issue the read or write */
199 adi_jtag_dp_scan_u32(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
201 /* For reads, collect posted value; RDBUFF has no other effect.
202 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
204 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
205 adi_jtag_dp_scan_u32(swjdp
, JTAG_DP_DPACC
,
206 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
208 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
209 * ack = OK/FAULT and then check CTRL_STAT
211 if ((instr
== JTAG_DP_APACC
)
212 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
213 return swjdp_transaction_endcheck(swjdp
);
218 int swjdp_transaction_endcheck(struct swjdp_common
*swjdp
)
223 /* too expensive to call keep_alive() here */
226 /* Danger!!!! BROKEN!!!! */
227 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
228 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
229 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
230 R956 introduced the check on return value here and now Michael Schwingen reports
231 that this code no longer works....
233 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
235 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
237 LOG_ERROR("BUG: Why does this fail the first time????");
239 /* Why??? second time it works??? */
242 /* Post CTRL/STAT read; discard any previous posted read value
243 * but collect its ACK status.
245 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
246 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
247 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
250 swjdp
->ack
= swjdp
->ack
& 0x7;
252 /* common code path avoids calling timeval_ms() */
253 if (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
255 long long then
= timeval_ms();
257 while (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
259 if (swjdp
->ack
== JTAG_ACK_WAIT
)
261 if ((timeval_ms()-then
) > 1000)
263 /* NOTE: this would be a good spot
264 * to use JTAG_DP_ABORT.
266 LOG_WARNING("Timeout (1000ms) waiting "
268 "in JTAG-DP transaction");
269 return ERROR_JTAG_DEVICE_ERROR
;
274 LOG_WARNING("Invalid ACK "
275 "in JTAG-DP transaction");
276 return ERROR_JTAG_DEVICE_ERROR
;
279 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
280 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
281 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
283 swjdp
->ack
= swjdp
->ack
& 0x7;
287 /* Check for STICKYERR and STICKYORUN */
288 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
290 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32
"", ctrlstat
);
291 /* Check power to debug regions */
292 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
294 ahbap_debugport_init(swjdp
);
298 uint32_t mem_ap_csw
, mem_ap_tar
;
300 /* Print information about last AHBAP access */
301 LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
", ap_csw 0x%" PRIx32
", ap_tar 0x%" PRIx32
"", swjdp
->dp_select_value
, swjdp
->ap_csw_value
, swjdp
->ap_tar_value
);
302 if (ctrlstat
& SSTICKYORUN
)
303 LOG_ERROR("JTAG-DP OVERRUN - "
304 "check clock or reduce jtag speed");
306 if (ctrlstat
& SSTICKYERR
)
307 LOG_ERROR("JTAG-DP STICKY ERROR");
309 /* Clear Sticky Error Bits */
310 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
311 DP_CTRL_STAT
, DPAP_WRITE
,
312 swjdp
->dp_ctrl_stat
| SSTICKYORUN
314 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
315 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
316 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
319 LOG_DEBUG("swjdp: status 0x%" PRIx32
"", ctrlstat
);
321 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
322 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
323 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
325 LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%" PRIx32
"", mem_ap_csw
, mem_ap_tar
);
328 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
330 return ERROR_JTAG_DEVICE_ERROR
;
336 /***************************************************************************
338 * DP and MEM-AP register access through APACC and DPACC *
340 ***************************************************************************/
342 static int dap_dp_write_reg(struct swjdp_common
*swjdp
,
343 uint32_t value
, uint8_t reg_addr
)
345 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
346 reg_addr
, DPAP_WRITE
, value
, NULL
);
349 static int dap_dp_read_reg(struct swjdp_common
*swjdp
,
350 uint32_t *value
, uint8_t reg_addr
)
352 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
353 reg_addr
, DPAP_READ
, 0, value
);
356 int dap_ap_select(struct swjdp_common
*swjdp
,uint8_t apsel
)
359 select
= (apsel
<< 24) & 0xFF000000;
361 if (select
!= swjdp
->apsel
)
363 swjdp
->apsel
= select
;
364 /* Switching AP invalidates cached values */
365 swjdp
->dp_select_value
= -1;
366 swjdp
->ap_csw_value
= -1;
367 swjdp
->ap_tar_value
= -1;
373 static int dap_dp_bankselect(struct swjdp_common
*swjdp
, uint32_t ap_reg
)
376 select
= (ap_reg
& 0x000000F0);
378 if (select
!= swjdp
->dp_select_value
)
380 dap_dp_write_reg(swjdp
, select
| swjdp
->apsel
, DP_SELECT
);
381 swjdp
->dp_select_value
= select
;
387 static int dap_ap_write_reg(struct swjdp_common
*swjdp
,
388 uint32_t reg_addr
, uint8_t *out_value_buf
)
390 dap_dp_bankselect(swjdp
, reg_addr
);
391 scan_inout_check(swjdp
, JTAG_DP_APACC
, reg_addr
,
392 DPAP_WRITE
, out_value_buf
, NULL
);
397 int dap_ap_write_reg_u32(struct swjdp_common
*swjdp
, uint32_t reg_addr
, uint32_t value
)
399 uint8_t out_value_buf
[4];
401 buf_set_u32(out_value_buf
, 0, 32, value
);
402 dap_dp_bankselect(swjdp
, reg_addr
);
403 scan_inout_check(swjdp
, JTAG_DP_APACC
, reg_addr
,
404 DPAP_WRITE
, out_value_buf
, NULL
);
409 int dap_ap_read_reg_u32(struct swjdp_common
*swjdp
, uint32_t reg_addr
, uint32_t *value
)
411 dap_dp_bankselect(swjdp
, reg_addr
);
412 scan_inout_check_u32(swjdp
, JTAG_DP_APACC
, reg_addr
,
413 DPAP_READ
, 0, value
);
418 /***************************************************************************
420 * AHB-AP access to memory and system registers on AHB bus *
422 ***************************************************************************/
424 int dap_setup_accessport(struct swjdp_common
*swjdp
, uint32_t csw
, uint32_t tar
)
426 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
427 if (csw
!= swjdp
->ap_csw_value
)
429 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
430 dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
431 swjdp
->ap_csw_value
= csw
;
433 if (tar
!= swjdp
->ap_tar_value
)
435 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
436 dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
437 swjdp
->ap_tar_value
= tar
;
439 if (csw
& CSW_ADDRINC_MASK
)
441 /* Do not cache TAR value when autoincrementing */
442 swjdp
->ap_tar_value
= -1;
447 /*****************************************************************************
449 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
451 * Read a uint32_t value from memory or system register *
452 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
453 * but with less overhead *
454 *****************************************************************************/
455 int mem_ap_read_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t *value
)
457 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
459 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
460 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
465 int mem_ap_read_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t *value
)
467 mem_ap_read_u32(swjdp
, address
, value
);
469 return swjdp_transaction_endcheck(swjdp
);
472 /*****************************************************************************
474 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
476 * Write a uint32_t value to memory or memory mapped register *
478 *****************************************************************************/
479 int mem_ap_write_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t value
)
481 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
483 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
484 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
489 int mem_ap_write_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t value
)
491 mem_ap_write_u32(swjdp
, address
, value
);
493 return swjdp_transaction_endcheck(swjdp
);
496 /*****************************************************************************
498 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
500 * Write a buffer in target order (little endian) *
502 *****************************************************************************/
503 int mem_ap_write_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
505 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
506 uint32_t adr
= address
;
507 uint8_t* pBuffer
= buffer
;
509 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
514 /* if we have an unaligned access - reorder data */
517 for (writecount
= 0; writecount
< count
; writecount
++)
521 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
523 for (i
= 0; i
< 4; i
++)
525 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
529 pBuffer
+= sizeof(uint32_t);
535 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
536 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
537 if (wcount
< blocksize
)
540 /* handle unaligned data at 4k boundary */
544 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
546 for (writecount
= 0; writecount
< blocksize
; writecount
++)
548 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
551 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
553 wcount
= wcount
- blocksize
;
554 address
= address
+ 4 * blocksize
;
555 buffer
= buffer
+ 4 * blocksize
;
564 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
565 return ERROR_JTAG_DEVICE_ERROR
;
572 static int mem_ap_write_buf_packed_u16(struct swjdp_common
*swjdp
,
573 uint8_t *buffer
, int count
, uint32_t address
)
575 int retval
= ERROR_OK
;
576 int wcount
, blocksize
, writecount
, i
;
578 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
586 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
587 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
589 if (wcount
< blocksize
)
592 /* handle unaligned data at 4k boundary */
596 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
597 writecount
= blocksize
;
601 nbytes
= MIN((writecount
<< 1), 4);
605 if (mem_ap_write_buf_u16(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
607 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
608 return ERROR_JTAG_DEVICE_ERROR
;
611 address
+= nbytes
>> 1;
616 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
618 for (i
= 0; i
< nbytes
; i
++)
620 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
625 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
626 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
627 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
629 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
630 return ERROR_JTAG_DEVICE_ERROR
;
634 buffer
+= nbytes
>> 1;
635 writecount
-= nbytes
>> 1;
637 } while (writecount
);
644 int mem_ap_write_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
646 int retval
= ERROR_OK
;
649 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
651 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
655 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
657 memcpy(&svalue
, buffer
, sizeof(uint16_t));
658 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
659 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
660 retval
= swjdp_transaction_endcheck(swjdp
);
669 static int mem_ap_write_buf_packed_u8(struct swjdp_common
*swjdp
,
670 uint8_t *buffer
, int count
, uint32_t address
)
672 int retval
= ERROR_OK
;
673 int wcount
, blocksize
, writecount
, i
;
675 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
683 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
684 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
686 if (wcount
< blocksize
)
689 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
690 writecount
= blocksize
;
694 nbytes
= MIN(writecount
, 4);
698 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
700 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
701 return ERROR_JTAG_DEVICE_ERROR
;
709 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
711 for (i
= 0; i
< nbytes
; i
++)
713 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
718 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
719 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
720 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
722 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
723 return ERROR_JTAG_DEVICE_ERROR
;
728 writecount
-= nbytes
;
730 } while (writecount
);
737 int mem_ap_write_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
739 int retval
= ERROR_OK
;
742 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
744 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
748 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
749 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
750 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
751 retval
= swjdp_transaction_endcheck(swjdp
);
760 /*********************************************************************************
762 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
764 * Read block fast in target order (little endian) into a buffer *
766 **********************************************************************************/
767 int mem_ap_read_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
769 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
770 uint32_t adr
= address
;
771 uint8_t* pBuffer
= buffer
;
773 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
780 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
781 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
782 if (wcount
< blocksize
)
785 /* handle unaligned data at 4k boundary */
789 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
791 /* Scan out first read */
792 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
793 DPAP_READ
, 0, NULL
, NULL
);
794 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
796 /* Scan out next read; scan in posted value for the
797 * previous one. Assumes read is acked "OK/FAULT",
798 * and CTRL_STAT says that meant "OK".
800 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
801 DPAP_READ
, 0, buffer
+ 4 * readcount
,
805 /* Scan in last posted value; RDBUFF has no other effect,
806 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
808 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
, DP_RDBUFF
,
809 DPAP_READ
, 0, buffer
+ 4 * readcount
,
811 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
813 wcount
= wcount
- blocksize
;
814 address
+= 4 * blocksize
;
815 buffer
+= 4 * blocksize
;
824 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
825 return ERROR_JTAG_DEVICE_ERROR
;
829 /* if we have an unaligned access - reorder data */
832 for (readcount
= 0; readcount
< count
; readcount
++)
836 memcpy(&data
, pBuffer
, sizeof(uint32_t));
838 for (i
= 0; i
< 4; i
++)
840 *((uint8_t*)pBuffer
) = (data
>> 8 * (adr
& 0x3));
850 static int mem_ap_read_buf_packed_u16(struct swjdp_common
*swjdp
,
851 uint8_t *buffer
, int count
, uint32_t address
)
854 int retval
= ERROR_OK
;
855 int wcount
, blocksize
, readcount
, i
;
857 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
865 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
866 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
867 if (wcount
< blocksize
)
870 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
872 /* handle unaligned data at 4k boundary */
875 readcount
= blocksize
;
879 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
880 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
882 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
883 return ERROR_JTAG_DEVICE_ERROR
;
886 nbytes
= MIN((readcount
<< 1), 4);
888 for (i
= 0; i
< nbytes
; i
++)
890 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
895 readcount
-= (nbytes
>> 1);
903 int mem_ap_read_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
906 int retval
= ERROR_OK
;
909 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
911 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
915 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
916 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
917 retval
= swjdp_transaction_endcheck(swjdp
);
920 for (i
= 0; i
< 2; i
++)
922 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
929 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
930 memcpy(buffer
, &svalue
, sizeof(uint16_t));
940 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
941 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
943 * The solution is to arrange for a large out/in scan in this loop and
944 * and convert data afterwards.
946 static int mem_ap_read_buf_packed_u8(struct swjdp_common
*swjdp
,
947 uint8_t *buffer
, int count
, uint32_t address
)
950 int retval
= ERROR_OK
;
951 int wcount
, blocksize
, readcount
, i
;
953 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
961 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
962 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
964 if (wcount
< blocksize
)
967 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
968 readcount
= blocksize
;
972 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
973 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
975 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
976 return ERROR_JTAG_DEVICE_ERROR
;
979 nbytes
= MIN(readcount
, 4);
981 for (i
= 0; i
< nbytes
; i
++)
983 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
996 int mem_ap_read_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
999 int retval
= ERROR_OK
;
1002 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
1004 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1008 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
1009 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1010 retval
= swjdp_transaction_endcheck(swjdp
);
1011 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1023 * @todo Rename this. We also need an initialization scheme which account
1024 * for SWD transports not just JTAG; that will need to address differences
1025 * in layering. (JTAG is useful without any debug target; but not SWD.)
1027 int ahbap_debugport_init(struct swjdp_common
*swjdp
)
1029 uint32_t idreg
, romaddr
, dummy
;
1036 /* Default MEM-AP setup.
1038 * REVISIT AP #0 may be an inappropriate default for this.
1039 * Should we probe, or receve a hint from the caller?
1040 * Presumably we can ignore the possibility of multiple APs.
1043 swjdp
->ap_csw_value
= -1;
1044 swjdp
->ap_tar_value
= -1;
1046 /* DP initialization */
1047 swjdp
->trans_mode
= TRANS_MODE_ATOMIC
;
1048 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1049 dap_dp_write_reg(swjdp
, SSTICKYERR
, DP_CTRL_STAT
);
1050 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1052 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1054 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1055 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1056 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1059 /* Check that we have debug power domains activated */
1060 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
1062 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1063 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1064 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1069 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
1071 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1072 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1073 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1078 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1079 /* With debug power on we can activate OVERRUN checking */
1080 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1081 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1082 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1085 * REVISIT this isn't actually *initializing* anything in an AP,
1086 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1087 * Should it? If the ROM address is valid, is this the right
1088 * place to scan the table and do any topology detection?
1090 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &idreg
);
1091 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &romaddr
);
1093 LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32
", Debug ROM Address 0x%" PRIx32
"", idreg
, romaddr
);
1098 /* CID interpretation -- see ARM IHI 0029B section 3
1099 * and ARM IHI 0031A table 13-3.
1101 static const char *class_description
[16] ={
1102 "Reserved", "ROM table", "Reserved", "Reserved",
1103 "Reserved", "Reserved", "Reserved", "Reserved",
1104 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1105 "Reserved", "OptimoDE DESS",
1106 "Generic IP component", "PrimeCell or System component"
1110 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1112 return cid3
== 0xb1 && cid2
== 0x05
1113 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1116 int dap_info_command(struct command_context
*cmd_ctx
, struct swjdp_common
*swjdp
, int apsel
)
1119 uint32_t dbgbase
, apid
;
1120 int romtable_present
= 0;
1124 apselold
= swjdp
->apsel
;
1125 dap_ap_select(swjdp
, apsel
);
1126 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &dbgbase
);
1127 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1128 swjdp_transaction_endcheck(swjdp
);
1129 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1130 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1131 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1137 command_print(cmd_ctx
, "\tType is JTAG-AP");
1140 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1143 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1146 command_print(cmd_ctx
, "\tUnknown AP type");
1150 /* NOTE: a MEM-AP may have a single CoreSight component that's
1151 * not a ROM table ... or have no such components at all.
1154 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1159 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1162 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1163 if (romtable_present
)
1165 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1166 uint16_t entry_offset
;
1168 /* bit 16 of apid indicates a memory access port */
1170 command_print(cmd_ctx
, "\tValid ROM table present");
1172 command_print(cmd_ctx
, "\tROM table in legacy format");
1174 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1175 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1176 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1177 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1178 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1179 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1180 swjdp_transaction_endcheck(swjdp
);
1181 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1182 command_print(cmd_ctx
, "\tCID3 0x%2.2" PRIx32
1183 ", CID2 0x%2.2" PRIx32
1184 ", CID1 0x%2.2" PRIx32
1185 ", CID0 0x%2.2" PRIx32
,
1186 cid3
, cid2
, cid1
, cid0
);
1188 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1190 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1191 "Dedicated debug bus.");
1193 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1197 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1198 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1201 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1202 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1203 uint32_t component_start
, component_base
;
1207 component_base
= (uint32_t)((dbgbase
& 0xFFFFF000)
1208 + (int)(romentry
& 0xFFFFF000));
1209 mem_ap_read_atomic_u32(swjdp
,
1210 (component_base
& 0xFFFFF000) | 0xFE0, &c_pid0
);
1211 mem_ap_read_atomic_u32(swjdp
,
1212 (component_base
& 0xFFFFF000) | 0xFE4, &c_pid1
);
1213 mem_ap_read_atomic_u32(swjdp
,
1214 (component_base
& 0xFFFFF000) | 0xFE8, &c_pid2
);
1215 mem_ap_read_atomic_u32(swjdp
,
1216 (component_base
& 0xFFFFF000) | 0xFEC, &c_pid3
);
1217 mem_ap_read_atomic_u32(swjdp
,
1218 (component_base
& 0xFFFFF000) | 0xFD0, &c_pid4
);
1219 mem_ap_read_atomic_u32(swjdp
,
1220 (component_base
& 0xFFFFF000) | 0xFF0, &c_cid0
);
1221 mem_ap_read_atomic_u32(swjdp
,
1222 (component_base
& 0xFFFFF000) | 0xFF4, &c_cid1
);
1223 mem_ap_read_atomic_u32(swjdp
,
1224 (component_base
& 0xFFFFF000) | 0xFF8, &c_cid2
);
1225 mem_ap_read_atomic_u32(swjdp
,
1226 (component_base
& 0xFFFFF000) | 0xFFC, &c_cid3
);
1227 component_start
= component_base
- 0x1000*(c_pid4
>> 4);
1229 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
1230 ", start address 0x%" PRIx32
,
1231 component_base
, component_start
);
1232 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1233 (int) (c_cid1
>> 4) & 0xf,
1234 /* See ARM IHI 0029B Table 3-3 */
1235 class_description
[(c_cid1
>> 4) & 0xf]);
1237 /* CoreSight component? */
1238 if (((c_cid1
>> 4) & 0x0f) == 9) {
1241 char *major
= "Reserved", *subtype
= "Reserved";
1243 mem_ap_read_atomic_u32(swjdp
,
1244 (component_base
& 0xfffff000) | 0xfcc,
1246 minor
= (devtype
>> 4) & 0x0f;
1247 switch (devtype
& 0x0f) {
1249 major
= "Miscellaneous";
1255 subtype
= "Validation component";
1260 major
= "Trace Sink";
1274 major
= "Trace Link";
1280 subtype
= "Funnel, router";
1286 subtype
= "FIFO, buffer";
1291 major
= "Trace Source";
1297 subtype
= "Processor";
1303 subtype
= "Engine/Coprocessor";
1311 major
= "Debug Control";
1317 subtype
= "Trigger Matrix";
1320 subtype
= "Debug Auth";
1325 major
= "Debug Logic";
1331 subtype
= "Processor";
1337 subtype
= "Engine/Coprocessor";
1342 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1343 (unsigned) (devtype
& 0xff),
1345 /* REVISIT also show 0xfc8 DevId */
1348 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1349 command_print(cmd_ctx
, "\t\tCID3 0x%2.2" PRIx32
1350 ", CID2 0x%2.2" PRIx32
1351 ", CID1 0x%2.2" PRIx32
1352 ", CID0 0x%2.2" PRIx32
,
1353 c_cid3
, c_cid2
, c_cid1
, c_cid0
);
1354 command_print(cmd_ctx
, "\t\tPeripheral ID[4..0] = hex "
1355 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1357 (int) c_pid3
, (int) c_pid2
,
1358 (int) c_pid1
, (int) c_pid0
);
1360 /* Part number interpretations are from Cortex
1361 * core specs, the CoreSight components TRM
1362 * (ARM DDI 0314H), and ETM specs; also from
1363 * chip observation (e.g. TI SDTI).
1365 part_num
= c_pid0
& 0xff;
1366 part_num
|= (c_pid1
& 0x0f) << 8;
1369 type
= "Cortex-M3 NVIC";
1370 full
= "(Interrupt Controller)";
1373 type
= "Cortex-M3 ITM";
1374 full
= "(Instrumentation Trace Module)";
1377 type
= "Cortex-M3 DWT";
1378 full
= "(Data Watchpoint and Trace)";
1381 type
= "Cortex-M3 FBP";
1382 full
= "(Flash Patch and Breakpoint)";
1385 type
= "CoreSight ETM11";
1386 full
= "(Embedded Trace)";
1388 // case 0x113: what?
1389 case 0x120: /* from OMAP3 memmap */
1391 full
= "(System Debug Trace Interface)";
1393 case 0x343: /* from OMAP3 memmap */
1398 type
= "Cortex-M3 ETM";
1399 full
= "(Embedded Trace)";
1402 type
= "Coresight CTI";
1403 full
= "(Cross Trigger)";
1406 type
= "Coresight ETB";
1407 full
= "(Trace Buffer)";
1410 type
= "Coresight CSTF";
1411 full
= "(Trace Funnel)";
1414 type
= "CoreSight ETM9";
1415 full
= "(Embedded Trace)";
1418 type
= "Coresight TPIU";
1419 full
= "(Trace Port Interface Unit)";
1422 type
= "Cortex-A8 ETM";
1423 full
= "(Embedded Trace)";
1426 type
= "Cortex-A8 CTI";
1427 full
= "(Cross Trigger)";
1430 type
= "Cortex-M3 TPIU";
1431 full
= "(Trace Port Interface Unit)";
1434 type
= "Cortex-A8 Debug";
1435 full
= "(Debug Unit)";
1438 type
= "-*- unrecognized -*-";
1442 command_print(cmd_ctx
, "\t\tPart is %s %s",
1448 command_print(cmd_ctx
, "\t\tComponent not present");
1450 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1453 } while (romentry
> 0);
1457 command_print(cmd_ctx
, "\tNo ROM table present");
1459 dap_ap_select(swjdp
, apselold
);
1464 DAP_COMMAND_HANDLER(dap_baseaddr_command
)
1466 uint32_t apsel
, apselsave
, baseaddr
;
1469 apselsave
= swjdp
->apsel
;
1472 apsel
= swjdp
->apsel
;
1475 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1478 return ERROR_COMMAND_SYNTAX_ERROR
;
1481 if (apselsave
!= apsel
)
1482 dap_ap_select(swjdp
, apsel
);
1484 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &baseaddr
);
1485 retval
= swjdp_transaction_endcheck(swjdp
);
1486 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1488 if (apselsave
!= apsel
)
1489 dap_ap_select(swjdp
, apselsave
);
1494 DAP_COMMAND_HANDLER(dap_memaccess_command
)
1496 uint32_t memaccess_tck
;
1500 memaccess_tck
= swjdp
->memaccess_tck
;
1503 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1506 return ERROR_COMMAND_SYNTAX_ERROR
;
1508 swjdp
->memaccess_tck
= memaccess_tck
;
1510 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1511 swjdp
->memaccess_tck
);
1516 DAP_COMMAND_HANDLER(dap_apsel_command
)
1518 uint32_t apsel
, apid
;
1526 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1529 return ERROR_COMMAND_SYNTAX_ERROR
;
1532 dap_ap_select(swjdp
, apsel
);
1533 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1534 retval
= swjdp_transaction_endcheck(swjdp
);
1535 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1541 DAP_COMMAND_HANDLER(dap_apid_command
)
1543 uint32_t apsel
, apselsave
, apid
;
1546 apselsave
= swjdp
->apsel
;
1549 apsel
= swjdp
->apsel
;
1552 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1555 return ERROR_COMMAND_SYNTAX_ERROR
;
1558 if (apselsave
!= apsel
)
1559 dap_ap_select(swjdp
, apsel
);
1561 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1562 retval
= swjdp_transaction_endcheck(swjdp
);
1563 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1564 if (apselsave
!= apsel
)
1565 dap_ap_select(swjdp
, apselsave
);
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