1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
32 #include <helper/list.h>
34 #include "helper/bits.h"
36 /* JEP106 ID for ARM */
39 /* three-bit ACK values for SWD access (sent LSB first) */
40 #define SWD_ACK_OK 0x1
41 #define SWD_ACK_WAIT 0x2
42 #define SWD_ACK_FAULT 0x4
47 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
49 /* A[3:0] for DP registers; A[1:0] are always zero.
50 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
51 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
52 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
54 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
55 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
56 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
57 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
58 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
59 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
60 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
61 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
62 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
63 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
64 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
66 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
68 /* Fields of the DP's AP ABORT register */
69 #define DAPABORT (1UL << 0)
70 #define STKCMPCLR (1UL << 1) /* SWD-only */
71 #define STKERRCLR (1UL << 2) /* SWD-only */
72 #define WDERRCLR (1UL << 3) /* SWD-only */
73 #define ORUNERRCLR (1UL << 4) /* SWD-only */
75 /* Fields of the DP's CTRL/STAT register */
76 #define CORUNDETECT (1UL << 0)
77 #define SSTICKYORUN (1UL << 1)
78 /* 3:2 - transaction mode (e.g. pushed compare) */
79 #define SSTICKYCMP (1UL << 4)
80 #define SSTICKYERR (1UL << 5)
81 #define READOK (1UL << 6) /* SWD-only */
82 #define WDATAERR (1UL << 7) /* SWD-only */
83 /* 11:8 - mask lanes for pushed compare or verify ops */
84 /* 21:12 - transaction counter */
85 #define CDBGRSTREQ (1UL << 26)
86 #define CDBGRSTACK (1UL << 27)
87 #define CDBGPWRUPREQ (1UL << 28)
88 #define CDBGPWRUPACK (1UL << 29)
89 #define CSYSPWRUPREQ (1UL << 30)
90 #define CSYSPWRUPACK (1UL << 31)
92 #define DP_SELECT_APSEL 0xFF000000
93 #define DP_SELECT_APBANK 0x000000F0
94 #define DP_SELECT_DPBANK 0x0000000F
95 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
97 #define DP_APSEL_MAX (255)
98 #define DP_APSEL_INVALID (-1)
101 /* MEM-AP register addresses */
102 #define MEM_AP_REG_CSW 0x00
103 #define MEM_AP_REG_TAR 0x04
104 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
105 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
106 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
107 #define MEM_AP_REG_BD1 0x14
108 #define MEM_AP_REG_BD2 0x18
109 #define MEM_AP_REG_BD3 0x1C
110 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
111 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
112 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
113 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
114 /* Generic AP register address */
115 #define AP_REG_IDR 0xFC /* RO: Identification Register */
117 /* Fields of the MEM-AP's CSW register */
118 #define CSW_SIZE_MASK 7
122 #define CSW_ADDRINC_MASK (3UL << 4)
123 #define CSW_ADDRINC_OFF 0UL
124 #define CSW_ADDRINC_SINGLE (1UL << 4)
125 #define CSW_ADDRINC_PACKED (2UL << 4)
126 #define CSW_DEVICE_EN (1UL << 6)
127 #define CSW_TRIN_PROG (1UL << 7)
129 /* All fields in bits 12 and above are implementation-defined
130 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
131 * Some bits are shared between buses
133 #define CSW_SPIDEN (1UL << 23)
134 #define CSW_DBGSWENABLE (1UL << 31)
136 /* AHB: Privileged */
137 #define CSW_AHB_HPROT1 (1UL << 25)
138 /* AHB: set HMASTER signals to AHB-AP ID */
139 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
140 /* AHB5: non-secure access via HNONSEC
141 * AHB3: SBO, UNPREDICTABLE if zero */
142 #define CSW_AHB_SPROT (1UL << 30)
143 /* AHB: initial value of csw_default */
144 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
146 /* AXI: Privileged */
147 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
148 /* AXI: Non-secure */
149 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
150 /* AXI: initial value of csw_default */
151 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
153 /* APB: initial value of csw_default */
154 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
156 /* Fields of the MEM-AP's CFG register */
157 #define MEM_AP_REG_CFG_BE BIT(0)
158 #define MEM_AP_REG_CFG_LA BIT(1)
159 #define MEM_AP_REG_CFG_LD BIT(2)
160 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
162 /* Fields of the MEM-AP's IDR register */
163 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
164 #define AP_REG_IDR_REVISION_SHIFT (28)
165 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
166 #define AP_REG_IDR_DESIGNER_SHIFT (17)
167 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
168 #define AP_REG_IDR_CLASS_SHIFT (13)
169 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
170 #define AP_REG_IDR_VARIANT_SHIFT (4)
171 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
172 #define AP_REG_IDR_TYPE_SHIFT (0)
174 #define AP_REG_IDR_CLASS_NONE (0x0)
175 #define AP_REG_IDR_CLASS_COM (0x1)
176 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
178 #define AP_REG_IDR_VALUE(d, c, t) (\
179 (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
180 (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
181 (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
184 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
186 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
187 enum swd_special_seq
{
197 * This represents an ARM Debug Interface (v5) Access Port (AP).
198 * Most common is a MEM-AP, for memory access.
202 * DAP this AP belongs to.
204 struct adiv5_dap
*dap
;
212 * Default value for (MEM-AP) AP_REG_CSW register.
214 uint32_t csw_default
;
217 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
218 * configure an access mode, such as autoincrementing AP_REG_TAR during
219 * word access. "-1" indicates no cached value.
224 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
225 * configure the address being read or written
226 * "-1" indicates no cached value.
228 target_addr_t tar_value
;
231 * Configures how many extra tck clocks are added after starting a
232 * MEM-AP access before we try to read its status (and/or result).
234 uint32_t memaccess_tck
;
236 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
237 uint32_t tar_autoincr_block
;
239 /* true if packed transfers are supported by the MEM-AP */
240 bool packed_transfers
;
242 /* true if unaligned memory access is not supported by the MEM-AP */
243 bool unaligned_access_bad
;
245 /* true if tar_value is in sync with TAR register */
248 /* MEM AP configuration register indicating LPAE support */
254 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
255 * A DAP has two types of component: one Debug Port (DP), which is a
256 * transport agent; and at least one Access Port (AP), controlling
259 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
260 * Accordingly, this interface is responsible for hiding the transport
261 * differences so upper layer code can largely ignore them.
263 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
264 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
265 * a choice made at board design time (by only using the SWD pins), or
266 * as part of setting up a debug session (if all the dual-role JTAG/SWD
267 * signals are available).
270 const struct dap_ops
*ops
;
272 /* dap transaction list for WAIT support */
273 struct list_head cmd_journal
;
275 /* pool for dap_cmd objects */
276 struct list_head cmd_pool
;
278 /* number of dap_cmd objects in the pool */
279 size_t cmd_pool_size
;
281 struct jtag_tap
*tap
;
283 uint32_t dp_ctrl_stat
;
285 struct adiv5_ap ap
[DP_APSEL_MAX
+ 1];
287 /* The current manually selected AP by the "dap apsel" command */
291 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
292 * indicates no cached value and forces rewrite of the register.
296 /* information about current pending SWjDP-AHBAP transaction */
300 * Holds the pointer to the destination word for the last queued read,
301 * for use with posted AP read sequence optimization.
305 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
306 * despite lack of support in the ARMv7 architecture. Memory access through
307 * the AHB-AP has strange byte ordering these processors, and we need to
308 * swizzle appropriately. */
309 bool ti_be_32_quirks
;
312 * STLINK adapter need to know if last AP operation was read or write, and
313 * in case of write has to flush it with a dummy read from DP_RDBUFF
315 bool stlink_flush_ap_write
;
318 * Signals that an attempt to reestablish communication afresh
319 * should be performed before the next access.
323 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
324 * do not set this bit until later in the bringup sequence */
325 bool ignore_syspwrupack
;
329 * Transport-neutral representation of queued DAP transactions, supporting
330 * both JTAG and SWD transports. All submitted transactions are logically
331 * queued, until the queue is executed by run(). Some implementations might
332 * execute transactions as soon as they're submitted, but no status is made
333 * available until run().
336 /** connect operation for SWD */
337 int (*connect
)(struct adiv5_dap
*dap
);
339 /** send a sequence to the DAP */
340 int (*send_sequence
)(struct adiv5_dap
*dap
, enum swd_special_seq seq
);
342 /** DP register read. */
343 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
345 /** DP register write. */
346 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
349 /** AP register read. */
350 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
352 /** AP register write. */
353 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
356 /** AP operation abort. */
357 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
359 /** Executes all queued DAP operations. */
360 int (*run
)(struct adiv5_dap
*dap
);
362 /** Executes all queued DAP operations but doesn't check
363 * sticky error conditions */
364 int (*sync
)(struct adiv5_dap
*dap
);
366 /** Optional; called at OpenOCD exit */
367 void (*quit
)(struct adiv5_dap
*dap
);
374 AP_TYPE_JTAG_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_NONE
, 0), /* JTAG-AP */
375 AP_TYPE_COM_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_COM
, 0), /* COM-AP */
376 AP_TYPE_AHB3_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 1), /* AHB3 Memory-AP */
377 AP_TYPE_APB_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 2), /* APB2 or APB3 Memory-AP */
378 AP_TYPE_AXI_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 4), /* AXI3 or AXI4 Memory-AP */
379 AP_TYPE_AHB5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 5), /* AHB5 Memory-AP */
380 AP_TYPE_APB4_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 6), /* APB4 Memory-AP */
381 AP_TYPE_AXI5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 7), /* AXI5 Memory-AP */
382 AP_TYPE_AHB5H_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 8), /* AHB5 with enhanced HPROT Memory-AP */
385 /* Check the ap->cfg_reg Long Address field (bit 1)
387 * 0b0: The AP only supports physical addresses 32 bits or smaller
388 * 0b1: The AP supports physical addresses larger than 32 bits
390 * @param ap The AP used for reading.
392 * @return true for 64 bit, false for 32 bit
394 static inline bool is_64bit_ap(struct adiv5_ap
*ap
)
396 return (ap
->cfg_reg
& MEM_AP_REG_CFG_LA
) != 0;
400 * Send an adi-v5 sequence to the DAP.
402 * @param dap The DAP used for reading.
403 * @param seq The sequence to send.
405 * @return ERROR_OK for success, else a fault code.
407 static inline int dap_send_sequence(struct adiv5_dap
*dap
,
408 enum swd_special_seq seq
)
411 return dap
->ops
->send_sequence(dap
, seq
);
415 * Queue a DP register read.
416 * Note that not all DP registers are readable; also, that JTAG and SWD
417 * have slight differences in DP register support.
419 * @param dap The DAP used for reading.
420 * @param reg The two-bit number of the DP register being read.
421 * @param data Pointer saying where to store the register's value
422 * (in host endianness).
424 * @return ERROR_OK for success, else a fault code.
426 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
427 unsigned reg
, uint32_t *data
)
430 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
434 * Queue a DP register write.
435 * Note that not all DP registers are writable; also, that JTAG and SWD
436 * have slight differences in DP register support.
438 * @param dap The DAP used for writing.
439 * @param reg The two-bit number of the DP register being written.
440 * @param data Value being written (host endianness)
442 * @return ERROR_OK for success, else a fault code.
444 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
445 unsigned reg
, uint32_t data
)
448 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
452 * Queue an AP register read.
454 * @param ap The AP used for reading.
455 * @param reg The number of the AP register being read.
456 * @param data Pointer saying where to store the register's value
457 * (in host endianness).
459 * @return ERROR_OK for success, else a fault code.
461 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
462 unsigned reg
, uint32_t *data
)
464 assert(ap
->dap
->ops
);
465 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
469 * Queue an AP register write.
471 * @param ap The AP used for writing.
472 * @param reg The number of the AP register being written.
473 * @param data Value being written (host endianness)
475 * @return ERROR_OK for success, else a fault code.
477 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
478 unsigned reg
, uint32_t data
)
480 assert(ap
->dap
->ops
);
481 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
485 * Queue an AP abort operation. The current AP transaction is aborted,
486 * including any update of the transaction counter. The AP is left in
487 * an unknown state (so it must be re-initialized). For use only after
488 * the AP has reported WAIT status for an extended period.
490 * @param dap The DAP used for writing.
491 * @param ack Pointer to where transaction status will be stored.
493 * @return ERROR_OK for success, else a fault code.
495 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
498 return dap
->ops
->queue_ap_abort(dap
, ack
);
502 * Perform all queued DAP operations, and clear any errors posted in the
503 * CTRL_STAT register when they are done. Note that if more than one AP
504 * operation will be queued, one of the first operations in the queue
505 * should probably enable CORUNDETECT in the CTRL/STAT register.
507 * @param dap The DAP used.
509 * @return ERROR_OK for success, else a fault code.
511 static inline int dap_run(struct adiv5_dap
*dap
)
514 return dap
->ops
->run(dap
);
517 static inline int dap_sync(struct adiv5_dap
*dap
)
521 return dap
->ops
->sync(dap
);
525 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
530 retval
= dap_queue_dp_read(dap
, reg
, value
);
531 if (retval
!= ERROR_OK
)
537 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
538 uint32_t mask
, uint32_t value
, int timeout
)
541 assert((value
& mask
) == value
);
545 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
548 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
552 if ((regval
& mask
) == value
)
559 LOG_DEBUG("DAP: poll %x timeout", reg
);
566 /* Queued MEM-AP memory mapped single word transfers. */
567 int mem_ap_read_u32(struct adiv5_ap
*ap
,
568 target_addr_t address
, uint32_t *value
);
569 int mem_ap_write_u32(struct adiv5_ap
*ap
,
570 target_addr_t address
, uint32_t value
);
572 /* Synchronous MEM-AP memory mapped single word transfers. */
573 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
574 target_addr_t address
, uint32_t *value
);
575 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
576 target_addr_t address
, uint32_t value
);
578 /* Synchronous MEM-AP memory mapped bus block transfers. */
579 int mem_ap_read_buf(struct adiv5_ap
*ap
,
580 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
581 int mem_ap_write_buf(struct adiv5_ap
*ap
,
582 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
584 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
585 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
586 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
587 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
588 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
590 /* Initialisation of the debug system, power domains and registers */
591 int dap_dp_init(struct adiv5_dap
*dap
);
592 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
);
593 int mem_ap_init(struct adiv5_ap
*ap
);
595 /* Invalidate cached DP select and cached TAR and CSW of all APs */
596 void dap_invalidate_cache(struct adiv5_dap
*dap
);
598 /* Probe the AP for ROM Table location */
599 int dap_get_debugbase(struct adiv5_ap
*ap
,
600 target_addr_t
*dbgbase
, uint32_t *apid
);
602 /* Probe Access Ports to find a particular type */
603 int dap_find_ap(struct adiv5_dap
*dap
,
604 enum ap_type type_to_find
,
605 struct adiv5_ap
**ap_out
);
607 static inline struct adiv5_ap
*dap_ap(struct adiv5_dap
*dap
, uint8_t ap_num
)
609 return &dap
->ap
[ap_num
];
612 /* Lookup CoreSight component */
613 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
614 target_addr_t dbgbase
, uint8_t type
, target_addr_t
*addr
, int32_t *idx
);
618 /* Put debug link into SWD mode */
619 int dap_to_swd(struct adiv5_dap
*dap
);
621 /* Put debug link into JTAG mode */
622 int dap_to_jtag(struct adiv5_dap
*dap
);
624 extern const struct command_registration dap_instance_commands
[];
626 struct arm_dap_object
;
627 extern struct adiv5_dap
*dap_instance_by_jim_obj(Jim_Interp
*interp
, Jim_Obj
*o
);
628 extern struct adiv5_dap
*adiv5_get_dap(struct arm_dap_object
*obj
);
629 extern int dap_info_command(struct command_invocation
*cmd
,
630 struct adiv5_ap
*ap
);
631 extern int dap_register_commands(struct command_context
*cmd_ctx
);
632 extern const char *adiv5_dap_name(struct adiv5_dap
*self
);
633 extern const struct swd_driver
*adiv5_dap_swd_driver(struct adiv5_dap
*self
);
634 extern int dap_cleanup_all(void);
636 struct adiv5_private_config
{
638 struct adiv5_dap
*dap
;
641 extern int adiv5_verify_config(struct adiv5_private_config
*pc
);
642 extern int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
);
644 struct adiv5_mem_ap_spot
{
645 struct adiv5_dap
*dap
;
650 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
);
651 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
652 struct jim_getopt_info
*goi
);
654 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
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SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
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+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)