1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2006 by Magnus Lundin *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
10 * Copyright (C) 2019-2021, Ampere Computing LLC *
11 ***************************************************************************/
13 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
14 #define OPENOCD_TARGET_ARM_ADI_V5_H
18 * This defines formats and data structures used to talk to ADIv5 entities.
19 * Those include a DAP, different types of Debug Port (DP), and memory mapped
20 * resources accessed through a MEM-AP.
23 #include <helper/list.h>
25 #include "helper/bits.h"
27 /* JEP106 ID for ARM */
30 /* three-bit ACK values for SWD access (sent LSB first) */
31 #define SWD_ACK_OK 0x1
32 #define SWD_ACK_WAIT 0x2
33 #define SWD_ACK_FAULT 0x4
38 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
40 /* A[3:0] for DP registers; A[1:0] are always zero.
41 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
42 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
43 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
45 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
46 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
47 #define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */
48 #define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */
49 #define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */
50 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
51 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
52 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
53 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
54 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
55 #define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */
56 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
57 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
58 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
59 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
61 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
63 /* Fields of DP_DPIDR register */
64 #define DP_DPIDR_VERSION_SHIFT 12
65 #define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
67 /* Fields of the DP's AP ABORT register */
68 #define DAPABORT (1UL << 0)
69 #define STKCMPCLR (1UL << 1) /* SWD-only */
70 #define STKERRCLR (1UL << 2) /* SWD-only */
71 #define WDERRCLR (1UL << 3) /* SWD-only */
72 #define ORUNERRCLR (1UL << 4) /* SWD-only */
74 /* Fields of register DP_DPIDR1 */
75 #define DP_DPIDR1_ASIZE_MASK (0x7F)
76 #define DP_DPIDR1_ERRMODE BIT(7)
78 /* Fields of register DP_BASEPTR0 */
79 #define DP_BASEPTR0_VALID BIT(0)
81 /* Fields of the DP's CTRL/STAT register */
82 #define CORUNDETECT (1UL << 0)
83 #define SSTICKYORUN (1UL << 1)
84 /* 3:2 - transaction mode (e.g. pushed compare) */
85 #define SSTICKYCMP (1UL << 4)
86 #define SSTICKYERR (1UL << 5)
87 #define READOK (1UL << 6) /* SWD-only */
88 #define WDATAERR (1UL << 7) /* SWD-only */
89 /* 11:8 - mask lanes for pushed compare or verify ops */
90 /* 21:12 - transaction counter */
91 #define CDBGRSTREQ (1UL << 26)
92 #define CDBGRSTACK (1UL << 27)
93 #define CDBGPWRUPREQ (1UL << 28)
94 #define CDBGPWRUPACK (1UL << 29)
95 #define CSYSPWRUPREQ (1UL << 30)
96 #define CSYSPWRUPACK (1UL << 31)
98 #define DP_DLPIDR_PROTVSN 1u
100 #define DP_SELECT_APSEL 0xFF000000
101 #define DP_SELECT_APBANK 0x000000F0
102 #define DP_SELECT_DPBANK 0x0000000F
103 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
105 #define DP_APSEL_MAX (255) /* for ADIv5 only */
106 #define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
108 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
109 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
110 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
111 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
114 /* MEM-AP register addresses */
115 #define ADIV5_MEM_AP_REG_CSW (0x00)
116 #define ADIV5_MEM_AP_REG_TAR (0x04)
117 #define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */
118 #define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */
119 #define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */
120 #define ADIV5_MEM_AP_REG_BD1 (0x14)
121 #define ADIV5_MEM_AP_REG_BD2 (0x18)
122 #define ADIV5_MEM_AP_REG_BD3 (0x1C)
123 #define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */
124 #define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */
125 #define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */
126 #define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */
128 #define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)
129 #define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)
130 #define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)
131 #define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)
132 #define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)
133 #define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)
134 #define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)
135 #define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)
136 #define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)
137 #define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)
138 #define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)
139 #define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)
141 #define MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)
142 #define MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)
143 #define MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)
144 #define MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)
145 #define MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)
146 #define MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)
147 #define MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)
148 #define MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)
149 #define MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)
150 #define MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)
151 #define MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)
152 #define MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)
154 /* Generic AP register address */
155 #define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */
156 #define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)
157 #define AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)
159 /* Fields of the MEM-AP's CSW register */
160 #define CSW_SIZE_MASK 7
164 #define CSW_ADDRINC_MASK (3UL << 4)
165 #define CSW_ADDRINC_OFF 0UL
166 #define CSW_ADDRINC_SINGLE (1UL << 4)
167 #define CSW_ADDRINC_PACKED (2UL << 4)
168 #define CSW_DEVICE_EN (1UL << 6)
169 #define CSW_TRIN_PROG (1UL << 7)
171 /* All fields in bits 12 and above are implementation-defined
172 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
173 * Some bits are shared between buses
175 #define CSW_SPIDEN (1UL << 23)
176 #define CSW_DBGSWENABLE (1UL << 31)
178 /* AHB: Privileged */
179 #define CSW_AHB_HPROT1 (1UL << 25)
180 /* AHB: set HMASTER signals to AHB-AP ID */
181 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
182 /* AHB5: non-secure access via HNONSEC
183 * AHB3: SBO, UNPREDICTABLE if zero */
184 #define CSW_AHB_SPROT (1UL << 30)
185 /* AHB: initial value of csw_default */
186 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
188 /* AXI: Privileged */
189 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
190 /* AXI: Non-secure */
191 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
192 /* AXI: initial value of csw_default */
193 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
195 /* APB: initial value of csw_default */
196 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
198 /* Fields of the MEM-AP's CFG register */
199 #define MEM_AP_REG_CFG_BE BIT(0)
200 #define MEM_AP_REG_CFG_LA BIT(1)
201 #define MEM_AP_REG_CFG_LD BIT(2)
202 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
204 /* Fields of the MEM-AP's IDR register */
205 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
206 #define AP_REG_IDR_REVISION_SHIFT (28)
207 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
208 #define AP_REG_IDR_DESIGNER_SHIFT (17)
209 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
210 #define AP_REG_IDR_CLASS_SHIFT (13)
211 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
212 #define AP_REG_IDR_VARIANT_SHIFT (4)
213 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
214 #define AP_REG_IDR_TYPE_SHIFT (0)
216 #define AP_REG_IDR_CLASS_NONE (0x0)
217 #define AP_REG_IDR_CLASS_COM (0x1)
218 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
220 #define AP_REG_IDR_VALUE(d, c, t) (\
221 (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
222 (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
223 (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
226 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
228 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
229 enum swd_special_seq
{
240 * This represents an ARM Debug Interface (v5) Access Port (AP).
241 * Most common is a MEM-AP, for memory access.
245 * DAP this AP belongs to.
247 struct adiv5_dap
*dap
;
250 * ADIv5: Number of this AP (0~255)
251 * ADIv6: Base address of this AP (4k aligned)
252 * TODO: to be more coherent, it should be renamed apsel
257 * Default value for (MEM-AP) AP_REG_CSW register.
259 uint32_t csw_default
;
262 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
263 * configure an access mode, such as autoincrementing AP_REG_TAR during
264 * word access. "-1" indicates no cached value.
269 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
270 * configure the address being read or written
271 * "-1" indicates no cached value.
273 target_addr_t tar_value
;
276 * Configures how many extra tck clocks are added after starting a
277 * MEM-AP access before we try to read its status (and/or result).
279 uint32_t memaccess_tck
;
281 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
282 uint32_t tar_autoincr_block
;
284 /* true if packed transfers are supported by the MEM-AP */
285 bool packed_transfers
;
287 /* true if unaligned memory access is not supported by the MEM-AP */
288 bool unaligned_access_bad
;
290 /* true if tar_value is in sync with TAR register */
293 /* MEM AP configuration register indicating LPAE support */
296 /* references counter */
297 unsigned int refcount
;
299 /* AP referenced during config. Never put it, even when refcount reaches zero */
300 bool config_ap_never_release
;
305 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
306 * A DAP has two types of component: one Debug Port (DP), which is a
307 * transport agent; and at least one Access Port (AP), controlling
310 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
311 * Accordingly, this interface is responsible for hiding the transport
312 * differences so upper layer code can largely ignore them.
314 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
315 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
316 * a choice made at board design time (by only using the SWD pins), or
317 * as part of setting up a debug session (if all the dual-role JTAG/SWD
318 * signals are available).
321 const struct dap_ops
*ops
;
323 /* dap transaction list for WAIT support */
324 struct list_head cmd_journal
;
326 /* pool for dap_cmd objects */
327 struct list_head cmd_pool
;
329 /* number of dap_cmd objects in the pool */
330 size_t cmd_pool_size
;
332 struct jtag_tap
*tap
;
334 uint32_t dp_ctrl_stat
;
336 struct adiv5_ap ap
[DP_APSEL_MAX
+ 1];
338 /* The current manually selected AP by the "dap apsel" command */
342 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
343 * indicates no cached value and forces rewrite of the register.
347 /* information about current pending SWjDP-AHBAP transaction */
351 * Holds the pointer to the destination word for the last queued read,
352 * for use with posted AP read sequence optimization.
356 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
357 * despite lack of support in the ARMv7 architecture. Memory access through
358 * the AHB-AP has strange byte ordering these processors, and we need to
359 * swizzle appropriately. */
360 bool ti_be_32_quirks
;
362 /* The Nuvoton NPCX M4 has an issue with writing to non-4-byte-aligned mmios.
363 * The work around is to repeat the data in all 4 bytes of DRW */
367 * STLINK adapter need to know if last AP operation was read or write, and
368 * in case of write has to flush it with a dummy read from DP_RDBUFF
370 bool stlink_flush_ap_write
;
373 * Signals that an attempt to reestablish communication afresh
374 * should be performed before the next access.
378 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
379 * do not set this bit until later in the bringup sequence */
380 bool ignore_syspwrupack
;
382 /** Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID */
383 uint32_t multidrop_targetsel
;
384 /** TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured */
385 bool multidrop_dp_id_valid
;
386 /** TINSTANCE field of multidrop_targetsel has been configured */
387 bool multidrop_instance_id_valid
;
390 * Record if enter in SWD required passing through DORMANT
392 bool switch_through_dormant
;
394 /** Indicates ADI version (5, 6 or 0 for unknown) being used */
395 unsigned int adi_version
;
397 /* ADIv6 only field indicating ROM Table address size */
402 * Transport-neutral representation of queued DAP transactions, supporting
403 * both JTAG and SWD transports. All submitted transactions are logically
404 * queued, until the queue is executed by run(). Some implementations might
405 * execute transactions as soon as they're submitted, but no status is made
406 * available until run().
409 /** connect operation for SWD */
410 int (*connect
)(struct adiv5_dap
*dap
);
412 /** send a sequence to the DAP */
413 int (*send_sequence
)(struct adiv5_dap
*dap
, enum swd_special_seq seq
);
415 /** DP register read. */
416 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
418 /** DP register write. */
419 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
422 /** AP register read. */
423 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
425 /** AP register write. */
426 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
429 /** AP operation abort. */
430 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
432 /** Executes all queued DAP operations. */
433 int (*run
)(struct adiv5_dap
*dap
);
435 /** Executes all queued DAP operations but doesn't check
436 * sticky error conditions */
437 int (*sync
)(struct adiv5_dap
*dap
);
439 /** Optional; called at OpenOCD exit */
440 void (*quit
)(struct adiv5_dap
*dap
);
447 AP_TYPE_JTAG_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_NONE
, 0), /* JTAG-AP */
448 AP_TYPE_COM_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_COM
, 0), /* COM-AP */
449 AP_TYPE_AHB3_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 1), /* AHB3 Memory-AP */
450 AP_TYPE_APB_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 2), /* APB2 or APB3 Memory-AP */
451 AP_TYPE_AXI_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 4), /* AXI3 or AXI4 Memory-AP */
452 AP_TYPE_AHB5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 5), /* AHB5 Memory-AP */
453 AP_TYPE_APB4_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 6), /* APB4 Memory-AP */
454 AP_TYPE_AXI5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 7), /* AXI5 Memory-AP */
455 AP_TYPE_AHB5H_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 8), /* AHB5 with enhanced HPROT Memory-AP */
458 /* Check the ap->cfg_reg Long Address field (bit 1)
460 * 0b0: The AP only supports physical addresses 32 bits or smaller
461 * 0b1: The AP supports physical addresses larger than 32 bits
463 * @param ap The AP used for reading.
465 * @return true for 64 bit, false for 32 bit
467 static inline bool is_64bit_ap(struct adiv5_ap
*ap
)
469 return (ap
->cfg_reg
& MEM_AP_REG_CFG_LA
) != 0;
473 * Check if DAP is ADIv6
475 * @param dap The DAP to test
477 * @return true for ADIv6, false for either ADIv5 or unknown version
479 static inline bool is_adiv6(const struct adiv5_dap
*dap
)
481 return dap
->adi_version
== 6;
485 * Send an adi-v5 sequence to the DAP.
487 * @param dap The DAP used for reading.
488 * @param seq The sequence to send.
490 * @return ERROR_OK for success, else a fault code.
492 static inline int dap_send_sequence(struct adiv5_dap
*dap
,
493 enum swd_special_seq seq
)
496 return dap
->ops
->send_sequence(dap
, seq
);
500 * Queue a DP register read.
501 * Note that not all DP registers are readable; also, that JTAG and SWD
502 * have slight differences in DP register support.
504 * @param dap The DAP used for reading.
505 * @param reg The two-bit number of the DP register being read.
506 * @param data Pointer saying where to store the register's value
507 * (in host endianness).
509 * @return ERROR_OK for success, else a fault code.
511 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
512 unsigned reg
, uint32_t *data
)
515 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
519 * Queue a DP register write.
520 * Note that not all DP registers are writable; also, that JTAG and SWD
521 * have slight differences in DP register support.
523 * @param dap The DAP used for writing.
524 * @param reg The two-bit number of the DP register being written.
525 * @param data Value being written (host endianness)
527 * @return ERROR_OK for success, else a fault code.
529 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
530 unsigned reg
, uint32_t data
)
533 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
537 * Queue an AP register read.
539 * @param ap The AP used for reading.
540 * @param reg The number of the AP register being read.
541 * @param data Pointer saying where to store the register's value
542 * (in host endianness).
544 * @return ERROR_OK for success, else a fault code.
546 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
547 unsigned reg
, uint32_t *data
)
549 assert(ap
->dap
->ops
);
550 if (ap
->refcount
== 0) {
552 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" used without get", ap
->ap_num
);
554 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
558 * Queue an AP register write.
560 * @param ap The AP used for writing.
561 * @param reg The number of the AP register being written.
562 * @param data Value being written (host endianness)
564 * @return ERROR_OK for success, else a fault code.
566 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
567 unsigned reg
, uint32_t data
)
569 assert(ap
->dap
->ops
);
570 if (ap
->refcount
== 0) {
572 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" used without get", ap
->ap_num
);
574 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
578 * Queue an AP abort operation. The current AP transaction is aborted,
579 * including any update of the transaction counter. The AP is left in
580 * an unknown state (so it must be re-initialized). For use only after
581 * the AP has reported WAIT status for an extended period.
583 * @param dap The DAP used for writing.
584 * @param ack Pointer to where transaction status will be stored.
586 * @return ERROR_OK for success, else a fault code.
588 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
591 return dap
->ops
->queue_ap_abort(dap
, ack
);
595 * Perform all queued DAP operations, and clear any errors posted in the
596 * CTRL_STAT register when they are done. Note that if more than one AP
597 * operation will be queued, one of the first operations in the queue
598 * should probably enable CORUNDETECT in the CTRL/STAT register.
600 * @param dap The DAP used.
602 * @return ERROR_OK for success, else a fault code.
604 static inline int dap_run(struct adiv5_dap
*dap
)
607 return dap
->ops
->run(dap
);
610 static inline int dap_sync(struct adiv5_dap
*dap
)
614 return dap
->ops
->sync(dap
);
618 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
623 retval
= dap_queue_dp_read(dap
, reg
, value
);
624 if (retval
!= ERROR_OK
)
630 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
631 uint32_t mask
, uint32_t value
, int timeout
)
634 assert((value
& mask
) == value
);
638 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
641 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
645 if ((regval
& mask
) == value
)
652 LOG_DEBUG("DAP: poll %x timeout", reg
);
659 /* Queued MEM-AP memory mapped single word transfers. */
660 int mem_ap_read_u32(struct adiv5_ap
*ap
,
661 target_addr_t address
, uint32_t *value
);
662 int mem_ap_write_u32(struct adiv5_ap
*ap
,
663 target_addr_t address
, uint32_t value
);
665 /* Synchronous MEM-AP memory mapped single word transfers. */
666 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
667 target_addr_t address
, uint32_t *value
);
668 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
669 target_addr_t address
, uint32_t value
);
671 /* Synchronous MEM-AP memory mapped bus block transfers. */
672 int mem_ap_read_buf(struct adiv5_ap
*ap
,
673 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
674 int mem_ap_write_buf(struct adiv5_ap
*ap
,
675 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
677 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
678 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
679 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
680 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
681 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
683 /* Initialisation of the debug system, power domains and registers */
684 int dap_dp_init(struct adiv5_dap
*dap
);
685 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
);
686 int mem_ap_init(struct adiv5_ap
*ap
);
688 /* Invalidate cached DP select and cached TAR and CSW of all APs */
689 void dap_invalidate_cache(struct adiv5_dap
*dap
);
691 /* read ADIv6 baseptr register */
692 int adiv6_dap_read_baseptr(struct command_invocation
*cmd
, struct adiv5_dap
*dap
, target_addr_t
*baseptr
);
694 /* test if ap_num is valid, based on current knowledge of dap */
695 bool is_ap_num_valid(struct adiv5_dap
*dap
, uint64_t ap_num
);
697 /* Probe Access Ports to find a particular type. Increment AP refcount */
698 int dap_find_get_ap(struct adiv5_dap
*dap
,
699 enum ap_type type_to_find
,
700 struct adiv5_ap
**ap_out
);
702 /* Return AP with specified ap_num. Increment AP refcount */
703 struct adiv5_ap
*dap_get_ap(struct adiv5_dap
*dap
, uint64_t ap_num
);
705 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
706 struct adiv5_ap
*dap_get_config_ap(struct adiv5_dap
*dap
, uint64_t ap_num
);
708 /* Decrement AP refcount and release the AP when refcount reaches zero */
709 int dap_put_ap(struct adiv5_ap
*ap
);
711 /** Check if SWD multidrop configuration is valid */
712 static inline bool dap_is_multidrop(struct adiv5_dap
*dap
)
714 return dap
->multidrop_dp_id_valid
&& dap
->multidrop_instance_id_valid
;
717 /* Lookup CoreSight component */
718 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
719 uint8_t type
, target_addr_t
*addr
, int32_t idx
);
723 /* Put debug link into SWD mode */
724 int dap_to_swd(struct adiv5_dap
*dap
);
726 /* Put debug link into JTAG mode */
727 int dap_to_jtag(struct adiv5_dap
*dap
);
729 extern const struct command_registration dap_instance_commands
[];
731 struct arm_dap_object
;
732 extern struct adiv5_dap
*dap_instance_by_jim_obj(Jim_Interp
*interp
, Jim_Obj
*o
);
733 extern struct adiv5_dap
*adiv5_get_dap(struct arm_dap_object
*obj
);
734 extern int dap_info_command(struct command_invocation
*cmd
,
735 struct adiv5_ap
*ap
);
736 extern int dap_register_commands(struct command_context
*cmd_ctx
);
737 extern const char *adiv5_dap_name(struct adiv5_dap
*self
);
738 extern const struct swd_driver
*adiv5_dap_swd_driver(struct adiv5_dap
*self
);
739 extern int dap_cleanup_all(void);
741 struct adiv5_private_config
{
743 struct adiv5_dap
*dap
;
746 extern int adiv5_verify_config(struct adiv5_private_config
*pc
);
747 extern int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
);
749 struct adiv5_mem_ap_spot
{
750 struct adiv5_dap
*dap
;
755 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
);
756 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
757 struct jim_getopt_info
*goi
);
759 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
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