1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
32 #include <helper/list.h>
34 #include "helper/bits.h"
36 /* three-bit ACK values for SWD access (sent LSB first) */
37 #define SWD_ACK_OK 0x1
38 #define SWD_ACK_WAIT 0x2
39 #define SWD_ACK_FAULT 0x4
44 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
46 /* A[3:0] for DP registers; A[1:0] are always zero.
47 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
48 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
49 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
51 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
52 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
53 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
54 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
55 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
56 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
57 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
58 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
59 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
60 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
61 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
63 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
65 /* Fields of the DP's AP ABORT register */
66 #define DAPABORT (1UL << 0)
67 #define STKCMPCLR (1UL << 1) /* SWD-only */
68 #define STKERRCLR (1UL << 2) /* SWD-only */
69 #define WDERRCLR (1UL << 3) /* SWD-only */
70 #define ORUNERRCLR (1UL << 4) /* SWD-only */
72 /* Fields of the DP's CTRL/STAT register */
73 #define CORUNDETECT (1UL << 0)
74 #define SSTICKYORUN (1UL << 1)
75 /* 3:2 - transaction mode (e.g. pushed compare) */
76 #define SSTICKYCMP (1UL << 4)
77 #define SSTICKYERR (1UL << 5)
78 #define READOK (1UL << 6) /* SWD-only */
79 #define WDATAERR (1UL << 7) /* SWD-only */
80 /* 11:8 - mask lanes for pushed compare or verify ops */
81 /* 21:12 - transaction counter */
82 #define CDBGRSTREQ (1UL << 26)
83 #define CDBGRSTACK (1UL << 27)
84 #define CDBGPWRUPREQ (1UL << 28)
85 #define CDBGPWRUPACK (1UL << 29)
86 #define CSYSPWRUPREQ (1UL << 30)
87 #define CSYSPWRUPACK (1UL << 31)
89 #define DP_SELECT_APSEL 0xFF000000
90 #define DP_SELECT_APBANK 0x000000F0
91 #define DP_SELECT_DPBANK 0x0000000F
92 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
94 #define DP_APSEL_MAX (255)
95 #define DP_APSEL_INVALID (-1)
98 /* MEM-AP register addresses */
99 #define MEM_AP_REG_CSW 0x00
100 #define MEM_AP_REG_TAR 0x04
101 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
102 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
103 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
104 #define MEM_AP_REG_BD1 0x14
105 #define MEM_AP_REG_BD2 0x18
106 #define MEM_AP_REG_BD3 0x1C
107 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
108 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
109 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
110 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
111 /* Generic AP register address */
112 #define AP_REG_IDR 0xFC /* RO: Identification Register */
114 /* Fields of the MEM-AP's CSW register */
115 #define CSW_SIZE_MASK 7
119 #define CSW_ADDRINC_MASK (3UL << 4)
120 #define CSW_ADDRINC_OFF 0UL
121 #define CSW_ADDRINC_SINGLE (1UL << 4)
122 #define CSW_ADDRINC_PACKED (2UL << 4)
123 #define CSW_DEVICE_EN (1UL << 6)
124 #define CSW_TRIN_PROG (1UL << 7)
126 /* All fields in bits 12 and above are implementation-defined
127 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
128 * Some bits are shared between buses
130 #define CSW_SPIDEN (1UL << 23)
131 #define CSW_DBGSWENABLE (1UL << 31)
133 /* AHB: Privileged */
134 #define CSW_AHB_HPROT1 (1UL << 25)
135 /* AHB: set HMASTER signals to AHB-AP ID */
136 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
137 /* AHB5: non-secure access via HNONSEC
138 * AHB3: SBO, UNPREDICTABLE if zero */
139 #define CSW_AHB_SPROT (1UL << 30)
140 /* AHB: initial value of csw_default */
141 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
143 /* AXI: Privileged */
144 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
145 /* AXI: Non-secure */
146 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
147 /* AXI: initial value of csw_default */
148 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
150 /* APB: initial value of csw_default */
151 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
153 /* Fields of the MEM-AP's CFG register */
154 #define MEM_AP_REG_CFG_BE BIT(0)
155 #define MEM_AP_REG_CFG_LA BIT(1)
156 #define MEM_AP_REG_CFG_LD BIT(2)
158 /* Fields of the MEM-AP's IDR register */
159 #define IDR_REV (0xFUL << 28)
160 #define IDR_JEP106 (0x7FFUL << 17)
161 #define IDR_CLASS (0xFUL << 13)
162 #define IDR_VARIANT (0xFUL << 4)
163 #define IDR_TYPE (0xFUL << 0)
165 #define IDR_JEP106_ARM 0x04760000
167 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
168 enum swd_special_seq
{
178 * This represents an ARM Debug Interface (v5) Access Port (AP).
179 * Most common is a MEM-AP, for memory access.
183 * DAP this AP belongs to.
185 struct adiv5_dap
*dap
;
193 * Default value for (MEM-AP) AP_REG_CSW register.
195 uint32_t csw_default
;
198 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
199 * configure an access mode, such as autoincrementing AP_REG_TAR during
200 * word access. "-1" indicates no cached value.
205 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
206 * configure the address being read or written
207 * "-1" indicates no cached value.
209 target_addr_t tar_value
;
212 * Configures how many extra tck clocks are added after starting a
213 * MEM-AP access before we try to read its status (and/or result).
215 uint32_t memaccess_tck
;
217 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
218 uint32_t tar_autoincr_block
;
220 /* true if packed transfers are supported by the MEM-AP */
221 bool packed_transfers
;
223 /* true if unaligned memory access is not supported by the MEM-AP */
224 bool unaligned_access_bad
;
226 /* true if tar_value is in sync with TAR register */
229 /* MEM AP configuration register indicating LPAE support */
235 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
236 * A DAP has two types of component: one Debug Port (DP), which is a
237 * transport agent; and at least one Access Port (AP), controlling
240 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
241 * Accordingly, this interface is responsible for hiding the transport
242 * differences so upper layer code can largely ignore them.
244 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
245 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
246 * a choice made at board design time (by only using the SWD pins), or
247 * as part of setting up a debug session (if all the dual-role JTAG/SWD
248 * signals are available).
251 const struct dap_ops
*ops
;
253 /* dap transaction list for WAIT support */
254 struct list_head cmd_journal
;
256 /* pool for dap_cmd objects */
257 struct list_head cmd_pool
;
259 /* number of dap_cmd objects in the pool */
260 size_t cmd_pool_size
;
262 struct jtag_tap
*tap
;
264 uint32_t dp_ctrl_stat
;
266 struct adiv5_ap ap
[DP_APSEL_MAX
+ 1];
268 /* The current manually selected AP by the "dap apsel" command */
272 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
273 * indicates no cached value and forces rewrite of the register.
277 /* information about current pending SWjDP-AHBAP transaction */
281 * Holds the pointer to the destination word for the last queued read,
282 * for use with posted AP read sequence optimization.
286 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
287 * despite lack of support in the ARMv7 architecture. Memory access through
288 * the AHB-AP has strange byte ordering these processors, and we need to
289 * swizzle appropriately. */
290 bool ti_be_32_quirks
;
293 * STLINK adapter need to know if last AP operation was read or write, and
294 * in case of write has to flush it with a dummy read from DP_RDBUFF
296 bool stlink_flush_ap_write
;
299 * Signals that an attempt to reestablish communication afresh
300 * should be performed before the next access.
304 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
305 * do not set this bit until later in the bringup sequence */
306 bool ignore_syspwrupack
;
310 * Transport-neutral representation of queued DAP transactions, supporting
311 * both JTAG and SWD transports. All submitted transactions are logically
312 * queued, until the queue is executed by run(). Some implementations might
313 * execute transactions as soon as they're submitted, but no status is made
314 * available until run().
317 /** connect operation for SWD */
318 int (*connect
)(struct adiv5_dap
*dap
);
320 /** send a sequence to the DAP */
321 int (*send_sequence
)(struct adiv5_dap
*dap
, enum swd_special_seq seq
);
323 /** DP register read. */
324 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
326 /** DP register write. */
327 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
330 /** AP register read. */
331 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
333 /** AP register write. */
334 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
337 /** AP operation abort. */
338 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
340 /** Executes all queued DAP operations. */
341 int (*run
)(struct adiv5_dap
*dap
);
343 /** Executes all queued DAP operations but doesn't check
344 * sticky error conditions */
345 int (*sync
)(struct adiv5_dap
*dap
);
347 /** Optional; called at OpenOCD exit */
348 void (*quit
)(struct adiv5_dap
*dap
);
352 * Access Port classes
355 AP_CLASS_NONE
= 0x00000, /* No class defined */
356 AP_CLASS_MEM_AP
= 0x10000, /* MEM-AP */
363 AP_TYPE_JTAG_AP
= 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
364 AP_TYPE_AHB3_AP
= 0x1, /* AHB3 Memory-AP */
365 AP_TYPE_APB_AP
= 0x2, /* APB Memory-AP */
366 AP_TYPE_AXI_AP
= 0x4, /* AXI Memory-AP */
367 AP_TYPE_AHB5_AP
= 0x5, /* AHB5 Memory-AP. */
370 /* Check the ap->cfg_reg Long Address field (bit 1)
372 * 0b0: The AP only supports physical addresses 32 bits or smaller
373 * 0b1: The AP supports physical addresses larger than 32 bits
375 * @param ap The AP used for reading.
377 * @return true for 64 bit, false for 32 bit
379 static inline bool is_64bit_ap(struct adiv5_ap
*ap
)
381 return (ap
->cfg_reg
& MEM_AP_REG_CFG_LA
) != 0;
385 * Send an adi-v5 sequence to the DAP.
387 * @param dap The DAP used for reading.
388 * @param seq The sequence to send.
390 * @return ERROR_OK for success, else a fault code.
392 static inline int dap_send_sequence(struct adiv5_dap
*dap
,
393 enum swd_special_seq seq
)
396 return dap
->ops
->send_sequence(dap
, seq
);
400 * Queue a DP register read.
401 * Note that not all DP registers are readable; also, that JTAG and SWD
402 * have slight differences in DP register support.
404 * @param dap The DAP used for reading.
405 * @param reg The two-bit number of the DP register being read.
406 * @param data Pointer saying where to store the register's value
407 * (in host endianness).
409 * @return ERROR_OK for success, else a fault code.
411 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
412 unsigned reg
, uint32_t *data
)
415 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
419 * Queue a DP register write.
420 * Note that not all DP registers are writable; also, that JTAG and SWD
421 * have slight differences in DP register support.
423 * @param dap The DAP used for writing.
424 * @param reg The two-bit number of the DP register being written.
425 * @param data Value being written (host endianness)
427 * @return ERROR_OK for success, else a fault code.
429 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
430 unsigned reg
, uint32_t data
)
433 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
437 * Queue an AP register read.
439 * @param ap The AP used for reading.
440 * @param reg The number of the AP register being read.
441 * @param data Pointer saying where to store the register's value
442 * (in host endianness).
444 * @return ERROR_OK for success, else a fault code.
446 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
447 unsigned reg
, uint32_t *data
)
449 assert(ap
->dap
->ops
!= NULL
);
450 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
454 * Queue an AP register write.
456 * @param ap The AP used for writing.
457 * @param reg The number of the AP register being written.
458 * @param data Value being written (host endianness)
460 * @return ERROR_OK for success, else a fault code.
462 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
463 unsigned reg
, uint32_t data
)
465 assert(ap
->dap
->ops
!= NULL
);
466 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
470 * Queue an AP abort operation. The current AP transaction is aborted,
471 * including any update of the transaction counter. The AP is left in
472 * an unknown state (so it must be re-initialized). For use only after
473 * the AP has reported WAIT status for an extended period.
475 * @param dap The DAP used for writing.
476 * @param ack Pointer to where transaction status will be stored.
478 * @return ERROR_OK for success, else a fault code.
480 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
483 return dap
->ops
->queue_ap_abort(dap
, ack
);
487 * Perform all queued DAP operations, and clear any errors posted in the
488 * CTRL_STAT register when they are done. Note that if more than one AP
489 * operation will be queued, one of the first operations in the queue
490 * should probably enable CORUNDETECT in the CTRL/STAT register.
492 * @param dap The DAP used.
494 * @return ERROR_OK for success, else a fault code.
496 static inline int dap_run(struct adiv5_dap
*dap
)
499 return dap
->ops
->run(dap
);
502 static inline int dap_sync(struct adiv5_dap
*dap
)
506 return dap
->ops
->sync(dap
);
510 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
515 retval
= dap_queue_dp_read(dap
, reg
, value
);
516 if (retval
!= ERROR_OK
)
522 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
523 uint32_t mask
, uint32_t value
, int timeout
)
526 assert((value
& mask
) == value
);
530 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
533 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
537 if ((regval
& mask
) == value
)
544 LOG_DEBUG("DAP: poll %x timeout", reg
);
551 /* Queued MEM-AP memory mapped single word transfers. */
552 int mem_ap_read_u32(struct adiv5_ap
*ap
,
553 target_addr_t address
, uint32_t *value
);
554 int mem_ap_write_u32(struct adiv5_ap
*ap
,
555 target_addr_t address
, uint32_t value
);
557 /* Synchronous MEM-AP memory mapped single word transfers. */
558 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
559 target_addr_t address
, uint32_t *value
);
560 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
561 target_addr_t address
, uint32_t value
);
563 /* Synchronous MEM-AP memory mapped bus block transfers. */
564 int mem_ap_read_buf(struct adiv5_ap
*ap
,
565 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
566 int mem_ap_write_buf(struct adiv5_ap
*ap
,
567 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
569 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
570 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
571 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
572 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
573 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
575 /* Initialisation of the debug system, power domains and registers */
576 int dap_dp_init(struct adiv5_dap
*dap
);
577 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
);
578 int mem_ap_init(struct adiv5_ap
*ap
);
580 /* Invalidate cached DP select and cached TAR and CSW of all APs */
581 void dap_invalidate_cache(struct adiv5_dap
*dap
);
583 /* Probe the AP for ROM Table location */
584 int dap_get_debugbase(struct adiv5_ap
*ap
,
585 target_addr_t
*dbgbase
, uint32_t *apid
);
587 /* Probe Access Ports to find a particular type */
588 int dap_find_ap(struct adiv5_dap
*dap
,
589 enum ap_type type_to_find
,
590 struct adiv5_ap
**ap_out
);
592 static inline struct adiv5_ap
*dap_ap(struct adiv5_dap
*dap
, uint8_t ap_num
)
594 return &dap
->ap
[ap_num
];
597 /* Lookup CoreSight component */
598 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
599 target_addr_t dbgbase
, uint8_t type
, target_addr_t
*addr
, int32_t *idx
);
603 /* Put debug link into SWD mode */
604 int dap_to_swd(struct adiv5_dap
*dap
);
606 /* Put debug link into JTAG mode */
607 int dap_to_jtag(struct adiv5_dap
*dap
);
609 extern const struct command_registration dap_instance_commands
[];
611 struct arm_dap_object
;
612 extern struct adiv5_dap
*dap_instance_by_jim_obj(Jim_Interp
*interp
, Jim_Obj
*o
);
613 extern struct adiv5_dap
*adiv5_get_dap(struct arm_dap_object
*obj
);
614 extern int dap_info_command(struct command_invocation
*cmd
,
615 struct adiv5_ap
*ap
);
616 extern int dap_register_commands(struct command_context
*cmd_ctx
);
617 extern const char *adiv5_dap_name(struct adiv5_dap
*self
);
618 extern const struct swd_driver
*adiv5_dap_swd_driver(struct adiv5_dap
*self
);
619 extern int dap_cleanup_all(void);
621 struct adiv5_private_config
{
623 struct adiv5_dap
*dap
;
626 extern int adiv5_verify_config(struct adiv5_private_config
*pc
);
627 extern int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
);
629 struct adiv5_mem_ap_spot
{
630 struct adiv5_dap
*dap
;
635 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
);
636 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
637 struct jim_getopt_info
*goi
);
639 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
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