1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2019-2021, Ampere Computing LLC *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
22 ***************************************************************************/
24 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
25 #define OPENOCD_TARGET_ARM_ADI_V5_H
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
34 #include <helper/list.h>
36 #include "helper/bits.h"
38 /* JEP106 ID for ARM */
41 /* three-bit ACK values for SWD access (sent LSB first) */
42 #define SWD_ACK_OK 0x1
43 #define SWD_ACK_WAIT 0x2
44 #define SWD_ACK_FAULT 0x4
49 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
51 /* A[3:0] for DP registers; A[1:0] are always zero.
52 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
53 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
54 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
56 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
57 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
58 #define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */
59 #define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */
60 #define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */
61 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
62 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
63 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
64 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
65 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
66 #define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */
67 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
68 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
69 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
70 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
72 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
74 /* Fields of DP_DPIDR register */
75 #define DP_DPIDR_VERSION_SHIFT 12
76 #define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
78 /* Fields of the DP's AP ABORT register */
79 #define DAPABORT (1UL << 0)
80 #define STKCMPCLR (1UL << 1) /* SWD-only */
81 #define STKERRCLR (1UL << 2) /* SWD-only */
82 #define WDERRCLR (1UL << 3) /* SWD-only */
83 #define ORUNERRCLR (1UL << 4) /* SWD-only */
85 /* Fields of register DP_DPIDR1 */
86 #define DP_DPIDR1_ASIZE_MASK (0x7F)
87 #define DP_DPIDR1_ERRMODE BIT(7)
89 /* Fields of register DP_BASEPTR0 */
90 #define DP_BASEPTR0_VALID BIT(0)
92 /* Fields of the DP's CTRL/STAT register */
93 #define CORUNDETECT (1UL << 0)
94 #define SSTICKYORUN (1UL << 1)
95 /* 3:2 - transaction mode (e.g. pushed compare) */
96 #define SSTICKYCMP (1UL << 4)
97 #define SSTICKYERR (1UL << 5)
98 #define READOK (1UL << 6) /* SWD-only */
99 #define WDATAERR (1UL << 7) /* SWD-only */
100 /* 11:8 - mask lanes for pushed compare or verify ops */
101 /* 21:12 - transaction counter */
102 #define CDBGRSTREQ (1UL << 26)
103 #define CDBGRSTACK (1UL << 27)
104 #define CDBGPWRUPREQ (1UL << 28)
105 #define CDBGPWRUPACK (1UL << 29)
106 #define CSYSPWRUPREQ (1UL << 30)
107 #define CSYSPWRUPACK (1UL << 31)
109 #define DP_DLPIDR_PROTVSN 1u
111 #define DP_SELECT_APSEL 0xFF000000
112 #define DP_SELECT_APBANK 0x000000F0
113 #define DP_SELECT_DPBANK 0x0000000F
114 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
116 #define DP_APSEL_MAX (255) /* for ADIv5 only */
117 #define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
119 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
120 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
121 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
122 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
125 /* MEM-AP register addresses */
126 #define ADIV5_MEM_AP_REG_CSW (0x00)
127 #define ADIV5_MEM_AP_REG_TAR (0x04)
128 #define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */
129 #define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */
130 #define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */
131 #define ADIV5_MEM_AP_REG_BD1 (0x14)
132 #define ADIV5_MEM_AP_REG_BD2 (0x18)
133 #define ADIV5_MEM_AP_REG_BD3 (0x1C)
134 #define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */
135 #define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */
136 #define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */
137 #define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */
139 #define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)
140 #define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)
141 #define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)
142 #define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)
143 #define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)
144 #define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)
145 #define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)
146 #define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)
147 #define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)
148 #define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)
149 #define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)
150 #define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)
152 #define MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)
153 #define MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)
154 #define MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)
155 #define MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)
156 #define MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)
157 #define MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)
158 #define MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)
159 #define MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)
160 #define MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)
161 #define MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)
162 #define MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)
163 #define MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)
165 /* Generic AP register address */
166 #define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */
167 #define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)
168 #define AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)
170 /* Fields of the MEM-AP's CSW register */
171 #define CSW_SIZE_MASK 7
175 #define CSW_ADDRINC_MASK (3UL << 4)
176 #define CSW_ADDRINC_OFF 0UL
177 #define CSW_ADDRINC_SINGLE (1UL << 4)
178 #define CSW_ADDRINC_PACKED (2UL << 4)
179 #define CSW_DEVICE_EN (1UL << 6)
180 #define CSW_TRIN_PROG (1UL << 7)
182 /* All fields in bits 12 and above are implementation-defined
183 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
184 * Some bits are shared between buses
186 #define CSW_SPIDEN (1UL << 23)
187 #define CSW_DBGSWENABLE (1UL << 31)
189 /* AHB: Privileged */
190 #define CSW_AHB_HPROT1 (1UL << 25)
191 /* AHB: set HMASTER signals to AHB-AP ID */
192 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
193 /* AHB5: non-secure access via HNONSEC
194 * AHB3: SBO, UNPREDICTABLE if zero */
195 #define CSW_AHB_SPROT (1UL << 30)
196 /* AHB: initial value of csw_default */
197 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
199 /* AXI: Privileged */
200 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
201 /* AXI: Non-secure */
202 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
203 /* AXI: initial value of csw_default */
204 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
206 /* APB: initial value of csw_default */
207 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
209 /* Fields of the MEM-AP's CFG register */
210 #define MEM_AP_REG_CFG_BE BIT(0)
211 #define MEM_AP_REG_CFG_LA BIT(1)
212 #define MEM_AP_REG_CFG_LD BIT(2)
213 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
215 /* Fields of the MEM-AP's IDR register */
216 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
217 #define AP_REG_IDR_REVISION_SHIFT (28)
218 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
219 #define AP_REG_IDR_DESIGNER_SHIFT (17)
220 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
221 #define AP_REG_IDR_CLASS_SHIFT (13)
222 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
223 #define AP_REG_IDR_VARIANT_SHIFT (4)
224 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
225 #define AP_REG_IDR_TYPE_SHIFT (0)
227 #define AP_REG_IDR_CLASS_NONE (0x0)
228 #define AP_REG_IDR_CLASS_COM (0x1)
229 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
231 #define AP_REG_IDR_VALUE(d, c, t) (\
232 (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
233 (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
234 (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
237 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
239 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
240 enum swd_special_seq
{
251 * This represents an ARM Debug Interface (v5) Access Port (AP).
252 * Most common is a MEM-AP, for memory access.
256 * DAP this AP belongs to.
258 struct adiv5_dap
*dap
;
261 * ADIv5: Number of this AP (0~255)
262 * ADIv6: Base address of this AP (4k aligned)
263 * TODO: to be more coherent, it should be renamed apsel
268 * Default value for (MEM-AP) AP_REG_CSW register.
270 uint32_t csw_default
;
273 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
274 * configure an access mode, such as autoincrementing AP_REG_TAR during
275 * word access. "-1" indicates no cached value.
280 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
281 * configure the address being read or written
282 * "-1" indicates no cached value.
284 target_addr_t tar_value
;
287 * Configures how many extra tck clocks are added after starting a
288 * MEM-AP access before we try to read its status (and/or result).
290 uint32_t memaccess_tck
;
292 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
293 uint32_t tar_autoincr_block
;
295 /* true if packed transfers are supported by the MEM-AP */
296 bool packed_transfers
;
298 /* true if unaligned memory access is not supported by the MEM-AP */
299 bool unaligned_access_bad
;
301 /* true if tar_value is in sync with TAR register */
304 /* MEM AP configuration register indicating LPAE support */
307 /* references counter */
308 unsigned int refcount
;
310 /* AP referenced during config. Never put it, even when refcount reaches zero */
311 bool config_ap_never_release
;
316 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
317 * A DAP has two types of component: one Debug Port (DP), which is a
318 * transport agent; and at least one Access Port (AP), controlling
321 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
322 * Accordingly, this interface is responsible for hiding the transport
323 * differences so upper layer code can largely ignore them.
325 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
326 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
327 * a choice made at board design time (by only using the SWD pins), or
328 * as part of setting up a debug session (if all the dual-role JTAG/SWD
329 * signals are available).
332 const struct dap_ops
*ops
;
334 /* dap transaction list for WAIT support */
335 struct list_head cmd_journal
;
337 /* pool for dap_cmd objects */
338 struct list_head cmd_pool
;
340 /* number of dap_cmd objects in the pool */
341 size_t cmd_pool_size
;
343 struct jtag_tap
*tap
;
345 uint32_t dp_ctrl_stat
;
347 struct adiv5_ap ap
[DP_APSEL_MAX
+ 1];
349 /* The current manually selected AP by the "dap apsel" command */
353 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
354 * indicates no cached value and forces rewrite of the register.
358 /* information about current pending SWjDP-AHBAP transaction */
362 * Holds the pointer to the destination word for the last queued read,
363 * for use with posted AP read sequence optimization.
367 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
368 * despite lack of support in the ARMv7 architecture. Memory access through
369 * the AHB-AP has strange byte ordering these processors, and we need to
370 * swizzle appropriately. */
371 bool ti_be_32_quirks
;
374 * STLINK adapter need to know if last AP operation was read or write, and
375 * in case of write has to flush it with a dummy read from DP_RDBUFF
377 bool stlink_flush_ap_write
;
380 * Signals that an attempt to reestablish communication afresh
381 * should be performed before the next access.
385 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
386 * do not set this bit until later in the bringup sequence */
387 bool ignore_syspwrupack
;
389 /** Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID */
390 uint32_t multidrop_targetsel
;
391 /** TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured */
392 bool multidrop_dp_id_valid
;
393 /** TINSTANCE field of multidrop_targetsel has been configured */
394 bool multidrop_instance_id_valid
;
397 * Record if enter in SWD required passing through DORMANT
399 bool switch_through_dormant
;
401 /** Indicates ADI version (5, 6 or 0 for unknown) being used */
402 unsigned int adi_version
;
404 /* ADIv6 only field indicating ROM Table address size */
409 * Transport-neutral representation of queued DAP transactions, supporting
410 * both JTAG and SWD transports. All submitted transactions are logically
411 * queued, until the queue is executed by run(). Some implementations might
412 * execute transactions as soon as they're submitted, but no status is made
413 * available until run().
416 /** connect operation for SWD */
417 int (*connect
)(struct adiv5_dap
*dap
);
419 /** send a sequence to the DAP */
420 int (*send_sequence
)(struct adiv5_dap
*dap
, enum swd_special_seq seq
);
422 /** DP register read. */
423 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
425 /** DP register write. */
426 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
429 /** AP register read. */
430 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
432 /** AP register write. */
433 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
436 /** AP operation abort. */
437 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
439 /** Executes all queued DAP operations. */
440 int (*run
)(struct adiv5_dap
*dap
);
442 /** Executes all queued DAP operations but doesn't check
443 * sticky error conditions */
444 int (*sync
)(struct adiv5_dap
*dap
);
446 /** Optional; called at OpenOCD exit */
447 void (*quit
)(struct adiv5_dap
*dap
);
454 AP_TYPE_JTAG_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_NONE
, 0), /* JTAG-AP */
455 AP_TYPE_COM_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_COM
, 0), /* COM-AP */
456 AP_TYPE_AHB3_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 1), /* AHB3 Memory-AP */
457 AP_TYPE_APB_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 2), /* APB2 or APB3 Memory-AP */
458 AP_TYPE_AXI_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 4), /* AXI3 or AXI4 Memory-AP */
459 AP_TYPE_AHB5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 5), /* AHB5 Memory-AP */
460 AP_TYPE_APB4_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 6), /* APB4 Memory-AP */
461 AP_TYPE_AXI5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 7), /* AXI5 Memory-AP */
462 AP_TYPE_AHB5H_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 8), /* AHB5 with enhanced HPROT Memory-AP */
465 /* Check the ap->cfg_reg Long Address field (bit 1)
467 * 0b0: The AP only supports physical addresses 32 bits or smaller
468 * 0b1: The AP supports physical addresses larger than 32 bits
470 * @param ap The AP used for reading.
472 * @return true for 64 bit, false for 32 bit
474 static inline bool is_64bit_ap(struct adiv5_ap
*ap
)
476 return (ap
->cfg_reg
& MEM_AP_REG_CFG_LA
) != 0;
480 * Check if DAP is ADIv6
482 * @param dap The DAP to test
484 * @return true for ADIv6, false for either ADIv5 or unknown version
486 static inline bool is_adiv6(const struct adiv5_dap
*dap
)
488 return dap
->adi_version
== 6;
492 * Send an adi-v5 sequence to the DAP.
494 * @param dap The DAP used for reading.
495 * @param seq The sequence to send.
497 * @return ERROR_OK for success, else a fault code.
499 static inline int dap_send_sequence(struct adiv5_dap
*dap
,
500 enum swd_special_seq seq
)
503 return dap
->ops
->send_sequence(dap
, seq
);
507 * Queue a DP register read.
508 * Note that not all DP registers are readable; also, that JTAG and SWD
509 * have slight differences in DP register support.
511 * @param dap The DAP used for reading.
512 * @param reg The two-bit number of the DP register being read.
513 * @param data Pointer saying where to store the register's value
514 * (in host endianness).
516 * @return ERROR_OK for success, else a fault code.
518 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
519 unsigned reg
, uint32_t *data
)
522 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
526 * Queue a DP register write.
527 * Note that not all DP registers are writable; also, that JTAG and SWD
528 * have slight differences in DP register support.
530 * @param dap The DAP used for writing.
531 * @param reg The two-bit number of the DP register being written.
532 * @param data Value being written (host endianness)
534 * @return ERROR_OK for success, else a fault code.
536 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
537 unsigned reg
, uint32_t data
)
540 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
544 * Queue an AP register read.
546 * @param ap The AP used for reading.
547 * @param reg The number of the AP register being read.
548 * @param data Pointer saying where to store the register's value
549 * (in host endianness).
551 * @return ERROR_OK for success, else a fault code.
553 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
554 unsigned reg
, uint32_t *data
)
556 assert(ap
->dap
->ops
);
557 if (ap
->refcount
== 0) {
559 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" used without get", ap
->ap_num
);
561 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
565 * Queue an AP register write.
567 * @param ap The AP used for writing.
568 * @param reg The number of the AP register being written.
569 * @param data Value being written (host endianness)
571 * @return ERROR_OK for success, else a fault code.
573 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
574 unsigned reg
, uint32_t data
)
576 assert(ap
->dap
->ops
);
577 if (ap
->refcount
== 0) {
579 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" used without get", ap
->ap_num
);
581 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
585 * Queue an AP abort operation. The current AP transaction is aborted,
586 * including any update of the transaction counter. The AP is left in
587 * an unknown state (so it must be re-initialized). For use only after
588 * the AP has reported WAIT status for an extended period.
590 * @param dap The DAP used for writing.
591 * @param ack Pointer to where transaction status will be stored.
593 * @return ERROR_OK for success, else a fault code.
595 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
598 return dap
->ops
->queue_ap_abort(dap
, ack
);
602 * Perform all queued DAP operations, and clear any errors posted in the
603 * CTRL_STAT register when they are done. Note that if more than one AP
604 * operation will be queued, one of the first operations in the queue
605 * should probably enable CORUNDETECT in the CTRL/STAT register.
607 * @param dap The DAP used.
609 * @return ERROR_OK for success, else a fault code.
611 static inline int dap_run(struct adiv5_dap
*dap
)
614 return dap
->ops
->run(dap
);
617 static inline int dap_sync(struct adiv5_dap
*dap
)
621 return dap
->ops
->sync(dap
);
625 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
630 retval
= dap_queue_dp_read(dap
, reg
, value
);
631 if (retval
!= ERROR_OK
)
637 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
638 uint32_t mask
, uint32_t value
, int timeout
)
641 assert((value
& mask
) == value
);
645 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
648 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
652 if ((regval
& mask
) == value
)
659 LOG_DEBUG("DAP: poll %x timeout", reg
);
666 /* Queued MEM-AP memory mapped single word transfers. */
667 int mem_ap_read_u32(struct adiv5_ap
*ap
,
668 target_addr_t address
, uint32_t *value
);
669 int mem_ap_write_u32(struct adiv5_ap
*ap
,
670 target_addr_t address
, uint32_t value
);
672 /* Synchronous MEM-AP memory mapped single word transfers. */
673 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
674 target_addr_t address
, uint32_t *value
);
675 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
676 target_addr_t address
, uint32_t value
);
678 /* Synchronous MEM-AP memory mapped bus block transfers. */
679 int mem_ap_read_buf(struct adiv5_ap
*ap
,
680 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
681 int mem_ap_write_buf(struct adiv5_ap
*ap
,
682 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
684 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
685 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
686 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
687 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
688 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
690 /* Initialisation of the debug system, power domains and registers */
691 int dap_dp_init(struct adiv5_dap
*dap
);
692 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
);
693 int mem_ap_init(struct adiv5_ap
*ap
);
695 /* Invalidate cached DP select and cached TAR and CSW of all APs */
696 void dap_invalidate_cache(struct adiv5_dap
*dap
);
698 /* read ADIv6 baseptr register */
699 int adiv6_dap_read_baseptr(struct command_invocation
*cmd
, struct adiv5_dap
*dap
, target_addr_t
*baseptr
);
701 /* test if ap_num is valid, based on current knowledge of dap */
702 bool is_ap_num_valid(struct adiv5_dap
*dap
, uint64_t ap_num
);
704 /* Probe Access Ports to find a particular type. Increment AP refcount */
705 int dap_find_get_ap(struct adiv5_dap
*dap
,
706 enum ap_type type_to_find
,
707 struct adiv5_ap
**ap_out
);
709 /* Return AP with specified ap_num. Increment AP refcount */
710 struct adiv5_ap
*dap_get_ap(struct adiv5_dap
*dap
, uint64_t ap_num
);
712 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
713 struct adiv5_ap
*dap_get_config_ap(struct adiv5_dap
*dap
, uint64_t ap_num
);
715 /* Decrement AP refcount and release the AP when refcount reaches zero */
716 int dap_put_ap(struct adiv5_ap
*ap
);
718 /** Check if SWD multidrop configuration is valid */
719 static inline bool dap_is_multidrop(struct adiv5_dap
*dap
)
721 return dap
->multidrop_dp_id_valid
&& dap
->multidrop_instance_id_valid
;
724 /* Lookup CoreSight component */
725 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
726 uint8_t type
, target_addr_t
*addr
, int32_t idx
);
730 /* Put debug link into SWD mode */
731 int dap_to_swd(struct adiv5_dap
*dap
);
733 /* Put debug link into JTAG mode */
734 int dap_to_jtag(struct adiv5_dap
*dap
);
736 extern const struct command_registration dap_instance_commands
[];
738 struct arm_dap_object
;
739 extern struct adiv5_dap
*dap_instance_by_jim_obj(Jim_Interp
*interp
, Jim_Obj
*o
);
740 extern struct adiv5_dap
*adiv5_get_dap(struct arm_dap_object
*obj
);
741 extern int dap_info_command(struct command_invocation
*cmd
,
742 struct adiv5_ap
*ap
);
743 extern int dap_register_commands(struct command_context
*cmd_ctx
);
744 extern const char *adiv5_dap_name(struct adiv5_dap
*self
);
745 extern const struct swd_driver
*adiv5_dap_swd_driver(struct adiv5_dap
*self
);
746 extern int dap_cleanup_all(void);
748 struct adiv5_private_config
{
750 struct adiv5_dap
*dap
;
753 extern int adiv5_verify_config(struct adiv5_private_config
*pc
);
754 extern int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
);
756 struct adiv5_mem_ap_spot
{
757 struct adiv5_dap
*dap
;
762 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
);
763 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
764 struct jim_getopt_info
*goi
);
766 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
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