src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARM_ADI_V5_H
  24 #define ARM_ADI_V5_H
  25
  26 /**
  27  * @file
  28  * This defines formats and data structures used to talk to ADIv5 entities.
  29  * Those include a DAP, different types of Debug Port (DP), and memory mapped
  30  * resources accessed through a MEM-AP.
  31  */
  32
  33 #include "arm_jtag.h"
  34
  35 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
  36 #define JTAG_DP_ABORT           0x8
  37 #define JTAG_DP_DPACC           0xA
  38 #define JTAG_DP_APACC           0xB
  39 #define JTAG_DP_IDCODE          0xE
  40
  41 /* three-bit ACK values for DPACC and APACC reads */
  42 #define JTAG_ACK_OK_FAULT       0x2
  43 #define JTAG_ACK_WAIT           0x1
  44
  45 /* three-bit ACK values for SWD access (sent LSB first) */
  46 #define SWD_ACK_OK              0x4
  47 #define SWD_ACK_WAIT            0x2
  48 #define SWD_ACK_FAULT           0x1
  49
  50 #define DPAP_WRITE              0
  51 #define DPAP_READ               1
  52
  53 /* A[3:0] for DP registers; A[1:0] are always zero.
  54  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  55  *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
  56  * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
  57  */
  58 #define DP_IDCODE               0               /* SWD: read */
  59 #define DP_ABORT                0               /* SWD: write */
  60 #define DP_CTRL_STAT            0x4             /* r/w */
  61 #define DP_WCR                  0x4             /* SWD: r/w (mux CTRLSEL) */
  62 #define DP_RESEND               0x8             /* SWD: read */
  63 #define DP_SELECT               0x8             /* JTAG: r/w; SWD: write */
  64 #define DP_RDBUFF               0xC             /* read-only */
  65
  66 /* Fields of the DP's AP ABORT register */
  67 #define DAPABORT                (1 << 0)
  68 #define STKCMPCLR               (1 << 1)        /* SWD-only */
  69 #define STKERRCLR               (1 << 2)        /* SWD-only */
  70 #define WDERRCLR                (1 << 3)        /* SWD-only */
  71 #define ORUNERRCLR              (1 << 4)        /* SWD-only */
  72
  73 /* Fields of the DP's CTRL/STAT register */
  74 #define CORUNDETECT             (1 << 0)
  75 #define SSTICKYORUN             (1 << 1)
  76 /* 3:2 - transaction mode (e.g. pushed compare) */
  77 #define SSTICKYCMP              (1 << 4)
  78 #define SSTICKYERR              (1 << 5)
  79 #define READOK                  (1 << 6)        /* SWD-only */
  80 #define WDATAERR                (1 << 7)        /* SWD-only */
  81 /* 11:8 - mask lanes for pushed compare or verify ops */
  82 /* 21:12 - transaction counter */
  83 #define CDBGRSTREQ              (1 << 26)
  84 #define CDBGRSTACK              (1 << 27)
  85 #define CDBGPWRUPREQ    (1 << 28)
  86 #define CDBGPWRUPACK    (1 << 29)
  87 #define CSYSPWRUPREQ    (1 << 30)
  88 #define CSYSPWRUPACK    (1 << 31)
  89
  90 /* MEM-AP register addresses */
  91 /* TODO: rename as MEM_AP_REG_* */
  92 #define AP_REG_CSW              0x00
  93 #define AP_REG_TAR              0x04
  94 #define AP_REG_DRW              0x0C
  95 #define AP_REG_BD0              0x10
  96 #define AP_REG_BD1              0x14
  97 #define AP_REG_BD2              0x18
  98 #define AP_REG_BD3              0x1C
  99 #define AP_REG_CFG              0xF4            /* big endian? */
 100 #define AP_REG_BASE             0xF8
 101
 102 /* Generic AP register address */
 103 #define AP_REG_IDR              0xFC
 104
 105 /* Fields of the MEM-AP's CSW register */
 106 #define CSW_8BIT                0
 107 #define CSW_16BIT               1
 108 #define CSW_32BIT               2
 109 #define CSW_ADDRINC_MASK        (3 << 4)
 110 #define CSW_ADDRINC_OFF         0
 111 #define CSW_ADDRINC_SINGLE      (1 << 4)
 112 #define CSW_ADDRINC_PACKED      (2 << 4)
 113 #define CSW_DEVICE_EN           (1 << 6)
 114 #define CSW_TRIN_PROG           (1 << 7)
 115 #define CSW_SPIDEN                      (1 << 23)
 116 /* 30:24 - implementation-defined! */
 117 #define CSW_HPROT                       (1 << 25)               /* ? */
 118 #define CSW_MASTER_DEBUG        (1 << 29)               /* ? */
 119 #define CSW_DBGSWENABLE         (1 << 31)
 120
 121 /* transaction mode */
 122 #define TRANS_MODE_NONE                 0
 123 /* Transaction waits for previous to complete */
 124 #define TRANS_MODE_ATOMIC               1
 125 /* Freerunning transactions with delays and overrun checking */
 126 #define TRANS_MODE_COMPOSITE    2
 127
 128 /**
 129  * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
 130  * A DAP has two types of component:  one Debug Port (DP), which is a
 131  * transport agent; and at least one Access Port (AP), controlling
 132  * resource access.  Most common is a MEM-AP, for memory access.
 133  *
 134  * @todo Rename "swjdp_common" as "dap".  Use of SWJ-DP is optional!
 135  */
 136 struct swjdp_common
 137 {
 138         struct arm_jtag *jtag_info;
 139         /* Control config */
 140         uint32_t dp_ctrl_stat;
 141
 142         /**
 143          * Cache for DP_SELECT bits identifying the current AP.  A DAP may
 144          * connect to multiple APs, such as one MEM-AP for general access,
 145          * another reserved for accessing debug modules, and a JTAG-DP.
 146          * "-1" indicates no cached value.
 147          */
 148         uint32_t apsel;
 149
 150         /**
 151          * Cache for DP_SELECT bits identifying the current four-word AP
 152          * register bank.  This caches AP register addresss bits 7:4; JTAG
 153          * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
 154          * "-1" indicates no cached value.
 155          */
 156         uint32_t ap_bank_value;
 157
 158         /**
 159          * Cache for (MEM-AP) AP_REG_CSW register value.  This is written to
 160          * configure an access mode, such as autoincrementing AP_REG_TAR during
 161          * word access.  "-1" indicates no cached value.
 162          */
 163         uint32_t ap_csw_value;
 164
 165         /**
 166          * Cache for (MEM-AP) AP_REG_TAR register value This is written to
 167          * configure the address being read or written
 168          * "-1" indicates no cached value.
 169          */
 170         uint32_t ap_tar_value;
 171
 172         /* information about current pending SWjDP-AHBAP transaction */
 173         uint8_t  trans_mode;
 174         uint8_t  trans_rw;
 175         uint8_t  ack;
 176         /**
 177          * Configures how many extra tck clocks are added after starting a
 178          * MEM-AP access before we try to read its status (and/or result).
 179          */
 180         uint32_t        memaccess_tck;
 181         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 182         uint32_t tar_autoincr_block;
 183
 184 };
 185
 186 /** Accessor for currently selected DAP-AP number (0..255) */
 187 static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
 188 {
 189         return (uint8_t)(swjdp ->apsel >> 24);
 190 }
 191
 192 /* AP selection applies to future AP transactions */
 193 void dap_ap_select(struct swjdp_common *dap,uint8_t apsel);
 194
 195 /* AP transactions ... synchronous given TRANS_MODE_ATOMIC */
 196 int dap_setup_accessport(struct swjdp_common *swjdp,
 197                 uint32_t csw, uint32_t tar);
 198 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 199                 uint32_t addr, uint32_t value);
 200 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 201                 uint32_t addr, uint32_t *value);
 202
 203 /* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */
 204 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp);
 205
 206 /* Queued MEM-AP memory mapped single word transfers */
 207 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
 208 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
 209
 210 /* Synchronous MEM-AP memory mapped single word transfers */
 211 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
 212                 uint32_t address, uint32_t *value);
 213 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,
 214                 uint32_t address, uint32_t value);
 215
 216 /* MEM-AP memory mapped bus block transfers */
 217 int mem_ap_read_buf_u8(struct swjdp_common *swjdp,
 218                 uint8_t *buffer, int count, uint32_t address);
 219 int mem_ap_read_buf_u16(struct swjdp_common *swjdp,
 220                 uint8_t *buffer, int count, uint32_t address);
 221 int mem_ap_read_buf_u32(struct swjdp_common *swjdp,
 222                 uint8_t *buffer, int count, uint32_t address);
 223
 224 int mem_ap_write_buf_u8(struct swjdp_common *swjdp,
 225                 uint8_t *buffer, int count, uint32_t address);
 226 int mem_ap_write_buf_u16(struct swjdp_common *swjdp,
 227                 uint8_t *buffer, int count, uint32_t address);
 228 int mem_ap_write_buf_u32(struct swjdp_common *swjdp,
 229                 uint8_t *buffer, int count, uint32_t address);
 230
 231 /* Initialisation of the debug system, power domains and registers */
 232 int ahbap_debugport_init(struct swjdp_common *swjdp);
 233
 234
 235 /* Commands for user dap access */
 236 int dap_info_command(struct command_context *cmd_ctx,
 237                 struct swjdp_common *swjdp, int apsel);
 238
 239 #define DAP_COMMAND_HANDLER(name) \
 240                 COMMAND_HELPER(name, struct swjdp_common *swjdp)
 241 DAP_COMMAND_HANDLER(dap_baseaddr_command);
 242 DAP_COMMAND_HANDLER(dap_memaccess_command);
 243 DAP_COMMAND_HANDLER(dap_apsel_command);
 244 DAP_COMMAND_HANDLER(dap_apid_command);
 245
 246 #endif