e3d053c98295dcc1b5ca2feaaace593b2add9a92
[openocd.git] / src / target / armv4_5.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by √ėyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV4_5_H
27 #define ARMV4_5_H
28
29 #include "target.h"
30
31 typedef enum armv4_5_mode
32 {
33 ARMV4_5_MODE_USR = 16,
34 ARMV4_5_MODE_FIQ = 17,
35 ARMV4_5_MODE_IRQ = 18,
36 ARMV4_5_MODE_SVC = 19,
37 ARMV4_5_MODE_ABT = 23,
38 ARM_MODE_MON = 26,
39 ARMV4_5_MODE_UND = 27,
40 ARMV4_5_MODE_SYS = 31,
41 ARMV4_5_MODE_ANY = -1
42 } armv4_5_mode_t;
43
44 const char *arm_mode_name(unsigned psr_mode);
45 bool is_arm_mode(unsigned psr_mode);
46
47 int armv4_5_mode_to_number(enum armv4_5_mode mode);
48 enum armv4_5_mode armv4_5_number_to_mode(int number);
49
50 typedef enum armv4_5_state
51 {
52 ARMV4_5_STATE_ARM,
53 ARMV4_5_STATE_THUMB,
54 ARMV4_5_STATE_JAZELLE,
55 } armv4_5_state_t;
56
57 extern char* armv4_5_state_strings[];
58
59 extern const int armv4_5_core_reg_map[8][17];
60
61 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
62 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
63
64 /* offsets into armv4_5 core register cache */
65 enum
66 {
67 ARMV4_5_CPSR = 31,
68 ARMV4_5_SPSR_FIQ = 32,
69 ARMV4_5_SPSR_IRQ = 33,
70 ARMV4_5_SPSR_SVC = 34,
71 ARMV4_5_SPSR_ABT = 35,
72 ARMV4_5_SPSR_UND = 36,
73 ARM_SPSR_MON = 39,
74 };
75
76 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
77
78 /* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
79 #define armv4_5_common_s arm
80
81 /**
82 * Represents a generic ARM core, with standard application registers.
83 *
84 * There are sixteen application registers (including PC, SP, LR) and a PSR.
85 * Cortex-M series cores do not support as many core states or shadowed
86 * registers as traditional ARM cores, and only support Thumb2 instructions.
87 */
88 struct arm
89 {
90 int common_magic;
91 struct reg_cache *core_cache;
92
93 /**
94 * Indicates what registers are in the ARM state core register set.
95 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
96 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
97 * more registers are shadowed, for "Secure Monitor" mode.
98 */
99 enum armv4_5_mode core_type;
100
101 enum armv4_5_mode core_mode;
102 enum armv4_5_state core_state;
103
104 /** Flag reporting unavailability of the BKPT instruction. */
105 bool is_armv4;
106
107 /** Handle for the Embedded Trace Module, if one is present. */
108 struct etm_context *etm;
109
110 int (*full_context)(struct target *target);
111 int (*read_core_reg)(struct target *target,
112 int num, enum armv4_5_mode mode);
113 int (*write_core_reg)(struct target *target,
114 int num, enum armv4_5_mode mode, uint32_t value);
115 void *arch_info;
116 };
117
118 #define target_to_armv4_5 target_to_arm
119
120 /** Convert target handle to generic ARM target state handle. */
121 static inline struct arm *target_to_arm(struct target *target)
122 {
123 return target->arch_info;
124 }
125
126 static inline bool is_arm(struct arm *arm)
127 {
128 return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
129 }
130
131 struct armv4_5_algorithm
132 {
133 int common_magic;
134
135 enum armv4_5_mode core_mode;
136 enum armv4_5_state core_state;
137 };
138
139 struct armv4_5_core_reg
140 {
141 int num;
142 enum armv4_5_mode mode;
143 struct target *target;
144 struct arm *armv4_5_common;
145 };
146
147 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
148 struct arm *armv4_5_common);
149
150 int armv4_5_arch_state(struct target *target);
151 int armv4_5_get_gdb_reg_list(struct target *target,
152 struct reg **reg_list[], int *reg_list_size);
153
154 int armv4_5_register_commands(struct command_context *cmd_ctx);
155 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
156
157 int armv4_5_run_algorithm(struct target *target,
158 int num_mem_params, struct mem_param *mem_params,
159 int num_reg_params, struct reg_param *reg_params,
160 uint32_t entry_point, uint32_t exit_point,
161 int timeout_ms, void *arch_info);
162
163 int armv4_5_invalidate_core_regs(struct target *target);
164
165 int arm_checksum_memory(struct target *target,
166 uint32_t address, uint32_t count, uint32_t *checksum);
167 int arm_blank_check_memory(struct target *target,
168 uint32_t address, uint32_t count, uint32_t *blank);
169
170 extern struct reg arm_gdb_dummy_fp_reg;
171 extern struct reg arm_gdb_dummy_fps_reg;
172
173 /* ARM mode instructions
174 */
175
176 /* Store multiple increment after
177 * Rn: base register
178 * List: for each bit in list: store register
179 * S: in priviledged mode: store user-mode registers
180 * W = 1: update the base register. W = 0: leave the base register untouched
181 */
182 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
183
184 /* Load multiple increment after
185 * Rn: base register
186 * List: for each bit in list: store register
187 * S: in priviledged mode: store user-mode registers
188 * W = 1: update the base register. W = 0: leave the base register untouched
189 */
190 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
191
192 /* MOV r8, r8 */
193 #define ARMV4_5_NOP (0xe1a08008)
194
195 /* Move PSR to general purpose register
196 * R = 1: SPSR R = 0: CPSR
197 * Rn: target register
198 */
199 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
200
201 /* Store register
202 * Rd: register to store
203 * Rn: base register
204 */
205 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
206
207 /* Load register
208 * Rd: register to load
209 * Rn: base register
210 */
211 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
212
213 /* Move general purpose register to PSR
214 * R = 1: SPSR R = 0: CPSR
215 * Field: Field mask
216 * 1: control field 2: extension field 4: status field 8: flags field
217 * Rm: source register
218 */
219 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
220 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
221
222 /* Load Register Halfword Immediate Post-Index
223 * Rd: register to load
224 * Rn: base register
225 */
226 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
227
228 /* Load Register Byte Immediate Post-Index
229 * Rd: register to load
230 * Rn: base register
231 */
232 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
233
234 /* Store register Halfword Immediate Post-Index
235 * Rd: register to store
236 * Rn: base register
237 */
238 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
239
240 /* Store register Byte Immediate Post-Index
241 * Rd: register to store
242 * Rn: base register
243 */
244 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
245
246 /* Branch (and Link)
247 * Im: Branch target (left-shifted by 2 bits, added to PC)
248 * L: 1: branch and link 0: branch only
249 */
250 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
251
252 /* Branch and exchange (ARM state)
253 * Rm: register holding branch target address
254 */
255 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
256
257 /* Move to ARM register from coprocessor
258 * CP: Coprocessor number
259 * op1: Coprocessor opcode
260 * Rd: destination register
261 * CRn: first coprocessor operand
262 * CRm: second coprocessor operand
263 * op2: Second coprocessor opcode
264 */
265 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
266
267 /* Move to coprocessor from ARM register
268 * CP: Coprocessor number
269 * op1: Coprocessor opcode
270 * Rd: destination register
271 * CRn: first coprocessor operand
272 * CRm: second coprocessor operand
273 * op2: Second coprocessor opcode
274 */
275 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
276
277 /* Breakpoint instruction (ARMv5)
278 * Im: 16-bit immediate
279 */
280 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
281
282
283 /* Thumb mode instructions
284 */
285
286 /* Store register (Thumb mode)
287 * Rd: source register
288 * Rn: base register
289 */
290 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
291
292 /* Load register (Thumb state)
293 * Rd: destination register
294 * Rn: base register
295 */
296 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
297
298 /* Load multiple (Thumb state)
299 * Rn: base register
300 * List: for each bit in list: store register
301 */
302 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
303
304 /* Load register with PC relative addressing
305 * Rd: register to load
306 */
307 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
308
309 /* Move hi register (Thumb mode)
310 * Rd: destination register
311 * Rm: source register
312 */
313 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
314
315 /* No operation (Thumb mode)
316 */
317 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
318
319 /* Move immediate to register (Thumb state)
320 * Rd: destination register
321 * Im: 8-bit immediate value
322 */
323 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
324
325 /* Branch and Exchange
326 * Rm: register containing branch target
327 */
328 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
329
330 /* Branch (Thumb state)
331 * Imm: Branch target
332 */
333 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
334
335 /* Breakpoint instruction (ARMv5) (Thumb state)
336 * Im: 8-bit immediate
337 */
338 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
339
340 /* build basic mrc/mcr opcode */
341
342 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
343 {
344 uint32_t t = 0;
345 t|=op1<<21;
346 t|=op2<<5;
347 t|=CRn<<16;
348 t|=CRm<<0;
349 return t;
350 }
351
352 #endif /* ARMV4_5_H */

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