1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
18 ***************************************************************************/
23 #include "arm_adi_v5.h"
24 #include "armv7a_cache.h"
26 #include "armv4_5_mmu.h"
27 #include "armv4_5_cache.h"
35 #define ARMV7_COMMON_MAGIC 0x0A450999
37 /* VA to PA translation operations opc2 values*/
46 /* L210/L220 cache controller support */
47 struct armv7a_l2x_cache
{
52 struct armv7a_cachesize
{
54 /* cache dimensionning */
56 uint32_t associativity
;
59 /* info for set way operation on cache */
66 /* information about one architecture cache at any level */
67 struct armv7a_arch_cache
{
68 int ctype
; /* cache type, CLIDR encoding */
69 struct armv7a_cachesize d_u_size
; /* data cache */
70 struct armv7a_cachesize i_size
; /* instruction cache */
73 /* common cache information */
74 struct armv7a_cache_common
{
75 int info
; /* -1 invalid, else valid */
76 int loc
; /* level of coherency */
77 uint32_t dminline
; /* minimum d-cache linelen */
78 uint32_t iminline
; /* minimum i-cache linelen */
79 struct armv7a_arch_cache arch
[6]; /* cache info, L1 - L7 */
81 int d_u_cache_enabled
;
82 int auto_cache_enabled
; /* openocd automatic
84 /* outer unified cache if some */
86 int (*flush_all_data_cache
)(struct target
*target
);
89 struct armv7a_mmu_common
{
90 /* following field mmu working way */
91 int32_t cached
; /* 0: not initialized, 1: initialized */
92 uint32_t ttbcr
; /* cache for ttbcr register */
93 uint32_t ttbr_mask
[2];
94 uint32_t ttbr_range
[2];
96 int (*read_physical_memory
)(struct target
*target
, uint32_t address
, uint32_t size
,
97 uint32_t count
, uint8_t *buffer
);
98 struct armv7a_cache_common armv7a_cache
;
102 struct armv7a_common
{
105 struct reg_cache
*core_cache
;
107 /* Core Debug Unit */
110 struct adiv5_ap
*debug_ap
;
111 struct adiv5_ap
*memory_ap
;
112 bool memory_ap_available
;
114 uint8_t multi_processor_system
;
122 uint32_t implementor
;
124 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
125 struct armv7a_mmu_common armv7a_mmu
;
127 int (*examine_debug_reason
)(struct target
*target
);
128 int (*post_debug_entry
)(struct target
*target
);
130 void (*pre_restore_context
)(struct target
*target
);
133 static inline struct armv7a_common
*
134 target_to_armv7a(struct target
*target
)
136 return container_of(target
->arch_info
, struct armv7a_common
, arm
);
139 /* register offsets from armv7a.debug_base */
141 /* See ARMv7a arch spec section C10.2 */
142 #define CPUDBG_DIDR 0x000
144 /* See ARMv7a arch spec section C10.3 */
145 #define CPUDBG_WFAR 0x018
146 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
147 #define CPUDBG_DSCR 0x088
148 #define CPUDBG_DRCR 0x090
149 #define CPUDBG_PRCR 0x310
150 #define CPUDBG_PRSR 0x314
152 /* See ARMv7a arch spec section C10.4 */
153 #define CPUDBG_DTRRX 0x080
154 #define CPUDBG_ITR 0x084
155 #define CPUDBG_DTRTX 0x08c
157 /* See ARMv7a arch spec section C10.5 */
158 #define CPUDBG_BVR_BASE 0x100
159 #define CPUDBG_BCR_BASE 0x140
160 #define CPUDBG_WVR_BASE 0x180
161 #define CPUDBG_WCR_BASE 0x1C0
162 #define CPUDBG_VCR 0x01C
164 /* See ARMv7a arch spec section C10.6 */
165 #define CPUDBG_OSLAR 0x300
166 #define CPUDBG_OSLSR 0x304
167 #define CPUDBG_OSSRR 0x308
168 #define CPUDBG_ECR 0x024
170 /* See ARMv7a arch spec section C10.7 */
171 #define CPUDBG_DSCCR 0x028
172 #define CPUDBG_DSMCR 0x02C
174 /* See ARMv7a arch spec section C10.8 */
175 #define CPUDBG_AUTHSTATUS 0xFB8
177 int armv7a_arch_state(struct target
*target
);
178 int armv7a_identify_cache(struct target
*target
);
179 int armv7a_init_arch_info(struct target
*target
, struct armv7a_common
*armv7a
);
180 int armv7a_mmu_translate_va_pa(struct target
*target
, uint32_t va
,
181 uint32_t *val
, int meminfo
);
182 int armv7a_mmu_translate_va(struct target
*target
, uint32_t va
, uint32_t *val
);
184 int armv7a_handle_cache_info_command(struct command_context
*cmd_ctx
,
185 struct armv7a_cache_common
*armv7a_cache
);
187 extern const struct command_registration armv7a_command_handlers
[];
189 #endif /* ARMV4_5_H */
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