1 /***************************************************************************
2 * Copyright (C) 2015 by Oleksij Rempel *
3 * linux@rempel-privat.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include "jtag/interface.h"
26 #include "armv7a_cache.h"
27 #include <helper/time_support.h>
29 #include "target_type.h"
31 static int arm7a_l2x_sanity_check(struct target
*target
)
33 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
34 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
35 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
37 if (target
->state
!= TARGET_HALTED
) {
38 LOG_ERROR("%s: target not halted", __func__
);
39 return ERROR_TARGET_NOT_HALTED
;
42 if (!l2x_cache
|| !l2x_cache
->base
) {
43 LOG_DEBUG("l2x is not configured!");
50 * clean and invalidate complete l2x cache
52 int arm7a_l2x_flush_all_data(struct target
*target
)
54 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
55 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
56 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
60 retval
= arm7a_l2x_sanity_check(target
);
64 l2_way_val
= (1 << l2x_cache
->way
) - 1;
66 return target_write_phys_memory(target
,
67 l2x_cache
->base
+ L2X0_CLEAN_INV_WAY
,
68 4, 1, (uint8_t *)&l2_way_val
);
71 int armv7a_l2x_cache_flush_virt(struct target
*target
, uint32_t virt
,
74 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
75 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
76 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
77 /* FIXME: different controllers have different linelen? */
78 uint32_t i
, linelen
= 32;
81 retval
= arm7a_l2x_sanity_check(target
);
85 for (i
= 0; i
< size
; i
+= linelen
) {
86 uint32_t pa
, offs
= virt
+ i
;
88 /* FIXME: use less verbose virt2phys? */
89 retval
= target
->type
->virt2phys(target
, offs
, &pa
);
90 if (retval
!= ERROR_OK
)
93 retval
= target_write_phys_memory(target
,
94 l2x_cache
->base
+ L2X0_CLEAN_INV_LINE_PA
,
95 4, 1, (uint8_t *)&pa
);
96 if (retval
!= ERROR_OK
)
102 LOG_ERROR("d-cache invalidate failed");
107 static int armv7a_l2x_cache_inval_virt(struct target
*target
, uint32_t virt
,
110 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
111 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
112 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
113 /* FIXME: different controllers have different linelen */
114 uint32_t i
, linelen
= 32;
117 retval
= arm7a_l2x_sanity_check(target
);
121 for (i
= 0; i
< size
; i
+= linelen
) {
122 uint32_t pa
, offs
= virt
+ i
;
124 /* FIXME: use less verbose virt2phys? */
125 retval
= target
->type
->virt2phys(target
, offs
, &pa
);
126 if (retval
!= ERROR_OK
)
129 retval
= target_write_phys_memory(target
,
130 l2x_cache
->base
+ L2X0_INV_LINE_PA
,
131 4, 1, (uint8_t *)&pa
);
132 if (retval
!= ERROR_OK
)
138 LOG_ERROR("d-cache invalidate failed");
143 static int armv7a_l2x_cache_clean_virt(struct target
*target
, uint32_t virt
,
146 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
147 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
148 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
149 /* FIXME: different controllers have different linelen */
150 uint32_t i
, linelen
= 32;
153 retval
= arm7a_l2x_sanity_check(target
);
157 for (i
= 0; i
< size
; i
+= linelen
) {
158 uint32_t pa
, offs
= virt
+ i
;
160 /* FIXME: use less verbose virt2phys? */
161 retval
= target
->type
->virt2phys(target
, offs
, &pa
);
162 if (retval
!= ERROR_OK
)
165 retval
= target_write_phys_memory(target
,
166 l2x_cache
->base
+ L2X0_CLEAN_LINE_PA
,
167 4, 1, (uint8_t *)&pa
);
168 if (retval
!= ERROR_OK
)
174 LOG_ERROR("d-cache invalidate failed");
179 static int arm7a_handle_l2x_cache_info_command(struct command_context
*cmd_ctx
,
180 struct armv7a_cache_common
*armv7a_cache
)
182 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
183 (armv7a_cache
->outer_cache
);
185 if (armv7a_cache
->info
== -1) {
186 command_print(cmd_ctx
, "cache not yet identified");
190 command_print(cmd_ctx
,
191 "L2 unified cache Base Address 0x%" PRIx32
", %" PRId32
" ways",
192 l2x_cache
->base
, l2x_cache
->way
);
197 static int armv7a_l2x_cache_init(struct target
*target
, uint32_t base
, uint32_t way
)
199 struct armv7a_l2x_cache
*l2x_cache
;
200 struct target_list
*head
= target
->head
;
203 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
204 if (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
) {
205 LOG_ERROR("L2 cache was already initialised\n");
209 l2x_cache
= calloc(1, sizeof(struct armv7a_l2x_cache
));
210 l2x_cache
->base
= base
;
211 l2x_cache
->way
= way
;
212 armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
= l2x_cache
;
214 /* initialize all targets in this cluster (smp target)
215 * l2 cache must be configured after smp declaration */
216 while (head
!= (struct target_list
*)NULL
) {
218 if (curr
!= target
) {
219 armv7a
= target_to_armv7a(curr
);
220 if (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
) {
221 LOG_ERROR("smp target : cache l2 already initialized\n");
224 armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
= l2x_cache
;
231 COMMAND_HANDLER(arm7a_l2x_cache_info_command
)
233 struct target
*target
= get_current_target(CMD_CTX
);
234 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
237 retval
= arm7a_l2x_sanity_check(target
);
241 return arm7a_handle_l2x_cache_info_command(CMD_CTX
,
242 &armv7a
->armv7a_mmu
.armv7a_cache
);
245 COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command
)
247 struct target
*target
= get_current_target(CMD_CTX
);
249 return arm7a_l2x_flush_all_data(target
);
252 COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd
)
254 struct target
*target
= get_current_target(CMD_CTX
);
257 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
258 return ERROR_COMMAND_SYNTAX_ERROR
;
261 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
265 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
267 return armv7a_l2x_cache_flush_virt(target
, virt
, size
);
270 COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd
)
272 struct target
*target
= get_current_target(CMD_CTX
);
275 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
276 return ERROR_COMMAND_SYNTAX_ERROR
;
279 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
283 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
285 return armv7a_l2x_cache_inval_virt(target
, virt
, size
);
288 COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd
)
290 struct target
*target
= get_current_target(CMD_CTX
);
293 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
294 return ERROR_COMMAND_SYNTAX_ERROR
;
297 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
301 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
303 return armv7a_l2x_cache_clean_virt(target
, virt
, size
);
306 /* FIXME: should we configure way size? or controller type? */
307 COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd
)
309 struct target
*target
= get_current_target(CMD_CTX
);
313 return ERROR_COMMAND_SYNTAX_ERROR
;
315 /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
316 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], base
);
317 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], way
);
319 /* AP address is in bits 31:24 of DP_SELECT */
320 return armv7a_l2x_cache_init(target
, base
, way
);
323 static const struct command_registration arm7a_l2x_cache_commands
[] = {
326 .handler
= armv7a_l2x_cache_conf_cmd
,
328 .help
= "configure l2x cache ",
329 .usage
= "<base_addr> <number_of_way>",
333 .handler
= arm7a_l2x_cache_info_command
,
335 .help
= "print cache realted information",
340 .handler
= arm7a_l2x_cache_flush_all_command
,
342 .help
= "flush complete l2x cache",
347 .handler
= arm7a_l2x_cache_flush_virt_cmd
,
349 .help
= "flush (clean and invalidate) l2x cache by virtual address offset and range size",
350 .usage
= "<virt_addr> [size]",
354 .handler
= arm7a_l2x_cache_inval_virt_cmd
,
356 .help
= "invalidate l2x cache by virtual address offset and range size",
357 .usage
= "<virt_addr> [size]",
361 .handler
= arm7a_l2x_cache_clean_virt_cmd
,
363 .help
= "clean l2x cache by virtual address address offset and range size",
364 .usage
= "<virt_addr> [size]",
366 COMMAND_REGISTRATION_DONE
369 const struct command_registration arm7a_l2x_cache_command_handler
[] = {
373 .help
= "l2x cache command group",
375 .chain
= arm7a_l2x_cache_commands
,
377 COMMAND_REGISTRATION_DONE
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)