1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
33 #include "replacements.h"
46 #define _DEBUG_INSTRUCTION_EXECUTION_
49 char* armv7m_mode_strings
[] =
51 "Thread", "Thread (User)", "Handler",
54 char* armv7m_exception_strings
[] =
56 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
57 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
60 char* armv7m_core_reg_list
[] =
62 /* Registers accessed through core debug */
63 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
66 /* Registers accessed through special reg 20 */
67 "primask", "basepri", "faultmask", "control"
70 u8 armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
72 reg_t armv7m_gdb_dummy_fp_reg
=
74 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
77 u8 armv7m_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
79 reg_t armv7m_gdb_dummy_fps_reg
=
81 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
84 #ifdef ARMV7_GDB_HACKS
85 u8 armv7m_gdb_dummy_cpsr_value
[] = {0, 0, 0, 0};
87 reg_t armv7m_gdb_dummy_cpsr_reg
=
89 "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value
, 0, 1, 32, NULL
, 0, NULL
, 0
93 armv7m_core_reg_t armv7m_core_reg_list_arch_info
[] =
95 /* CORE_GP are accesible using the core debug registers */
96 {0, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
97 {1, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
98 {2, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
99 {3, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
100 {4, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
101 {5, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
102 {6, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
103 {7, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
104 {8, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
105 {9, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
106 {10, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
107 {11, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
108 {12, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
109 {13, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
110 {14, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
111 {15, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
113 {16, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* xPSR */
114 {17, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* MSP */
115 {18, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PSP */
117 /* CORE_SP are accesible using coreregister 20 */
118 {19, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PRIMASK */
119 {20, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* BASEPRI */
120 {21, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* FAULTMASK */
121 {22, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
} /* CONTROL */
124 int armv7m_core_reg_arch_type
= -1;
125 int armv7m_dummy_core_reg_arch_type
= -1;
127 int armv7m_restore_context(target_t
*target
)
131 /* get pointers to arch-specific information */
132 armv7m_common_t
*armv7m
= target
->arch_info
;
136 if (armv7m
->pre_restore_context
)
137 armv7m
->pre_restore_context(target
);
139 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
141 if (armv7m
->core_cache
->reg_list
[i
].dirty
)
143 armv7m
->write_core_reg(target
, i
);
147 if (armv7m
->post_restore_context
)
148 armv7m
->post_restore_context(target
);
153 /* Core state functions */
154 char *armv7m_exception_string(int number
)
156 static char enamebuf
[32];
158 if ((number
< 0) | (number
> 511))
159 return "Invalid exception";
161 return armv7m_exception_strings
[number
];
162 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
166 int armv7m_get_core_reg(reg_t
*reg
)
169 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
170 target_t
*target
= armv7m_reg
->target
;
171 armv7m_common_t
*armv7m_target
= target
->arch_info
;
173 if (target
->state
!= TARGET_HALTED
)
175 return ERROR_TARGET_NOT_HALTED
;
178 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
183 int armv7m_set_core_reg(reg_t
*reg
, u8
*buf
)
185 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
186 target_t
*target
= armv7m_reg
->target
;
187 u32 value
= buf_get_u32(buf
, 0, 32);
189 if (target
->state
!= TARGET_HALTED
)
191 return ERROR_TARGET_NOT_HALTED
;
194 buf_set_u32(reg
->value
, 0, 32, value
);
201 int armv7m_read_core_reg(struct target_s
*target
, int num
)
205 armv7m_core_reg_t
* armv7m_core_reg
;
207 /* get pointers to arch-specific information */
208 armv7m_common_t
*armv7m
= target
->arch_info
;
210 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
211 return ERROR_INVALID_ARGUMENTS
;
213 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
214 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
215 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
216 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
217 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
222 int armv7m_write_core_reg(struct target_s
*target
, int num
)
226 armv7m_core_reg_t
*armv7m_core_reg
;
228 /* get pointers to arch-specific information */
229 armv7m_common_t
*armv7m
= target
->arch_info
;
231 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
232 return ERROR_INVALID_ARGUMENTS
;
234 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
235 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
236 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
237 if (retval
!= ERROR_OK
)
239 LOG_ERROR("JTAG failure");
240 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
241 return ERROR_JTAG_DEVICE_ERROR
;
243 LOG_DEBUG("write core reg %i value 0x%x", num
, reg_value
);
244 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
245 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
250 int armv7m_invalidate_core_regs(target_t
*target
)
252 /* get pointers to arch-specific information */
253 armv7m_common_t
*armv7m
= target
->arch_info
;
256 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
258 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
259 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
265 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
267 /* get pointers to arch-specific information */
268 armv7m_common_t
*armv7m
= target
->arch_info
;
272 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
274 for (i
= 0; i
< 16; i
++)
276 (*reg_list
)[i
] = &armv7m
->core_cache
->reg_list
[i
];
279 for (i
= 16; i
< 24; i
++)
281 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
284 (*reg_list
)[24] = &armv7m_gdb_dummy_fps_reg
;
286 #ifdef ARMV7_GDB_HACKS
287 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
288 (*reg_list
)[25] = &armv7m_gdb_dummy_cpsr_reg
;
290 /* ARMV7M is always in thumb mode, try to make GDB understand this
291 * if it does not support this arch */
292 armv7m
->core_cache
->reg_list
[15].value
[0] |= 1;
294 (*reg_list
)[25] = &armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
];
300 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
302 /* get pointers to arch-specific information */
303 armv7m_common_t
*armv7m
= target
->arch_info
;
304 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
305 enum armv7m_mode core_mode
= armv7m
->core_mode
;
306 int retval
= ERROR_OK
;
309 u32 context
[ARMV7NUMCOREREGS
];
311 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
313 LOG_ERROR("current target isn't an ARMV7M target");
314 return ERROR_TARGET_INVALID
;
317 if (target
->state
!= TARGET_HALTED
)
319 LOG_WARNING("target not halted");
320 return ERROR_TARGET_NOT_HALTED
;
323 /* refresh core register cache */
324 /* Not needed if core register cache is always consistent with target process state */
325 for (i
= 0; i
< ARMV7NUMCOREREGS
; i
++)
327 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
328 armv7m
->read_core_reg(target
, i
);
329 context
[i
] = buf_get_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32);
332 for (i
= 0; i
< num_mem_params
; i
++)
334 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
337 for (i
= 0; i
< num_reg_params
; i
++)
339 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
344 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
348 if (reg
->size
!= reg_params
[i
].size
)
350 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
354 regvalue
= buf_get_u32(reg_params
[i
].value
, 0, 32);
355 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
358 if (armv7m_algorithm_info
->core_mode
!= ARMV7M_MODE_ANY
)
360 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info
->core_mode
);
361 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 1, armv7m_algorithm_info
->core_mode
);
362 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].dirty
= 1;
363 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].valid
= 1;
366 /* ARMV7M always runs in Thumb state */
367 if ((retval
= breakpoint_add(target
, exit_point
, 2, BKPT_SOFT
)) != ERROR_OK
)
369 LOG_ERROR("can't add breakpoint to finish algorithm execution");
370 return ERROR_TARGET_FAILURE
;
373 /* This code relies on the target specific resume() and poll()->debug_entry()
374 sequence to write register values to the processor and the read them back */
375 if((retval
= target_resume(target
, 0, entry_point
, 1, 1)) != ERROR_OK
)
379 if((retval
= target_poll(target
)) != ERROR_OK
)
384 if((retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
)) != ERROR_OK
)
388 if (target
->state
!= TARGET_HALTED
)
390 if ((retval
=target_halt(target
))!=ERROR_OK
)
392 if ((retval
=target_wait_state(target
, TARGET_HALTED
, 500))!=ERROR_OK
)
396 return ERROR_TARGET_TIMEOUT
;
400 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
401 if (pc
!= exit_point
)
403 LOG_DEBUG("failed algoritm halted at 0x%x ", pc
);
404 return ERROR_TARGET_TIMEOUT
;
407 breakpoint_remove(target
, exit_point
);
409 /* Read memory values to mem_params[] */
410 for (i
= 0; i
< num_mem_params
; i
++)
412 if (mem_params
[i
].direction
!= PARAM_OUT
)
413 if((retval
= target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
419 /* Copy core register values to reg_params[] */
420 for (i
= 0; i
< num_reg_params
; i
++)
422 if (reg_params
[i
].direction
!= PARAM_OUT
)
424 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
428 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
432 if (reg
->size
!= reg_params
[i
].size
)
434 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
438 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
442 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
444 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m
->core_cache
->reg_list
[i
].name
, context
[i
]);
445 buf_set_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32, context
[i
]);
446 armv7m
->core_cache
->reg_list
[i
].valid
= 1;
447 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
450 armv7m
->core_mode
= core_mode
;
455 int armv7m_arch_state(struct target_s
*target
)
457 /* get pointers to arch-specific information */
458 armv7m_common_t
*armv7m
= target
->arch_info
;
460 LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
461 Jim_Nvp_value2name_simple( nvp_target_debug_reason
,target
->debug_reason
)->name
,
462 armv7m_mode_strings
[armv7m
->core_mode
],
463 armv7m_exception_string(armv7m
->exception_number
),
464 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
465 buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32));
470 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
472 /* get pointers to arch-specific information */
473 armv7m_common_t
*armv7m
= target
->arch_info
;
475 int num_regs
= ARMV7NUMCOREREGS
;
476 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
477 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
478 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
479 armv7m_core_reg_t
*arch_info
= malloc(sizeof(armv7m_core_reg_t
) * num_regs
);
482 if (armv7m_core_reg_arch_type
== -1)
484 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
487 register_init_dummy(&armv7m_gdb_dummy_fps_reg
);
488 #ifdef ARMV7_GDB_HACKS
489 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg
);
491 register_init_dummy(&armv7m_gdb_dummy_fp_reg
);
493 /* Build the process context cache */
494 cache
->name
= "arm v7m registers";
496 cache
->reg_list
= reg_list
;
497 cache
->num_regs
= num_regs
;
499 armv7m
->core_cache
= cache
;
501 for (i
= 0; i
< num_regs
; i
++)
503 arch_info
[i
] = armv7m_core_reg_list_arch_info
[i
];
504 arch_info
[i
].target
= target
;
505 arch_info
[i
].armv7m_common
= armv7m
;
506 reg_list
[i
].name
= armv7m_core_reg_list
[i
];
507 reg_list
[i
].size
= 32;
508 reg_list
[i
].value
= calloc(1, 4);
509 reg_list
[i
].dirty
= 0;
510 reg_list
[i
].valid
= 0;
511 reg_list
[i
].bitfield_desc
= NULL
;
512 reg_list
[i
].num_bitfields
= 0;
513 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
514 reg_list
[i
].arch_info
= &arch_info
[i
];
520 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
522 armv7m_build_reg_cache(target
);
527 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
529 /* register arch-specific functions */
531 target
->arch_info
= armv7m
;
532 armv7m
->read_core_reg
= armv7m_read_core_reg
;
533 armv7m
->write_core_reg
= armv7m_write_core_reg
;
538 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
543 int armv7m_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
545 working_area_t
*crc_algorithm
;
546 armv7m_algorithm_t armv7m_info
;
547 reg_param_t reg_params
[2];
550 u16 cortex_m3_crc_code
[] = {
551 0x4602, /* mov r2, r0 */
552 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
553 0x460B, /* mov r3, r1 */
554 0xF04F, 0x0400, /* mov r4, #0 */
555 0xE013, /* b ncomp */
557 0x5D11, /* ldrb r1, [r2, r4] */
558 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
559 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
561 0xF04F, 0x0500, /* mov r5, #0 */
563 0x2800, /* cmp r0, #0 */
564 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
565 0xF105, 0x0501, /* add r5, r5, #1 */
566 0x4630, /* mov r0, r6 */
568 0xEA86, 0x0007, /* eor r0, r6, r7 */
569 0x2D08, /* cmp r5, #8 */
570 0xD1F4, /* bne loop */
572 0xF104, 0x0401, /* add r4, r4, #1 */
574 0x429C, /* cmp r4, r3 */
575 0xD1E9, /* bne nbyte */
578 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
583 if (target_alloc_working_area(target
, sizeof(cortex_m3_crc_code
), &crc_algorithm
) != ERROR_OK
)
585 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
588 /* convert flash writing code into a buffer in target endianness */
589 for (i
= 0; i
< (sizeof(cortex_m3_crc_code
)/sizeof(u16
)); i
++)
590 if((retval
= target_write_u16(target
, crc_algorithm
->address
+ i
*sizeof(u16
), cortex_m3_crc_code
[i
])) != ERROR_OK
)
595 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
596 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
598 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
599 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
601 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
602 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
604 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 2, reg_params
,
605 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(cortex_m3_crc_code
)-6), 20000, &armv7m_info
)) != ERROR_OK
)
607 LOG_ERROR("error executing cortex_m3 crc algorithm");
608 destroy_reg_param(®_params
[0]);
609 destroy_reg_param(®_params
[1]);
610 target_free_working_area(target
, crc_algorithm
);
614 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
616 destroy_reg_param(®_params
[0]);
617 destroy_reg_param(®_params
[1]);
619 target_free_working_area(target
, crc_algorithm
);
624 int armv7m_blank_check_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* blank
)
626 working_area_t
*erase_check_algorithm
;
627 reg_param_t reg_params
[3];
628 armv7m_algorithm_t armv7m_info
;
632 u16 erase_check_code
[] =
635 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
636 0xEA02, 0x0203, /* and r2, r2, r3 */
637 0x3901, /* subs r1, r1, #1 */
638 0xD1F9, /* bne loop */
643 /* make sure we have a working area */
644 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
646 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
649 /* convert flash writing code into a buffer in target endianness */
650 for (i
= 0; i
< (sizeof(erase_check_code
)/sizeof(u16
)); i
++)
651 target_write_u16(target
, erase_check_algorithm
->address
+ i
*sizeof(u16
), erase_check_code
[i
]);
653 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
654 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
656 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
657 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
659 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
660 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
662 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
663 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
665 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
,
666 erase_check_algorithm
->address
, erase_check_algorithm
->address
+ (sizeof(erase_check_code
)-2), 10000, &armv7m_info
)) != ERROR_OK
)
668 destroy_reg_param(®_params
[0]);
669 destroy_reg_param(®_params
[1]);
670 destroy_reg_param(®_params
[2]);
671 target_free_working_area(target
, erase_check_algorithm
);
675 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
677 destroy_reg_param(®_params
[0]);
678 destroy_reg_param(®_params
[1]);
679 destroy_reg_param(®_params
[2]);
681 target_free_working_area(target
, erase_check_algorithm
);
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